501 lines
13 KiB
C
501 lines
13 KiB
C
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/*
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* IMX SPI Controller
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*
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* Copyright (c) 2016 Jean-Christophe Dubois <jcd@tribudubois.net>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#include "qemu/osdep.h"
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#include "hw/irq.h"
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#include "hw/ssi/imx_spi.h"
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#include "migration/vmstate.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#ifndef DEBUG_IMX_SPI
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#define DEBUG_IMX_SPI 0
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#endif
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#define DPRINTF(fmt, args...) \
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do { \
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if (DEBUG_IMX_SPI) { \
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fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_SPI, \
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__func__, ##args); \
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} \
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} while (0)
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static const char *imx_spi_reg_name(uint32_t reg)
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{
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static char unknown[20];
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switch (reg) {
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case ECSPI_RXDATA:
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return "ECSPI_RXDATA";
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case ECSPI_TXDATA:
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return "ECSPI_TXDATA";
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case ECSPI_CONREG:
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return "ECSPI_CONREG";
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case ECSPI_CONFIGREG:
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return "ECSPI_CONFIGREG";
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case ECSPI_INTREG:
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return "ECSPI_INTREG";
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case ECSPI_DMAREG:
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return "ECSPI_DMAREG";
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case ECSPI_STATREG:
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return "ECSPI_STATREG";
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case ECSPI_PERIODREG:
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return "ECSPI_PERIODREG";
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case ECSPI_TESTREG:
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return "ECSPI_TESTREG";
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case ECSPI_MSGDATA:
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return "ECSPI_MSGDATA";
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default:
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sprintf(unknown, "%u ?", reg);
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return unknown;
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}
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}
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static const VMStateDescription vmstate_imx_spi = {
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.name = TYPE_IMX_SPI,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_FIFO32(tx_fifo, IMXSPIState),
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VMSTATE_FIFO32(rx_fifo, IMXSPIState),
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VMSTATE_INT16(burst_length, IMXSPIState),
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VMSTATE_UINT32_ARRAY(regs, IMXSPIState, ECSPI_MAX),
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VMSTATE_END_OF_LIST()
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},
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};
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static void imx_spi_txfifo_reset(IMXSPIState *s)
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{
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fifo32_reset(&s->tx_fifo);
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s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TE;
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s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_TF;
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}
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static void imx_spi_rxfifo_reset(IMXSPIState *s)
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{
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fifo32_reset(&s->rx_fifo);
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s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RR;
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s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RF;
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s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RO;
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}
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static void imx_spi_update_irq(IMXSPIState *s)
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{
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int level;
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if (fifo32_is_empty(&s->rx_fifo)) {
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s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RR;
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} else {
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s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RR;
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}
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if (fifo32_is_full(&s->rx_fifo)) {
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s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RF;
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} else {
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s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RF;
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}
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if (fifo32_is_empty(&s->tx_fifo)) {
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s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TE;
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} else {
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s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_TE;
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}
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if (fifo32_is_full(&s->tx_fifo)) {
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s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TF;
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} else {
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s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_TF;
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}
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level = s->regs[ECSPI_STATREG] & s->regs[ECSPI_INTREG] ? 1 : 0;
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qemu_set_irq(s->irq, level);
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DPRINTF("IRQ level is %d\n", level);
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}
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static uint8_t imx_spi_selected_channel(IMXSPIState *s)
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{
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return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_CHANNEL_SELECT);
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}
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static uint32_t imx_spi_burst_length(IMXSPIState *s)
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{
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uint32_t burst;
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burst = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1;
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if (burst % 8) {
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burst = ROUND_UP(burst, 8);
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}
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return burst;
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}
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static bool imx_spi_is_enabled(IMXSPIState *s)
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{
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return s->regs[ECSPI_CONREG] & ECSPI_CONREG_EN;
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}
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static bool imx_spi_channel_is_master(IMXSPIState *s)
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{
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uint8_t mode = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_CHANNEL_MODE);
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return (mode & (1 << imx_spi_selected_channel(s))) ? true : false;
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}
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static bool imx_spi_is_multiple_master_burst(IMXSPIState *s)
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{
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uint8_t wave = EXTRACT(s->regs[ECSPI_CONFIGREG], ECSPI_CONFIGREG_SS_CTL);
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return imx_spi_channel_is_master(s) &&
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!(s->regs[ECSPI_CONREG] & ECSPI_CONREG_SMC) &&
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((wave & (1 << imx_spi_selected_channel(s))) ? true : false);
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}
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static void imx_spi_flush_txfifo(IMXSPIState *s)
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{
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uint32_t tx;
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uint32_t rx;
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DPRINTF("Begin: TX Fifo Size = %d, RX Fifo Size = %d\n",
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fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo));
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while (!fifo32_is_empty(&s->tx_fifo)) {
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int tx_burst = 0;
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if (s->burst_length <= 0) {
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s->burst_length = imx_spi_burst_length(s);
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DPRINTF("Burst length = %d\n", s->burst_length);
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if (imx_spi_is_multiple_master_burst(s)) {
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s->regs[ECSPI_CONREG] |= ECSPI_CONREG_XCH;
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}
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}
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tx = fifo32_pop(&s->tx_fifo);
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DPRINTF("data tx:0x%08x\n", tx);
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tx_burst = (s->burst_length % 32) ? : 32;
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rx = 0;
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while (tx_burst > 0) {
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uint8_t byte = tx >> (tx_burst - 8);
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DPRINTF("writing 0x%02x\n", (uint32_t)byte);
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/* We need to write one byte at a time */
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byte = ssi_transfer(s->bus, byte);
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DPRINTF("0x%02x read\n", (uint32_t)byte);
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rx = (rx << 8) | byte;
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/* Remove 8 bits from the actual burst */
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tx_burst -= 8;
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s->burst_length -= 8;
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}
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DPRINTF("data rx:0x%08x\n", rx);
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if (fifo32_is_full(&s->rx_fifo)) {
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s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RO;
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} else {
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fifo32_push(&s->rx_fifo, rx);
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}
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if (s->burst_length <= 0) {
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if (!imx_spi_is_multiple_master_burst(s)) {
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s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TC;
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break;
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}
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}
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}
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if (fifo32_is_empty(&s->tx_fifo)) {
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s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TC;
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s->regs[ECSPI_CONREG] &= ~ECSPI_CONREG_XCH;
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}
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/* TODO: We should also use TDR and RDR bits */
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DPRINTF("End: TX Fifo Size = %d, RX Fifo Size = %d\n",
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fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo));
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}
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static void imx_spi_common_reset(IMXSPIState *s)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(s->regs); i++) {
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switch (i) {
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case ECSPI_CONREG:
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/* CONREG is not updated on soft reset */
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break;
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case ECSPI_STATREG:
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s->regs[i] = 0x00000003;
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break;
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default:
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s->regs[i] = 0;
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break;
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}
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}
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imx_spi_rxfifo_reset(s);
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imx_spi_txfifo_reset(s);
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s->burst_length = 0;
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}
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static void imx_spi_soft_reset(IMXSPIState *s)
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{
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int i;
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imx_spi_common_reset(s);
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imx_spi_update_irq(s);
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for (i = 0; i < ECSPI_NUM_CS; i++) {
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qemu_set_irq(s->cs_lines[i], 1);
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}
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}
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static void imx_spi_reset(DeviceState *dev)
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{
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IMXSPIState *s = IMX_SPI(dev);
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imx_spi_common_reset(s);
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s->regs[ECSPI_CONREG] = 0;
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}
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static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size)
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{
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uint32_t value = 0;
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IMXSPIState *s = opaque;
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uint32_t index = offset >> 2;
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if (index >= ECSPI_MAX) {
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
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HWADDR_PRIx "\n", TYPE_IMX_SPI, __func__, offset);
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return 0;
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}
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value = s->regs[index];
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if (imx_spi_is_enabled(s)) {
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switch (index) {
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case ECSPI_RXDATA:
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if (fifo32_is_empty(&s->rx_fifo)) {
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/* value is undefined */
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value = 0xdeadbeef;
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} else {
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/* read from the RX FIFO */
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value = fifo32_pop(&s->rx_fifo);
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}
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break;
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case ECSPI_TXDATA:
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qemu_log_mask(LOG_GUEST_ERROR,
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"[%s]%s: Trying to read from TX FIFO\n",
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TYPE_IMX_SPI, __func__);
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/* Reading from TXDATA gives 0 */
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break;
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case ECSPI_MSGDATA:
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qemu_log_mask(LOG_GUEST_ERROR,
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"[%s]%s: Trying to read from MSG FIFO\n",
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TYPE_IMX_SPI, __func__);
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/* Reading from MSGDATA gives 0 */
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break;
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default:
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break;
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}
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imx_spi_update_irq(s);
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}
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DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx_spi_reg_name(index), value);
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return (uint64_t)value;
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}
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static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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IMXSPIState *s = opaque;
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uint32_t index = offset >> 2;
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uint32_t change_mask;
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uint32_t burst;
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if (index >= ECSPI_MAX) {
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
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HWADDR_PRIx "\n", TYPE_IMX_SPI, __func__, offset);
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return;
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}
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DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx_spi_reg_name(index),
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(uint32_t)value);
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if (!imx_spi_is_enabled(s)) {
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/* Block is disabled */
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if (index != ECSPI_CONREG) {
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/* Ignore access */
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return;
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}
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}
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change_mask = s->regs[index] ^ value;
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switch (index) {
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case ECSPI_RXDATA:
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to write to RX FIFO\n",
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TYPE_IMX_SPI, __func__);
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break;
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case ECSPI_TXDATA:
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if (fifo32_is_full(&s->tx_fifo)) {
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/* Ignore writes if queue is full */
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break;
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}
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fifo32_push(&s->tx_fifo, (uint32_t)value);
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if (imx_spi_channel_is_master(s) &&
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(s->regs[ECSPI_CONREG] & ECSPI_CONREG_SMC)) {
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/*
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* Start emitting if current channel is master and SMC bit is
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* set.
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*/
|
||
|
|
imx_spi_flush_txfifo(s);
|
||
|
|
}
|
||
|
|
|
||
|
|
break;
|
||
|
|
case ECSPI_STATREG:
|
||
|
|
/* the RO and TC bits are write-one-to-clear */
|
||
|
|
value &= ECSPI_STATREG_RO | ECSPI_STATREG_TC;
|
||
|
|
s->regs[ECSPI_STATREG] &= ~value;
|
||
|
|
|
||
|
|
break;
|
||
|
|
case ECSPI_CONREG:
|
||
|
|
s->regs[ECSPI_CONREG] = value;
|
||
|
|
|
||
|
|
burst = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1;
|
||
|
|
if (burst % 8) {
|
||
|
|
qemu_log_mask(LOG_UNIMP,
|
||
|
|
"[%s]%s: burst length %d not supported: rounding up to next multiple of 8\n",
|
||
|
|
TYPE_IMX_SPI, __func__, burst);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!imx_spi_is_enabled(s)) {
|
||
|
|
/* device is disabled, so this is a soft reset */
|
||
|
|
imx_spi_soft_reset(s);
|
||
|
|
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (imx_spi_channel_is_master(s)) {
|
||
|
|
int i;
|
||
|
|
|
||
|
|
/* We are in master mode */
|
||
|
|
|
||
|
|
for (i = 0; i < ECSPI_NUM_CS; i++) {
|
||
|
|
qemu_set_irq(s->cs_lines[i],
|
||
|
|
i == imx_spi_selected_channel(s) ? 0 : 1);
|
||
|
|
}
|
||
|
|
|
||
|
|
if ((value & change_mask & ECSPI_CONREG_SMC) &&
|
||
|
|
!fifo32_is_empty(&s->tx_fifo)) {
|
||
|
|
/* SMC bit is set and TX FIFO has some slots filled in */
|
||
|
|
imx_spi_flush_txfifo(s);
|
||
|
|
} else if ((value & change_mask & ECSPI_CONREG_XCH) &&
|
||
|
|
!(value & ECSPI_CONREG_SMC)) {
|
||
|
|
/* This is a request to start emitting */
|
||
|
|
imx_spi_flush_txfifo(s);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
break;
|
||
|
|
case ECSPI_MSGDATA:
|
||
|
|
/* it is not clear from the spec what MSGDATA is for */
|
||
|
|
/* Anyway it is not used by Linux driver */
|
||
|
|
/* So for now we just ignore it */
|
||
|
|
qemu_log_mask(LOG_UNIMP,
|
||
|
|
"[%s]%s: Trying to write to MSGDATA, ignoring\n",
|
||
|
|
TYPE_IMX_SPI, __func__);
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
s->regs[index] = value;
|
||
|
|
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
imx_spi_update_irq(s);
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct MemoryRegionOps imx_spi_ops = {
|
||
|
|
.read = imx_spi_read,
|
||
|
|
.write = imx_spi_write,
|
||
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
||
|
|
.valid = {
|
||
|
|
/*
|
||
|
|
* Our device would not work correctly if the guest was doing
|
||
|
|
* unaligned access. This might not be a limitation on the real
|
||
|
|
* device but in practice there is no reason for a guest to access
|
||
|
|
* this device unaligned.
|
||
|
|
*/
|
||
|
|
.min_access_size = 4,
|
||
|
|
.max_access_size = 4,
|
||
|
|
.unaligned = false,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static void imx_spi_realize(DeviceState *dev, Error **errp)
|
||
|
|
{
|
||
|
|
IMXSPIState *s = IMX_SPI(dev);
|
||
|
|
int i;
|
||
|
|
|
||
|
|
s->bus = ssi_create_bus(dev, "spi");
|
||
|
|
|
||
|
|
memory_region_init_io(&s->iomem, OBJECT(dev), &imx_spi_ops, s,
|
||
|
|
TYPE_IMX_SPI, 0x1000);
|
||
|
|
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
|
||
|
|
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
|
||
|
|
|
||
|
|
for (i = 0; i < ECSPI_NUM_CS; ++i) {
|
||
|
|
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]);
|
||
|
|
}
|
||
|
|
|
||
|
|
fifo32_create(&s->tx_fifo, ECSPI_FIFO_SIZE);
|
||
|
|
fifo32_create(&s->rx_fifo, ECSPI_FIFO_SIZE);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void imx_spi_class_init(ObjectClass *klass, void *data)
|
||
|
|
{
|
||
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
||
|
|
|
||
|
|
dc->realize = imx_spi_realize;
|
||
|
|
dc->vmsd = &vmstate_imx_spi;
|
||
|
|
dc->reset = imx_spi_reset;
|
||
|
|
dc->desc = "i.MX SPI Controller";
|
||
|
|
}
|
||
|
|
|
||
|
|
static const TypeInfo imx_spi_info = {
|
||
|
|
.name = TYPE_IMX_SPI,
|
||
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
||
|
|
.instance_size = sizeof(IMXSPIState),
|
||
|
|
.class_init = imx_spi_class_init,
|
||
|
|
};
|
||
|
|
|
||
|
|
static void imx_spi_register_types(void)
|
||
|
|
{
|
||
|
|
type_register_static(&imx_spi_info);
|
||
|
|
}
|
||
|
|
|
||
|
|
type_init(imx_spi_register_types)
|