30 lines
1.1 KiB
ReStructuredText
30 lines
1.1 KiB
ReStructuredText
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Virtual Accelerator Switchboard (VAS)
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=====================================
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VAS is present in P9 or later processors. In P9, each chip has one
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instance of VAS. Each instance of VAS is represented as a "platform
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device" i.e as a node in root of the device tree: ::
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/vas@<vas_addr>
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with unique VAS address which also represents the Hypervisor window
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context address for the instance of VAS.
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Each VAS node contains: ::
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compatible: "ibm,power9-vas", "ibm,vas"
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ibm,chip-id: Chip-id of the chip containing this instance of VAS.
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ibm,vas-id: unique identifier for each instance of VAS in the system.
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reg: contains 8 64-bit fields.
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Fields [0] and [1] represent the Hypervisor window context BAR
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(start and length). Fields [2] and [3] represent the OS/User
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window context BAR (start and length). Fields [4] and [5]
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contain the start and length of paste power bus address region
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for this chip. Fields [6] and [7] represent the bit field (start
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bit and number of bits) where the window id of the window should
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be encoded when computing the paste address for the window.
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