271 lines
7.9 KiB
C
271 lines
7.9 KiB
C
/*
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* Driver for USB OHCI ported from CoreBoot
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*
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* Copyright (C) 2014 BALATON Zoltan
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*
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* This file was part of the libpayload project.
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*
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* Copyright (C) 2010 Patrick Georgi
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef __OHCI_PRIVATE_H
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#define __OHCI_PRIVATE_H
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#include "libc/byteorder.h"
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#include "usb.h"
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#define READ_OPREG(ohci, field) (__le32_to_cpu((ohci)->opreg->field))
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#define MASK(startbit, lenbit) (((1<<(lenbit))-1)<<(startbit))
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// FIXME: fake
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typedef enum { CMD} reg;
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extern enum {
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NumberDownstreamPorts = 1<<0,
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PowerSwitchingMode = 1<<8,
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NoPowerSwitching = 1<<9,
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DeviceType = 1<<10,
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OverCurrentProtectionMode = 1<<11,
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NoOverCurrentProtection = 1<<12,
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PowerOnToPowerGoodTime = 1<<24
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} HcRhDescriptorAReg;
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extern enum {
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NumberDownstreamPortsMask = MASK(0, 8),
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PowerOnToPowerGoodTimeMask = MASK(24, 8)
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} HcRhDescriptorAMask;
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extern enum {
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DeviceRemovable = 1<<0,
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PortPowerControlMask = 1<<16
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} HcRhDescriptorBReg;
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extern enum {
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CurrentConnectStatus = 1<<0,
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PortEnableStatus = 1<<1,
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PortSuspendStatus = 1<<2,
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PortOverCurrentIndicator = 1<<3,
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PortResetStatus = 1<<4,
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PortPowerStatus = 1<<8,
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LowSpeedDeviceAttached = 1<<9,
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ConnectStatusChange = 1<<16,
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PortEnableStatusChange = 1<<17,
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PortSuspendStatusChange = 1<<18,
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PortOverCurrentIndicatorChange = 1<<19,
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PortResetStatusChange = 1<<20
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} HcRhPortStatusRead;
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extern enum {
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ClearPortEnable = 1<<0,
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SetPortEnable = 1<<1,
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SetPortSuspend = 1<<2,
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ClearSuspendStatus = 1<<3,
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SetPortReset = 1<<4,
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SetPortPower = 1<<8,
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ClearPortPower = 1<<9,
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} HcRhPortStatusSet;
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extern enum {
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LocalPowerStatus = 1<<0,
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OverCurrentIndicator = 1<<1,
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DeviceRemoteWakeupEnable = 1<<15,
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LocalPowerStatusChange = 1<<16,
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OverCurrentIndicatorChange = 1<<17,
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ClearRemoteWakeupEnable = 1<<31
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} HcRhStatusReg;
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extern enum {
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FrameInterval = 1<<0,
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FSLargestDataPacket = 1<<16,
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FrameIntervalToggle = 1<<31
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} HcFmIntervalOffset;
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extern enum {
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FrameIntervalMask = MASK(0, 14),
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FSLargestDataPacketMask = MASK(16, 15),
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FrameIntervalToggleMask = MASK(31, 1)
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} HcFmIntervalMask;
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extern enum {
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ControlBulkServiceRatio = 1<<0,
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PeriodicListEnable = 1<<2,
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IsochronousEnable = 1<<3,
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ControlListEnable = 1<<4,
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BulkListEnable = 1<<5,
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HostControllerFunctionalState = 1<<6,
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InterruptRouting = 1<<8,
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RemoteWakeupConnected = 1<<9,
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RemoteWakeupEnable = 1<<10
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} HcControlReg;
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extern enum {
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ControlBulkServiceRatioMask = MASK(0, 2),
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HostControllerFunctionalStateMask = MASK(6, 2)
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} HcControlMask;
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enum {
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USBReset = 0*HostControllerFunctionalState,
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USBResume = 1*HostControllerFunctionalState,
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USBOperational = 2*HostControllerFunctionalState,
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USBSuspend = 3*HostControllerFunctionalState
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};
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extern enum {
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HostControllerReset = 1<<0,
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ControlListFilled = 1<<1,
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BulkListFilled = 1<<2,
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OwnershipChangeRequest = 1<<3,
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SchedulingOverrunCount = 1<<16
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} HcCommandStatusReg;
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extern enum {
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SchedulingOverrunCountMask = MASK(16, 2)
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} HcCommandStatusMask;
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extern enum {
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FrameRemaining = 1<<0,
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FrameRemainingToggle = 1<<31
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} HcFmRemainingReg;
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extern enum {
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SchedulingOverrung = 1<<0,
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WritebackDoneHead = 1<<1,
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StartofFrame = 1<<2,
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ResumeDetected = 1<<3,
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UnrecoverableError = 1<<4,
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FrameNumberOverflow = 1<<5,
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RootHubStatusChange = 1<<6,
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OwnershipChange = 1<<30
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} HcInterruptStatusReg;
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typedef struct {
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// Control and Status Partition
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volatile u32 HcRevision;
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volatile u32 HcControl;
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volatile u32 HcCommandStatus;
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volatile u32 HcInterruptStatus;
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volatile u32 HcInterruptEnable;
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volatile u32 HcInterruptDisable;
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// Memory Pointer Partition
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volatile u32 HcHCCA;
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volatile u32 HcPeriodCurrentED;
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volatile u32 HcControlHeadED;
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volatile u32 HcControlCurrentED;
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volatile u32 HcBulkHeadED;
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volatile u32 HcBulkCurrentED;
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volatile u32 HcDoneHead;
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// Frame Counter Partition
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volatile u32 HcFmInterval;
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volatile u32 HcFmRemaining;
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volatile u32 HcFmNumber;
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volatile u32 HcPeriodicStart;
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volatile u32 HcLSThreshold;
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// Root Hub Partition
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volatile u32 HcRhDescriptorA;
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volatile u32 HcRhDescriptorB;
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volatile u32 HcRhStatus;
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/* all bits in HcRhPortStatus registers are R/WC, so
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_DO NOT_ use |= to set the bits,
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this clears the entire state */
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volatile u32 HcRhPortStatus[];
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} __attribute__ ((packed)) opreg_t;
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typedef struct { /* should be 256 bytes according to spec */
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u32 HccaInterruptTable[32];
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volatile u16 HccaFrameNumber;
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volatile u16 HccaPad1;
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volatile u32 HccaDoneHead;
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u8 reserved[116]; /* pad according to spec */
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u8 what[4]; /* really pad to 256 as spec only covers 252 */
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} __attribute__ ((packed)) hcca_t;
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typedef volatile struct {
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u32 config;
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u32 tail_pointer;
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u32 head_pointer;
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u32 next_ed;
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} __attribute__ ((packed)) ed_t;
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#define ED_HALTED 1
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#define ED_TOGGLE 2
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#define ED_FUNC_SHIFT 0
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#define ED_FUNC_MASK MASK(0, 7)
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#define ED_EP_SHIFT 7
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#define ED_EP_MASK MASK(7, 4)
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#define ED_DIR_SHIFT 11
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#define ED_DIR_MASK MASK(11, 2)
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#define ED_LOWSPEED (1 << 13)
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#define ED_MPS_SHIFT 16
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typedef volatile struct {
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u32 config;
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u32 current_buffer_pointer;
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u32 next_td;
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u32 buffer_end;
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} __attribute__ ((packed)) td_t;
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/*
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* Bits 0 through 17 of .config won't be interpreted by the host controller
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* (HC) and, after processing the TD, the HC has to ensure those bits have
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* the same state as before. So we are free to use those bits for our own
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* purpose.
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*/
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#define TD_QUEUETYPE_SHIFT 0
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#define TD_QUEUETYPE_MASK MASK(TD_QUEUETYPE_SHIFT, 2)
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#define TD_QUEUETYPE_ASYNC (0 << TD_QUEUETYPE_SHIFT)
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#define TD_QUEUETYPE_INTR (1 << TD_QUEUETYPE_SHIFT)
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#define TD_DIRECTION_SHIFT 19
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#define TD_DIRECTION_MASK MASK(TD_DIRECTION_SHIFT, 2)
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#define TD_DIRECTION_SETUP OHCI_SETUP << TD_DIRECTION_SHIFT
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#define TD_DIRECTION_IN OHCI_IN << TD_DIRECTION_SHIFT
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#define TD_DIRECTION_OUT OHCI_OUT << TD_DIRECTION_SHIFT
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#define TD_DELAY_INTERRUPT_SHIFT 21
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#define TD_DELAY_INTERRUPT_MASK MASK(TD_DELAY_INTERRUPT_SHIFT, 3)
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#define TD_DELAY_INTERRUPT_ZERO 0
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#define TD_DELAY_INTERRUPT_NOINTR (7 << TD_DELAY_INTERRUPT_SHIFT)
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#define TD_TOGGLE_DATA0 0
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#define TD_TOGGLE_DATA1 (1 << 24)
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#define TD_TOGGLE_FROM_ED 0
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#define TD_TOGGLE_FROM_TD (1 << 25)
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#define TD_CC_SHIFT 28
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#define TD_CC_MASK MASK(TD_CC_SHIFT, 4)
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#define TD_CC_NOERR 0
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#define TD_CC_NOACCESS (14 << TD_CC_SHIFT) /* the lower of the two values, so "no access" can be tested with >= */
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#define OHCI_INST(controller) ((ohci_t*)((controller)->instance))
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typedef struct ohci {
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opreg_t *opreg;
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hcca_t *hcca;
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usbdev_t *roothub;
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ed_t *periodic_ed;
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} ohci_t;
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typedef enum { OHCI_SETUP=0, OHCI_OUT=1, OHCI_IN=2, OHCI_FROM_TD=3 } ohci_pid_t;
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#endif
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