123 lines
3.6 KiB
ReStructuredText
123 lines
3.6 KiB
ReStructuredText
.. _device-tree/imc:
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===========================
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IMC Device Tree Bindings
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===========================
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See :ref:`imc` for general In-Memory Collection (IMC) counter information.
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imc-counters top-level node
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----------------------------
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.. code-block:: dts
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imc-counters {
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compatible = "ibm,opal-in-memory-counters";
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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phandle = <0x1000023a>;
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version-id = <0xd>;
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/* Denote IMC Events Catalog version used to build this DTS file. */
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};
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IMC device/units bindings
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-------------------------
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.. code-block:: dts
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mcs3 {
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compatible = "ibm,imc-counters";
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events-prefix = "PM_MCS3_"; /* denotes event name to be prefixed to get complete event name supported by this device */
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phandle = <0x10000241>;
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events = <0x10000242>; /* phandle of the events node supported by this device */
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unit = "MiB";
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scale = "4"; /* unit and scale for all the events for this device */
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reg = <0x118 0x8>; /* denotes base address for device event updates */
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type = <0x10>;
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size = 0x40000;
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offset = 0x180000;
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base_addr = <Base address of the counter in reserve memory>
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/* This is per-chip memory field and OPAL files it based on the no of chip in the system */
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/* base_addr property also indicates (or hints) kernel whether to memory */
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/* should be mmapped or allocated at system start for the counters */
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chipids = <chip-id for the base_addr >
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};
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trace@0 {
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compatible = "ibm,imc-counters";
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events-prefix = "trace_";
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reg = <0x0 0x8>;
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events = < &TRACE_IMC >;
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type = <0x2>;
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size = <0x40000>;
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};
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IMC device event bindings
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-------------------------
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.. code-block:: dts
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nest-mcs-events {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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phandle = <0x10000242>;
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event@98 {
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desc = "Total Write Bandwidth seen on both MCS"; /* event description */
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phandle = <0x1000023d>;
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reg = <0x98 0x8>; /* event offset,when added with (nest-offset-address + device reg) will point to actual counter memory */
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event-name = "DOWN_128B_DATA_XFER"; /* denotes the actual event name */
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};
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/* List of events supported */
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};
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TRACE_IMC: trace-events {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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event@10200000 {
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event-name = "cycles" ; /* For trace node, we only have cycles event now */
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reg = <0x10200000 0x8>;
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desc = "Reference cycles" ;
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};
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};
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Trace-mode SCOM
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----------------
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Trace scom is a 64 bit value which contains the event information for
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IMC-trace mode. Following is the trace-scom layout.
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**TRACE_IMC_SCOM bit representation**
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:0-1: SAMPSEL
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:2-33: CPMC_LOAD
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:34-40: CPMC1SEL
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:41-47: CPMC2SEL
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:48-50: BUFFERSIZE
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:51-63: RESERVED
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*CPMC_LOAD* contains the sampling duration. *SAMPSEL* and *CPMC*SEL*
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determines the event to count. *BUFFRSIZE* indicates the memory range.
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*BUFFERSIZE* can be
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::
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b’000’ - 4K entries * 64 per entry = 256K
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b’001’ - 8K entries * 64 per entry = 512K
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b’010’ - 16K entries * 64 per entry = 1M
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b’011’ - 32K entries * 64 per entry = 2M
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b’100’ - 64K entries * 64 per entry = 4M
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