riscv64
=================================================================== Gbp-Pq: Name riscv64.patch
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@ -733,6 +733,9 @@ def split_triplet(triplet, allow_unknown=False):
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elif cpu == 'sh4':
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canonical_cpu = 'sh4'
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endianness = 'little'
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elif cpu == 'riscv64':
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canonical_cpu = 'riscv64'
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endianness = 'little'
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elif allow_unknown:
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canonical_cpu = cpu
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endianness = 'unknown'
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@ -391,7 +391,8 @@ inline bool AtomicOperations::isLockfreeJS(int32_t size) {
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#elif defined(__ppc__) || defined(__PPC__) || defined(__sparc__) || \
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defined(__ppc64__) || defined(__PPC64__) || defined(__ppc64le__) || \
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defined(__PPC64LE__) || defined(__alpha__) || defined(__hppa__) || \
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defined(__sh__) || defined(__s390__) || defined(__s390x__)
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defined(__sh__) || defined(__s390__) || defined(__s390x__) || \
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defined(__riscv)
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# include "jit/shared/AtomicOperations-feeling-lucky.h"
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#else
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# error "No AtomicOperations support provided for this platform"
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@ -70,6 +70,11 @@
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# endif
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#endif
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#if defined(__riscv) && __riscv_xlen == 64
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# define HAS_64BIT_ATOMICS
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# define HAS_64BIT_LOCKFREE
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#endif
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#ifdef JS_CODEGEN_NONE
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# ifdef JS_64BIT
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# define HAS_64BIT_ATOMICS
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@ -169,6 +169,9 @@ static const ia64_instr _return_instr = {
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# define RETURN_INSTR _return_instr
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# define RETURN_INSTR_TYPE ia64_instr
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#elif defined(__riscv)
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#define RETURN_INSTR 0x80828082 /* ret; ret */
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#else
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# error "Need return instruction for this architecture"
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#endif
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@ -50,6 +50,7 @@ CPU_bitness = {
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'mips64': 64,
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'ppc': 32,
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'ppc64': 64,
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'riscv64': 64,
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's390': 32,
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's390x': 64,
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'sh4': 32,
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@ -89,6 +90,7 @@ CPU_preprocessor_checks = OrderedDict((
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('mips64', '__mips64'),
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('mips32', '__mips__'),
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('sh4', '__sh__'),
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('riscv64', '__riscv && __riscv_xlen == 64'),
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))
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assert sorted(CPU_preprocessor_checks.keys()) == sorted(CPU.POSSIBLE_VALUES)
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