204 lines
6.8 KiB
C
204 lines
6.8 KiB
C
/*
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* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
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* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this list of
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* conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice, this list
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* of conditions and the following disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _GIC_V3_H_
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#define _GIC_V3_H_
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#include "stdint.h"
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#include "target_config.h"
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#include "los_hw_cpu.h"
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#define BIT_32(bit) (1u << bit)
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#define BIT_64(bit) (1ul << bit)
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#define ICC_CTLR_EL1 "S3_0_C12_C12_4"
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#define ICC_PMR_EL1 "S3_0_C4_C6_0"
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#define ICC_IAR1_EL1 "S3_0_C12_C12_0"
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#define ICC_SRE_EL1 "S3_0_C12_C12_5"
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#define ICC_BPR0_EL1 "S3_0_C12_C8_3"
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#define ICC_BPR1_EL1 "S3_0_C12_C12_3"
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#define ICC_IGRPEN0_EL1 "S3_0_C12_C12_6"
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#define ICC_IGRPEN1_EL1 "S3_0_C12_C12_7"
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#define ICC_EOIR1_EL1 "S3_0_C12_C12_1"
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#define ICC_SGI1R_EL1 "S3_0_C12_C11_5"
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#define ICC_EOIR0_EL1 "S3_0_c12_c8_1"
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#define ICC_IAR0_EL1 "S3_0_C12_C8_0"
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#define ICC_CTLR_EL3 "S3_6_C12_C12_4"
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#define ICC_SRE_EL3 "S3_6_C12_C12_5"
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#define ICC_IGRPEN1_EL3 "S3_6_C12_C12_7"
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/* GICD_CTLR bit definitions */
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#define CTLR_ENALBE_G0 BIT_32(0)
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#define CTLR_ENABLE_G1NS BIT_32(1)
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#define CTLR_ENABLE_G1S BIT_32(2)
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#define CTLR_RES0 BIT_32(3)
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#define CTLR_ARE_S BIT_32(4)
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#define CTLR_ARE_NS BIT_32(5)
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#define CTLR_DS BIT_32(6)
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#define CTLR_E1NWF BIT_32(7)
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#define GICD_CTLR_RWP BIT_32(31)
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/* peripheral identification registers */
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#define GICD_CIDR0 (GICD_OFFSET + 0xfff0)
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#define GICD_CIDR1 (GICD_OFFSET + 0xfff4)
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#define GICD_CIDR2 (GICD_OFFSET + 0xfff8)
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#define GICD_CIDR3 (GICD_OFFSET + 0xfffc)
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#define GICD_PIDR0 (GICD_OFFSET + 0xffe0)
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#define GICD_PIDR1 (GICD_OFFSET + 0xffe4)
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#define GICD_PIDR2 (GICD_OFFSET + 0xffe8)
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#define GICD_PIDR3 (GICD_OFFSET + 0xffec)
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/* GICD_PIDR bit definitions and masks */
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#define GICD_PIDR2_ARCHREV_SHIFT 4
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#define GICD_PIDR2_ARCHREV_MASK 0xf
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/* redistributor registers */
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#define GICR_SGI_OFFSET (GICR_OFFSET + 0x10000)
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#define GICR_CTLR(i) (GICR_OFFSET + GICR_STRIDE * (i) + 0x0000)
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#define GICR_IIDR(i) (GICR_OFFSET + GICR_STRIDE * (i) + 0x0004)
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#define GICR_TYPER(i, n) (GICR_OFFSET + GICR_STRIDE * (i) + 0x0008 + (n)*4)
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#define GICR_STATUSR(i) (GICR_OFFSET + GICR_STRIDE * (i) + 0x0010)
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#define GICR_WAKER(i) (GICR_OFFSET + GICR_STRIDE * (i) + 0x0014)
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#define GICR_IGROUPR0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0080)
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#define GICR_IGRPMOD0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0d00)
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#define GICR_ISENABLER0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0100)
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#define GICR_ICENABLER0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0180)
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#define GICR_ISPENDR0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0200)
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#define GICR_ICPENDR0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0280)
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#define GICR_ISACTIVER0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0300)
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#define GICR_ICACTIVER0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0380)
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#define GICR_IPRIORITYR0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0400)
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#define GICR_ICFGR0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0c00)
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#define GICR_ICFGR1(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0c04)
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#define GICR_NSACR(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0e00)
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#define GICR_WAKER_PROCESSORSLEEP_LEN 1U
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#define GICR_WAKER_PROCESSORSLEEP_OFFSET 1
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#define GICR_WAKER_CHILDRENASLEEP_LEN 1U
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#define GICR_WAKER_CHILDRENASLEEP_OFFSET 2
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#define GICR_WAKER_PROCESSORSLEEP (GICR_WAKER_PROCESSORSLEEP_LEN << GICR_WAKER_PROCESSORSLEEP_OFFSET)
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#define GICR_WAKER_CHILDRENASLEEP (GICR_WAKER_CHILDRENASLEEP_LEN << GICR_WAKER_CHILDRENASLEEP_OFFSET)
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STATIC INLINE VOID GiccSetCtlr(UINT32 val)
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{
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#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
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__asm__ volatile("msr " ICC_CTLR_EL3 ", %0" ::"r"(val));
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#else
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__asm__ volatile("msr " ICC_CTLR_EL1 ", %0" ::"r"(val));
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#endif
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ISB;
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}
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STATIC INLINE VOID GiccSetPmr(UINT32 val)
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{
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__asm__ volatile("msr " ICC_PMR_EL1 ", %0" ::"r"(val));
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ISB;
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DSB;
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}
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STATIC INLINE VOID GiccSetIgrpen0(UINT32 val)
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{
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__asm__ volatile("msr " ICC_IGRPEN0_EL1 ", %0" ::"r"(val));
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ISB;
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}
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STATIC INLINE VOID GiccSetIgrpen1(UINT32 val)
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{
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#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
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__asm__ volatile("msr " ICC_IGRPEN1_EL3 ", %0" ::"r"(val));
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#else
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__asm__ volatile("msr " ICC_IGRPEN1_EL1 ", %0" ::"r"(val));
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#endif
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ISB;
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}
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STATIC INLINE UINT32 GiccGetSre(VOID)
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{
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UINT32 temp;
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#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
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__asm__ volatile("mrs %0, " ICC_SRE_EL3 : "=r"(temp));
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#else
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__asm__ volatile("mrs %0, " ICC_SRE_EL1 : "=r"(temp));
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#endif
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return temp;
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}
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STATIC INLINE VOID GiccSetSre(UINT32 val)
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{
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#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
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__asm__ volatile("msr " ICC_SRE_EL3 ", %0" ::"r"(val));
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#else
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__asm__ volatile("msr " ICC_SRE_EL1 ", %0" ::"r"(val));
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#endif
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ISB;
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}
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STATIC INLINE VOID GiccSetEoir(UINT32 val)
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{
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#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
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__asm__ volatile("msr " ICC_EOIR0_EL1 ", %0" ::"r"(val));
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#else
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__asm__ volatile("msr " ICC_EOIR1_EL1 ", %0" ::"r"(val));
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#endif
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ISB;
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}
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STATIC INLINE UINT32 GiccGetIar(VOID)
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{
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UINT32 temp;
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#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
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__asm__ volatile("mrs %0, " ICC_IAR0_EL1 : "=r"(temp));
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#else
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__asm__ volatile("mrs %0, " ICC_IAR1_EL1 : "=r"(temp));
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#endif
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DSB;
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return temp;
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}
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STATIC INLINE VOID GiccSetSgi1r(UINT64 val)
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{
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__asm__ volatile("msr " ICC_SGI1R_EL1 ", %0" ::"r"(val));
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ISB;
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DSB;
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}
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STATIC INLINE VOID GiccSetBpr0(UINT32 val)
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{
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__asm__ volatile("msr " ICC_BPR0_EL1 ", %0" ::"r"(val));
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ISB;
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DSB;
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}
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#endif
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