448 lines
12 KiB
C
448 lines
12 KiB
C
/*
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* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
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* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this list of
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* conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice, this list
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* of conditions and the following disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "gic_common.h"
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#include "gic_v3.h"
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#include "los_typedef.h"
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#include "los_hwi.h"
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#include "los_hwi_pri.h"
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#include "los_mp.h"
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#ifdef LOSCFG_ARCH_GIC_V3
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STATIC UINT32 g_curIrqNum = 0;
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STATIC INLINE UINT64 MpidrToAffinity(UINT64 mpidr)
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{
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return ((MPIDR_AFF_LEVEL(mpidr, 3) << 32) |
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(MPIDR_AFF_LEVEL(mpidr, 2) << 16) |
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(MPIDR_AFF_LEVEL(mpidr, 1) << 8) |
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(MPIDR_AFF_LEVEL(mpidr, 0)));
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}
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#if (LOSCFG_KERNEL_SMP == YES)
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STATIC UINT32 NextCpu(UINT32 cpu, UINT32 cpuMask)
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{
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UINT32 next = cpu + 1;
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while (next < LOSCFG_KERNEL_CORE_NUM) {
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if (cpuMask & (1U << next)) {
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goto OUT;
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}
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next++;
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}
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OUT:
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return next;
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}
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STATIC UINT16 GicTargetList(UINT32 *base, UINT32 cpuMask, UINT64 cluster)
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{
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UINT32 nextCpu;
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UINT16 tList = 0;
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UINT32 cpu = *base;
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UINT64 mpidr = CPU_MAP_GET(cpu);
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while (cpu < LOSCFG_KERNEL_CORE_NUM) {
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tList |= 1U << (mpidr & 0xf);
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nextCpu = NextCpu(cpu, cpuMask);
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if (nextCpu >= LOSCFG_KERNEL_CORE_NUM) {
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goto out;
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}
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cpu = nextCpu;
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mpidr = CPU_MAP_GET(cpu);
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if (cluster != (mpidr & ~0xffUL)) {
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cpu--;
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goto out;
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}
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}
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out:
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*base = cpu;
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return tList;
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}
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STATIC VOID GicSgi(UINT32 irq, UINT32 cpuMask)
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{
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UINT16 tList;
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UINT32 cpu = 0;
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UINT64 val, cluster;
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while (cpuMask && (cpu < LOSCFG_KERNEL_CORE_NUM)) {
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if (cpuMask & (1U << cpu)) {
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cluster = CPU_MAP_GET(cpu) & ~0xffUL;
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tList = GicTargetList(&cpu, cpuMask, cluster);
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/* Generates a Group 1 interrupt for the current security state */
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val = ((MPIDR_AFF_LEVEL(cluster, 3) << 48) |
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(MPIDR_AFF_LEVEL(cluster, 2) << 32) |
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(MPIDR_AFF_LEVEL(cluster, 1) << 16) |
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(irq << 24) | tList);
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GiccSetSgi1r(val);
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}
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cpu++;
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}
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}
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VOID HalIrqSendIpi(UINT32 target, UINT32 ipi)
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{
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GicSgi(ipi, target);
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}
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VOID HalIrqSetAffinity(UINT32 irq, UINT32 cpuMask)
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{
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UINT64 affinity = MpidrToAffinity(NextCpu(0, cpuMask));
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/* When ARE is on, use router */
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GIC_REG_64(GICD_IROUTER(irq)) = affinity;
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}
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#endif
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STATIC VOID GicWaitForRwp(UINT64 reg)
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{
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INT32 count = 1000000; /* 1s */
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while (GIC_REG_32(reg) & GICD_CTLR_RWP) {
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count -= 1;
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if (!count) {
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PRINTK("gic_v3: rwp timeout 0x%x\n", GIC_REG_32(reg));
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return;
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}
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}
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}
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STATIC INLINE VOID GicdSetGroup(UINT32 irq)
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{
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/* configure spi as group 0 on secure mode and group 1 on unsecure mode */
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#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
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GIC_REG_32(GICD_IGROUPR(irq / 32)) = 0;
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#else
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GIC_REG_32(GICD_IGROUPR(irq / 32)) = 0xffffffff;
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#endif
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}
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STATIC INLINE VOID GicrSetWaker(UINT32 cpu)
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{
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GIC_REG_32(GICR_WAKER(cpu)) &= ~GICR_WAKER_PROCESSORSLEEP;
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DSB;
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ISB;
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while ((GIC_REG_32(GICR_WAKER(cpu)) & 0x4) == GICR_WAKER_CHILDRENASLEEP);
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}
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STATIC INLINE VOID GicrSetGroup(UINT32 cpu)
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{
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/* configure sgi/ppi as group 0 on secure mode and group 1 on unsecure mode */
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#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
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GIC_REG_32(GICR_IGROUPR0(cpu)) = 0;
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GIC_REG_32(GICR_IGRPMOD0(cpu)) = 0;
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#else
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GIC_REG_32(GICR_IGROUPR0(cpu)) = 0xffffffff;
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#endif
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}
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STATIC VOID GicdSetPmr(UINT32 irq, UINT8 priority)
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{
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UINT32 pos = irq >> 2; /* one irq have the 8-bit interrupt priority field */
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UINT32 newPri = GIC_REG_32(GICD_IPRIORITYR(pos));
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/* Shift and mask the correct bits for the priority */
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newPri &= ~(GIC_PRIORITY_MASK << ((irq % 4) * GIC_PRIORITY_OFFSET));
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newPri |= priority << ((irq % 4) * GIC_PRIORITY_OFFSET);
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GIC_REG_32(GICD_IPRIORITYR(pos)) = newPri;
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}
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STATIC VOID GicrSetPmr(UINT32 irq, UINT8 priority)
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{
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UINT32 cpu = ArchCurrCpuid();
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UINT32 pos = irq >> 2; /* one irq have the 8-bit interrupt priority field */
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UINT32 newPri = GIC_REG_32(GICR_IPRIORITYR0(cpu) + pos * 4);
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/* Clear priority offset bits and set new priority */
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newPri &= ~(GIC_PRIORITY_MASK << ((irq % 4) * GIC_PRIORITY_OFFSET));
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newPri |= priority << ((irq % 4) * GIC_PRIORITY_OFFSET);
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GIC_REG_32(GICR_IPRIORITYR0(cpu) + pos * 4) = newPri;
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}
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STATIC VOID GiccInitPercpu(VOID)
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{
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/* enable system register interface */
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UINT32 sre = GiccGetSre();
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if (!(sre & 0x1)) {
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GiccSetSre(sre | 0x1);
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/*
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* Need to check that the SRE bit has actually been set. If
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* not, it means that SRE is disabled at up EL level. We're going to
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* die painfully, and there is nothing we can do about it.
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*/
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sre = GiccGetSre();
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LOS_ASSERT(sre & 0x1);
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}
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#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
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/* Enable group 0 and disable grp1ns grp1s interrupts */
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GiccSetIgrpen0(1);
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GiccSetIgrpen1(0);
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/*
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* For priority grouping.
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* The value of this field control show the 8-bit interrupt priority field
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* is split into a group priority field, that determines interrupt preemption,
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* and a subpriority field.
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*/
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GiccSetBpr0(MAX_BINARY_POINT_VALUE);
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#else
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/* enable group 1 interrupts */
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GiccSetIgrpen1(1);
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#endif
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/* set priority threshold to max */
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GiccSetPmr(0xff);
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/* EOI deactivates interrupt too (mode 0) */
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GiccSetCtlr(0);
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}
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UINT32 HalCurIrqGet(VOID)
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{
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return g_curIrqNum;
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}
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VOID HalIrqMask(UINT32 vector)
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{
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INT32 i;
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const UINT32 mask = 1U << (vector % 32);
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if ((vector > OS_USER_HWI_MAX) || (vector < OS_USER_HWI_MIN)) {
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return;
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}
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if (vector < 32) {
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for (i = 0; i < LOSCFG_KERNEL_CORE_NUM; i++) {
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GIC_REG_32(GICR_ICENABLER0(i)) = mask;
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GicWaitForRwp(GICR_CTLR(i));
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}
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} else {
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GIC_REG_32(GICD_ICENABLER(vector >> 5)) = mask;
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GicWaitForRwp(GICD_CTLR);
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}
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}
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VOID HalIrqUnmask(UINT32 vector)
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{
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INT32 i;
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const UINT32 mask = 1U << (vector % 32);
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if ((vector > OS_USER_HWI_MAX) || (vector < OS_USER_HWI_MIN)) {
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return;
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}
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if (vector < 32) {
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for (i = 0; i < LOSCFG_KERNEL_CORE_NUM; i++) {
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GIC_REG_32(GICR_ISENABLER0(i)) = mask;
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GicWaitForRwp(GICR_CTLR(i));
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}
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} else {
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GIC_REG_32(GICD_ISENABLER(vector >> 5)) = mask;
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GicWaitForRwp(GICD_CTLR);
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}
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}
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VOID HalIrqPending(UINT32 vector)
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{
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if ((vector > OS_USER_HWI_MAX) || (vector < OS_USER_HWI_MIN)) {
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return;
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}
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GIC_REG_32(GICD_ISPENDR(vector >> 5)) = 1U << (vector % 32);
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}
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VOID HalIrqClear(UINT32 vector)
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{
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GiccSetEoir(vector);
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ISB;
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}
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UINT32 HalIrqSetPrio(UINT32 vector, UINT8 priority)
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{
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UINT8 prio = priority;
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if (vector > OS_HWI_MAX_NUM) {
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PRINT_ERR("Invalid irq value %u, max irq is %u\n", vector, OS_HWI_MAX_NUM);
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return LOS_NOK;
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}
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prio = prio & (UINT8)GIC_INTR_PRIO_MASK;
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if (vector >= GIC_MIN_SPI_NUM) {
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GicdSetPmr(vector, prio);
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} else {
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GicrSetPmr(vector, prio);
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}
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return LOS_OK;
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}
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VOID HalIrqInitPercpu(VOID)
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{
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INT32 idx;
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UINT32 cpu = ArchCurrCpuid();
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/* GICR init */
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GicrSetWaker(cpu);
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GicrSetGroup(cpu);
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GicWaitForRwp(GICR_CTLR(cpu));
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/* GICR: clear and mask sgi/ppi */
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GIC_REG_32(GICR_ICENABLER0(cpu)) = 0xffffffff;
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GIC_REG_32(GICR_ICPENDR0(cpu)) = 0xffffffff;
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GIC_REG_32(GICR_ISENABLER0(cpu)) = 0xffffffff;
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for (idx = 0; idx < GIC_MIN_SPI_NUM; idx += 1) {
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GicrSetPmr(idx, MIN_INTERRUPT_PRIORITY);
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}
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GicWaitForRwp(GICR_CTLR(cpu));
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/* GICC init */
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GiccInitPercpu();
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#ifdef LOSCFG_KERNEL_SMP
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/* unmask ipi interrupts */
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HalIrqUnmask(LOS_MP_IPI_WAKEUP);
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HalIrqUnmask(LOS_MP_IPI_HALT);
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#endif
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}
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VOID HalIrqInit(VOID)
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{
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UINT32 i;
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UINT64 affinity;
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/* disable distributor */
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GIC_REG_32(GICD_CTLR) = 0;
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GicWaitForRwp(GICD_CTLR);
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ISB;
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/* set externel interrupts to be level triggered, active low. */
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for (i = 32; i < OS_HWI_MAX_NUM; i += 16) {
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GIC_REG_32(GICD_ICFGR(i / 16)) = 0;
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}
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/* config distributer, mask and clear all spis, set group x */
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for (i = 32; i < OS_HWI_MAX_NUM; i += 32) {
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GIC_REG_32(GICD_ICENABLER(i / 32)) = 0xffffffff;
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GIC_REG_32(GICD_ICPENDR(i / 32)) = 0xffffffff;
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GIC_REG_32(GICD_IGRPMODR(i / 32)) = 0;
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GicdSetGroup(i);
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}
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/* set spi priority as default */
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for (i = 32; i < OS_HWI_MAX_NUM; i++) {
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GicdSetPmr(i, MIN_INTERRUPT_PRIORITY);
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}
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GicWaitForRwp(GICD_CTLR);
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/* disable all interrupts. */
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for (i = 0; i < OS_HWI_MAX_NUM; i += 32) {
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GIC_REG_32(GICD_ICENABLER(i / 32)) = 0xffffffff;
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}
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/* enable distributor with ARE, group 1 enabled */
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GIC_REG_32(GICD_CTLR) = CTLR_ENALBE_G0 | CTLR_ENABLE_G1NS | CTLR_ARE_S;
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/* set spi to boot cpu only. ARE must be enabled */
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affinity = MpidrToAffinity(AARCH64_SYSREG_READ(mpidr_el1));
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for (i = 32; i < OS_HWI_MAX_NUM; i++) {
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GIC_REG_64(GICD_IROUTER(i)) = affinity;
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}
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HalIrqInitPercpu();
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#if (LOSCFG_KERNEL_SMP == YES)
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/* register inter-processor interrupt */
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LOS_HwiCreate(LOS_MP_IPI_WAKEUP, 0xa0, 0, OsMpWakeHandler, 0);
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LOS_HwiCreate(LOS_MP_IPI_SCHEDULE, 0xa0, 0, OsMpScheduleHandler, 0);
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LOS_HwiCreate(LOS_MP_IPI_HALT, 0xa0, 0, OsMpScheduleHandler, 0);
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#endif
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}
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VOID HalIrqHandler(VOID)
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{
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UINT32 iar = GiccGetIar();
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UINT32 vector = iar & 0x3FFU;
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/*
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* invalid irq number, mainly the spurious interrupts 0x3ff,
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* valid irq ranges from 0~1019, we use OS_HWI_MAX_NUM to do
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* the checking.
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*/
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if (vector >= OS_HWI_MAX_NUM) {
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return;
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}
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g_curIrqNum = vector;
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OsInterrupt(vector);
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GiccSetEoir(vector);
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}
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CHAR *HalIrqVersion(VOID)
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{
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UINT32 pidr = GIC_REG_32(GICD_PIDR2V3);
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CHAR *irqVerString = NULL;
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switch (pidr >> GIC_REV_OFFSET) {
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case GICV3:
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irqVerString = "GICv3";
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break;
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case GICV4:
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irqVerString = "GICv4";
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break;
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default:
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irqVerString = "unknown";
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}
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return irqVerString;
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}
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#endif
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