98 lines
3.1 KiB
C
98 lines
3.1 KiB
C
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/*
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* Copyright (c) 2020 AIIT XUOS Lab
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* XiUOS is licensed under Mulan PSL v2.
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* You can use this software according to the terms and conditions of the Mulan PSL v2.
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* You may obtain a copy of Mulan PSL v2 at:
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* http://license.coscl.org.cn/MulanPSL2
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* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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* See the Mulan PSL v2 for more details.
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*/
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#ifndef MPU_H
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#define MPU_H
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#include <xs_base.h>
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#include <xs_klist.h>
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#define MPU_ALIGN(size, align) (((size)) & ~((align) - 1))
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#define USER_TEXT_START (uintptr_t)( USERSPACE )
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#define USER_TEXT_END (uintptr_t)( USERSPACE->us_textend )
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#define USER_SRAM_START (uintptr_t)( USERSPACE->us_datastart )
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#define USER_SRAM_END (uintptr_t)( USER_MEMORY_END_ADDRESS )
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#define MPU_MAX_REGION_NUM 8
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/* MPU Control Register Bit Definitions */
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#define MPU_ENABLE (1 << 0) /* Bit 0: Enable the MPU */
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#define MPU_HFNMIENA (1 << 1) /* Bit 1: Enable MPU during hard fault, NMI, and FAULTMAS */
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#define MPU_PRIVDEFENA (1 << 2) /* Bit 2: Enable privileged access to default memory map */
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#define MPU_RBAR_VALID (1 << 4)
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#define MPU_RASR_ENABLE (1 << 0) /* Bit 0: Region enable */
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#define MPU_RASR_REGION_SIZE(n) ((n-1) << 1)
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#define MPU_RASR_AP_NO_NO (0 << 24) /* P:None U:None */
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#define MPU_RASR_AP_RW_NO (1 << 24) /* P:RW U:None */
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#define MPU_RASR_AP_RW_RO (2 << 24) /* P:RW U:RO */
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#define MPU_RASR_AP_RW_RW (3 << 24) /* P:RW U:RW */
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#define MPU_RASR_AP_RO_NO (5 << 24) /* P:RO U:None */
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#define MPU_RASR_AP_RO_RO (6 << 24) /* P:RO U:RO */
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#define MPU_RASR_RASR_XN (1 << 28) /* Bit 28: Instruction access disable */
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#define MPU_RASR_SRD_MASK (0xff << 8)
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#define MPU_RASR_SRD_0 (0x01 << 8)
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#define MPU_RASR_SRD_1 (0x02 << 8)
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#define MPU_RASR_SRD_2 (0x04 << 8)
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#define MPU_RASR_SRD_3 (0x08 << 8)
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#define MPU_RASR_SRD_4 (0x10 << 8)
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#define MPU_RASR_SRD_5 (0x20 << 8)
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#define MPU_RASR_SRD_6 (0x40 << 8)
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#define MPU_RASR_SRD_7 (0x80 << 8)
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#define MPU_RASR_TEX_SHIFT (19) /* Bits 19-21: TEX Address Permission */
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#define MPU_RASR_TEX_MASK (7 << 19)
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#define MPU_RASR_TEX_0 (0 << 19) /* Strongly Ordered */
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#define MPU_RASR_TEX_1 (1 << 19) /* Normal */
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#define MPU_RASR_TEX_2 (2 << 19) /* Device */
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#define MPU_RASR_TEX_BB(bb) ((4|(bb)) << 19)
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#define MPU_RASR_B (1 << 16) /* Bit 16: Bufferable */
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#define MPU_RASR_C (1 << 17) /* Bit 17: Cacheable */
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#define MPU_RASR_S (1 << 18) /* Bit 18: Shareable */
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struct MpuConfig
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{
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uint32_t rasr;
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uint32_t rbar;
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};
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struct MpuRegion
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{
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x_base start;
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x_base size;
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struct MpuConfig config;
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};
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struct Mpu
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{
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uint8_t count;
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struct MpuRegion region[MPU_MAX_REGION_NUM];
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};
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void MpuEnable( uint32_t option);
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void MpuDisable(void);
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x_err_t MpuInit(void **task_mpu);
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void MpuLoad(void *task_mpu);
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#endif
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