Merge branch 'wang_weigen_master' of https://git.trustie.net/xuos/xiuos into xiuos_connection
This commit is contained in:
Liu_Weichao
commit
5fe8fb59b2
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@ -17,6 +17,7 @@ extern int SensorFrameworkInit(void);
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extern int AdapterFrameworkInit(void);
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extern int Adapter4GInit(void);
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extern int AdapterNbiotInit(void);
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extern int AdapterBlueToothInit(void);
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extern int AdapterWifiInit(void);
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extern int AdapterEthernetInit(void);
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@ -96,6 +97,9 @@ static struct InitDesc connection_desc[] =
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#ifdef CONNECTION_ADAPTER_4G
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{ "4G adapter", Adapter4GInit},
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#endif
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#ifdef CONNECTION_ADAPTER_NB
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{ "NB adpter", AdapterNbiotInit},
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#endif
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#ifdef CONNECTION_ADAPTER_ZIGBEE
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{ "zigbee adapter", AdapterZigbeeInit},
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#endif
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|
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@ -9,5 +9,6 @@ menu "knowing app"
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source "$APP_DIR/Applications/knowing_app/instrusion_detect/Kconfig"
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source "$APP_DIR/Applications/knowing_app/helmet_detect/Kconfig"
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source "$APP_DIR/Applications/knowing_app/iris_ml_demo/Kconfig"
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source "$APP_DIR/Applications/knowing_app/k210_fft_test/Kconfig"
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endif
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endmenu
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@ -0,0 +1,3 @@
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config K210_FFT_TEST
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bool "enable apps/k210 fft test"
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default n
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@ -0,0 +1,9 @@
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from building import *
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cwd = GetCurrentDir()
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src = Glob('*.c') + Glob('*.cpp')
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CPPPATH = [cwd]
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group = DefineGroup('Applications', src, depend = ['K210_FFT_TEST'], LOCAL_CPPPATH = CPPPATH)
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Return('group')
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@ -0,0 +1,101 @@
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#include <stdio.h>
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#include <stdlib.h>
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#include <math.h>
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#include "fft_soft.h"
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#define PI 3.14159265358979323846
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complex add(complex a, complex b)
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{
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complex ret = {a.real + b.real, a.imag + b.imag};
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return ret;
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}
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complex sub(complex a, complex b)
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{
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complex ret = {a.real - b.real, a.imag - b.imag};
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return ret;
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}
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complex mul(complex a, complex b)
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{
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complex ret = {a.real * b.real - a.imag * b.imag, a.real * b.imag + a.imag * b.real};
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return ret;
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}
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void bitrev(complex *data, int n)
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{
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int j = 0;
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int m = 0;
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for (int i = 0; i < n; i++)
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{
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if (j > i)
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SWAP(data[i], data[j]);
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m = n / 2;
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while (j >= m && m != 0)
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{
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j -= m;
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m >>= 1;
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}
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j += m;
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}
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}
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void fft_soft(complex *data, int n)
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{
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int M = 0;
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for (int i = n; i > 1; i = i >> 1, M++);
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bitrev(data, n);
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for (int m = 0; m < M; m++)
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{
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int K = n >> (m + 1);
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for (int k = 0; k < K; k++)
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{
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int J = 2 << m;
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int base = k * J;
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for (int j = 0; j < J / 2; j++)
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{
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int t = base + j;
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complex w = {cos(-2 * PI * j * K / n), sin(-2 * PI * j * K / n)};
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complex wn = mul(data[t + J / 2], w);
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complex temp = data[t];
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data[t] = add(data[t], wn);
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data[t + J / 2] = sub(temp, wn);
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}
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}
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}
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}
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void ifft_soft(complex *data, int n)
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{
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int M = 0;
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for (int i = n; i > 1; i = i >> 1, M++);
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bitrev(data, n);
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for (int m = 0; m < M; m++)
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{
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int K = n >> (m + 1);
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for (int k = 0; k < K; k++)
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{
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int J = 2 << m;
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int base = k * J;
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for (int j = 0; j < J / 2; j++)
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{
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int t = base + j;
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complex w = {cos(2 * PI * j * K / n), sin(2 * PI * j * K / n)};
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complex wn = mul(data[t + J / 2], w);
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complex temp = data[t];
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data[t] = add(data[t], wn);
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data[t + J / 2] = sub(temp, wn);
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}
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}
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}
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for (int i = 0; i < n; i++)
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{
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data[i].real /= n;
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data[i].imag /= n;
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}
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}
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@ -0,0 +1,14 @@
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#ifndef _FFT_SOFT_H
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#define _FFT_SOFT_H
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#include <stdint.h>
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#define SWAP(a, b) do {complex t = (a); (a) = (b); (b) = t;} while(0)
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typedef struct{double real, imag;} complex;
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void fft_soft(complex *data, int n);
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void ifft_soft(complex *data, int n);
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void show(complex *data, int n);
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#endif /* _FFT_SOFT_H */
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@ -0,0 +1,159 @@
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/* Copyright 2018 Canaan Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <transform.h>
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#include <math.h>
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#include "encoding.h"
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#include "dmac.h"
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#include "fft.h"
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#include "encoding.h"
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#include "sysctl.h"
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#include "fft_soft.h"
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#define FFT_N 512U
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#define FFT_FORWARD_SHIFT 0x0U
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#define FFT_BACKWARD_SHIFT 0x1ffU
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#define PI 3.14159265358979323846
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typedef enum _complex_mode
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{
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FFT_HARD = 0,
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FFT_SOFT = 1,
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FFT_COMPLEX_MAX,
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} complex_mode_t;
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int16_t real[FFT_N];
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int16_t imag[FFT_N];
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float hard_power[FFT_N];
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float soft_power[FFT_N];
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float hard_angel[FFT_N];
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float soft_angel[FFT_N];
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uint64_t fft_out_data[FFT_N / 2];
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uint64_t buffer_input[FFT_N];
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uint64_t buffer_output[FFT_N];
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uint64_t cycle[FFT_COMPLEX_MAX][FFT_DIR_MAX];
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uint16_t get_bit1_num(uint32_t data)
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{
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uint16_t num;
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for (num = 0; data; num++)
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data &= data - 1;
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return num;
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}
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void k210_fft_test(void)
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{
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int32_t i;
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float tempf1[3];
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fft_data_t *output_data;
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fft_data_t *input_data;
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uint16_t bit1_num = get_bit1_num(FFT_FORWARD_SHIFT);
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complex_hard_t data_hard[FFT_N] = {0};
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complex data_soft[FFT_N] = {0};
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for (i = 0; i < FFT_N; i++)
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{
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tempf1[0] = 0.3 * cosf(2 * PI * i / FFT_N + PI / 3) * 256;
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tempf1[1] = 0.1 * cosf(16 * 2 * PI * i / FFT_N - PI / 9) * 256;
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tempf1[2] = 0.5 * cosf((19 * 2 * PI * i / FFT_N) + PI / 6) * 256;
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data_hard[i].real = (int16_t)(tempf1[0] + tempf1[1] + tempf1[2] + 10);
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data_hard[i].imag = (int16_t)0;
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data_soft[i].real = data_hard[i].real;
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data_soft[i].imag = data_hard[i].imag;
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}
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for (int i = 0; i < FFT_N / 2; ++i)
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{
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input_data = (fft_data_t *)&buffer_input[i];
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input_data->R1 = data_hard[2 * i].real;
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input_data->I1 = data_hard[2 * i].imag;
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input_data->R2 = data_hard[2 * i + 1].real;
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input_data->I2 = data_hard[2 * i + 1].imag;
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}
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cycle[FFT_HARD][FFT_DIR_FORWARD] = read_cycle();
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fft_complex_uint16_dma(DMAC_CHANNEL0, DMAC_CHANNEL1, FFT_FORWARD_SHIFT, FFT_DIR_FORWARD, buffer_input, FFT_N, buffer_output);
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cycle[FFT_HARD][FFT_DIR_FORWARD] = read_cycle() - cycle[FFT_HARD][FFT_DIR_FORWARD];
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cycle[FFT_SOFT][FFT_DIR_FORWARD] = read_cycle();
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fft_soft(data_soft, FFT_N);
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cycle[FFT_SOFT][FFT_DIR_FORWARD] = read_cycle() - cycle[FFT_SOFT][FFT_DIR_FORWARD];
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for (i = 0; i < FFT_N / 2; i++)
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{
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output_data = (fft_data_t*)&buffer_output[i];
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data_hard[2 * i].imag = output_data->I1 ;
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data_hard[2 * i].real = output_data->R1 ;
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data_hard[2 * i + 1].imag = output_data->I2 ;
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data_hard[2 * i + 1].real = output_data->R2 ;
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}
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for (i = 0; i < FFT_N; i++)
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{
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hard_power[i] = sqrt(data_hard[i].real * data_hard[i].real + data_hard[i].imag * data_hard[i].imag) * 2;
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soft_power[i] = sqrt(data_soft[i].real * data_soft[i].real + data_soft[i].imag * data_soft[i].imag) * 2;
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}
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printf("\n[hard fft real][soft fft real][hard fft imag][soft fft imag]\n");
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for (i = 0; i < FFT_N / 2; i++)
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printf("%3d:%7d %7d %7d %7d\n",
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i, data_hard[i].real, (int32_t)data_soft[i].real, data_hard[i].imag, (int32_t)data_soft[i].imag);
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printf("\nhard power soft power:\n");
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printf("%3d : %f %f\n", 0, hard_power[0] / 2 / FFT_N * (1 << bit1_num), soft_power[0] / 2 / FFT_N);
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for (i = 1; i < FFT_N / 2; i++)
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printf("%3d : %f %f\n", i, hard_power[i] / FFT_N * (1 << bit1_num), soft_power[i] / FFT_N);
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printf("\nhard phase soft phase:\n");
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for (i = 0; i < FFT_N / 2; i++)
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{
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hard_angel[i] = atan2(data_hard[i].imag, data_hard[i].real);
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soft_angel[i] = atan2(data_soft[i].imag, data_soft[i].real);
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printf("%3d : %f %f\n", i, hard_angel[i] * 180 / PI, soft_angel[i] * 180 / PI);
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}
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for (int i = 0; i < FFT_N / 2; ++i)
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{
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input_data = (fft_data_t *)&buffer_input[i];
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input_data->R1 = data_hard[2 * i].real;
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input_data->I1 = data_hard[2 * i].imag;
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input_data->R2 = data_hard[2 * i + 1].real;
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input_data->I2 = data_hard[2 * i + 1].imag;
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}
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cycle[FFT_HARD][FFT_DIR_BACKWARD] = read_cycle();
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fft_complex_uint16_dma(DMAC_CHANNEL0, DMAC_CHANNEL1, FFT_BACKWARD_SHIFT, FFT_DIR_BACKWARD, buffer_input, FFT_N, buffer_output);
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cycle[FFT_HARD][FFT_DIR_BACKWARD] = read_cycle() - cycle[FFT_HARD][FFT_DIR_BACKWARD];
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cycle[FFT_SOFT][FFT_DIR_BACKWARD] = read_cycle();
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ifft_soft(data_soft, FFT_N);
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cycle[FFT_SOFT][FFT_DIR_BACKWARD] = read_cycle() - cycle[FFT_SOFT][FFT_DIR_BACKWARD];
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for (i = 0; i < FFT_N / 2; i++)
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{
|
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output_data = (fft_data_t*)&buffer_output[i];
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data_hard[2 * i].imag = output_data->I1 ;
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||||
data_hard[2 * i].real = output_data->R1 ;
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data_hard[2 * i + 1].imag = output_data->I2 ;
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data_hard[2 * i + 1].real = output_data->R2 ;
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}
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printf("\n[hard ifft real][soft ifft real][hard ifft imag][soft ifft imag]\n");
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for (i = 0; i < FFT_N / 2; i++)
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printf("%3d:%7d %7d %7d %7d\n",
|
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i, data_hard[i].real, (int32_t)data_soft[i].real, data_hard[i].imag, (int32_t)data_soft[i].imag);
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printf("[hard fft test] [%d bytes] forward time = %ld us, backward time = %ld us\n",
|
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FFT_N,
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cycle[FFT_HARD][FFT_DIR_FORWARD]/(sysctl_clock_get_freq(SYSCTL_CLOCK_CPU)/1000000),
|
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cycle[FFT_HARD][FFT_DIR_BACKWARD]/(sysctl_clock_get_freq(SYSCTL_CLOCK_CPU)/1000000));
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printf("[soft fft test] [%d bytes] forward time = %ld us, backward time = %ld us\n",
|
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FFT_N,
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cycle[FFT_SOFT][FFT_DIR_FORWARD]/(sysctl_clock_get_freq(SYSCTL_CLOCK_CPU)/1000000),
|
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cycle[FFT_SOFT][FFT_DIR_BACKWARD]/(sysctl_clock_get_freq(SYSCTL_CLOCK_CPU)/1000000));
|
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}
|
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#ifdef __RT_THREAD_H__
|
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MSH_CMD_EXPORT(k210_fft_test,k210 fft test );
|
||||
#endif
|
||||
|
|
@ -309,9 +309,9 @@ static int GetCompleteATReply(ATAgentType agent)
|
|||
|
||||
while (1) {
|
||||
PrivRead(agent->fd, &ch, 1);
|
||||
|
||||
#ifdef CONNECTION_FRAMEWORK_DEBUG
|
||||
printf(" %c (0x%x)\n", ch, ch);
|
||||
|
||||
#endif
|
||||
if (agent->receive_mode == ENTM_MODE){
|
||||
if (agent->entm_recv_len < ENTM_RECV_MAX) {
|
||||
PrivMutexObtain(&agent->lock);
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@
|
|||
#include <stdio.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
#define REPLY_TIME_OUT 3000
|
||||
#define REPLY_TIME_OUT 3
|
||||
|
||||
enum ReceiveMode
|
||||
{
|
||||
|
|
|
|||
|
|
@ -355,7 +355,7 @@ static int Hc08Send(struct Adapter *adapter, const void *buf, size_t len)
|
|||
static int Hc08Recv(struct Adapter *adapter, void *buf, size_t len)
|
||||
{
|
||||
if (adapter->agent) {
|
||||
return EntmRecv(adapter->agent, (char *)buf, len, 40000);
|
||||
return EntmRecv(adapter->agent, (char *)buf, len, 40);
|
||||
} else {
|
||||
printf("Hc08Recv can not find agent\n");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,10 @@
|
|||
if CONNECTION_ADAPTER_NB
|
||||
config ADAPTER_BC28
|
||||
bool "Using nbiot adapter device BC28"
|
||||
default y
|
||||
|
||||
if ADAPTER_BC28
|
||||
source "$APP_DIR/Framework/connection/nbiot/bc28/Kconfig"
|
||||
endif
|
||||
|
||||
endif
|
||||
|
|
@ -1,3 +1,7 @@
|
|||
SRC_FILES := adapter_nbiot.c
|
||||
|
||||
ifeq ($(CONFIG_ADAPTER_BC28),y)
|
||||
SRC_DIR += bc28
|
||||
endif
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
|
|||
|
|
@ -17,3 +17,156 @@
|
|||
* @author AIIT XUOS Lab
|
||||
* @date 2021.06.25
|
||||
*/
|
||||
#include <adapter.h>
|
||||
|
||||
|
||||
#ifdef ADAPTER_BC28
|
||||
extern AdapterProductInfoType BC28Attach(struct Adapter *adapter);
|
||||
#endif
|
||||
|
||||
#define ADAPTER_NBIOT_NAME "nbiot"
|
||||
|
||||
static int AdapterNbiotRegister(struct Adapter *adapter)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
strncpy(adapter->name, ADAPTER_NBIOT_NAME, NAME_NUM_MAX);
|
||||
|
||||
adapter->net_protocol = IP_PROTOCOL;
|
||||
adapter->net_role = CLIENT;
|
||||
|
||||
adapter->adapter_status = UNREGISTERED;
|
||||
|
||||
ret = AdapterDeviceRegister(adapter);
|
||||
if (ret < 0) {
|
||||
printf("AdapterNbiot register error\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int AdapterNbiotInit(void)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
struct Adapter *adapter = malloc(sizeof(struct Adapter));
|
||||
if (!adapter) {
|
||||
printf("malloc adapter failed.\n");
|
||||
return -1;
|
||||
}
|
||||
memset(adapter, 0, sizeof(struct Adapter));
|
||||
ret = AdapterNbiotRegister(adapter);
|
||||
if (ret < 0) {
|
||||
printf("register nbiot adapter error\n");
|
||||
free(adapter);
|
||||
return -1;
|
||||
}
|
||||
#ifdef ADAPTER_BC28
|
||||
AdapterProductInfoType product_info = BC28Attach(adapter);
|
||||
if (!product_info) {
|
||||
printf("bc28 attach error\n");
|
||||
free(adapter);
|
||||
return -1;
|
||||
}
|
||||
|
||||
adapter->product_info_flag = 1;
|
||||
adapter->info = product_info;
|
||||
adapter->done = product_info->model_done;
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/******************TEST*********************/
|
||||
int opennb(void)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
struct Adapter* adapter = AdapterDeviceFindByName(ADAPTER_NBIOT_NAME);
|
||||
|
||||
#ifdef ADAPTER_BC28
|
||||
ret = AdapterDeviceOpen(adapter);
|
||||
if(ret < 0){
|
||||
printf("open adapter failed\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, opennb, opennb, show adapter nb information);
|
||||
int closenb(void)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
struct Adapter* adapter = AdapterDeviceFindByName(ADAPTER_NBIOT_NAME);
|
||||
|
||||
#ifdef ADAPTER_BC28
|
||||
ret = AdapterDeviceClose(adapter);
|
||||
if(ret < 0){
|
||||
printf("open adapter failed\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, closenb, closenb, show adapter nb information);
|
||||
|
||||
int connectnb(int argc, char *argv[])
|
||||
{
|
||||
const char *send_msg = argv[1];
|
||||
int ret = 0;
|
||||
|
||||
struct Adapter* adapter = AdapterDeviceFindByName(ADAPTER_NBIOT_NAME);
|
||||
|
||||
|
||||
ret = AdapterDeviceConnect(adapter, 1, "101.68.82.219","9898",1);
|
||||
if(ret < 0){
|
||||
printf(" adapter send failed\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
||||
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_PARAM_NUM(2)|SHELL_CMD_DISABLE_RETURN, connectnb, connectnb, show adapter nb information);
|
||||
|
||||
int sendnb(int argc, char *argv[])
|
||||
{
|
||||
const char *send_msg = argv[1];
|
||||
int msg_len = atoi(argv[2]);
|
||||
int ret = 0;
|
||||
|
||||
struct Adapter* adapter = AdapterDeviceFindByName(ADAPTER_NBIOT_NAME);
|
||||
|
||||
printf("send argv1 %s len = %d\n",argv[1],msg_len);
|
||||
ret = AdapterDeviceSend(adapter, send_msg, msg_len);
|
||||
if(ret < 0){
|
||||
printf(" adapter send failed\n");
|
||||
return -1;
|
||||
}
|
||||
printf("nb send msg %s\n", send_msg);
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
||||
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_PARAM_NUM(2)|SHELL_CMD_DISABLE_RETURN, sendnb, sendnb, show adapter nb information);
|
||||
|
||||
int recvnb(void)
|
||||
{
|
||||
char recv_msg[128];
|
||||
struct Adapter* adapter = AdapterDeviceFindByName(ADAPTER_NBIOT_NAME);
|
||||
memset(recv_msg,0,128);
|
||||
AdapterDeviceRecv(adapter, recv_msg, 128);
|
||||
PrivTaskDelay(2000);
|
||||
printf("nb recv msg %s\n", recv_msg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, recvnb, recvnb, show adapter nb information);
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,12 @@
|
|||
#ifndef ADAPTER_NBIOT_H
|
||||
#define ADAPTER_NBIOT_H
|
||||
|
||||
#define CONFIG_NBIOT_RESET (0)
|
||||
#define CONFIG_NBIOT_CREATE_SOCKET (1)
|
||||
#define CONFIG_NBIOT_DELETE_SOCKET (2)
|
||||
|
||||
#define SOCKET_TYPE_DGRAM (0)
|
||||
#define SOCKET_TYPE_STREAM (1)
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
config ADAPTER_NBIOT_BC28
|
||||
string "BC28 adapter name"
|
||||
default "bc28"
|
||||
|
||||
if ADD_XIUOS_FETURES
|
||||
config ADAPTER_BC28_RESETPIN
|
||||
int "BC28 RESET pin number"
|
||||
default "100"
|
||||
|
||||
config ADAPTER_BC28_PIN_DRIVER
|
||||
string "BC28 device pin driver path"
|
||||
default "/dev/pin_dev"
|
||||
|
||||
config ADAPTER_BC28_DRIVER_EXTUART
|
||||
bool "Using extra uart to support nbiot"
|
||||
default n
|
||||
|
||||
config ADAPTER_BC28_DRIVER
|
||||
string "BC28 device uart driver path"
|
||||
default "/dev/usart2_dev2"
|
||||
depends on !ADAPTER_BC28_DRIVER_EXTUART
|
||||
|
||||
if ADAPTER_BC28_DRIVER_EXTUART
|
||||
config ADAPTER_BC28_DRIVER
|
||||
string "BC28 device extra uart driver path"
|
||||
default "/dev/extuart_dev5"
|
||||
|
||||
config ADAPTER_BC28_DRIVER_EXT_PORT
|
||||
int "if BC28 device using extuart, choose port"
|
||||
default "5"
|
||||
endif
|
||||
endif
|
||||
|
||||
if ADD_NUTTX_FETURES
|
||||
|
||||
endif
|
||||
|
||||
if ADD_RTTHREAD_FETURES
|
||||
|
||||
endif
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
SRC_FILES := bc28.c
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,551 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file bc28.c
|
||||
* @brief Implement the connection nbiot adapter function, using BC28 device
|
||||
* @version 1.1
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021.09.15
|
||||
*/
|
||||
|
||||
#include <adapter.h>
|
||||
#include <at_agent.h>
|
||||
#include "../adapter_nbiot.h"
|
||||
|
||||
#define SOCKET_PROTOCOL_TCP (6)
|
||||
#define SOCKET_PROTOCOL_UDP (17)
|
||||
|
||||
#define NET_TYPE_AF_INET (0)
|
||||
#define NET_TYPE_AF_INET6 (1)
|
||||
|
||||
#define SOCKET_INVALID_ID (-1)
|
||||
|
||||
|
||||
static int BC28UartOpen(struct Adapter *adapter)
|
||||
{
|
||||
if (NULL == adapter) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Open device in read-write mode */
|
||||
adapter->fd = PrivOpen(ADAPTER_BC28_DRIVER,O_RDWR);
|
||||
if (adapter->fd < 0) {
|
||||
printf("BC28UartOpen get serial %s fd error\n", ADAPTER_BC28_DRIVER);
|
||||
return -1;
|
||||
}
|
||||
/* set serial config, serial_baud_rate = 9600 */
|
||||
|
||||
struct SerialDataCfg cfg;
|
||||
memset(&cfg, 0 ,sizeof(struct SerialDataCfg));
|
||||
|
||||
cfg.serial_baud_rate = BAUD_RATE_9600;
|
||||
cfg.serial_data_bits = DATA_BITS_8;
|
||||
cfg.serial_stop_bits = STOP_BITS_1;
|
||||
cfg.serial_parity_mode = PARITY_NONE;
|
||||
cfg.serial_bit_order = BIT_ORDER_LSB;
|
||||
cfg.serial_invert_mode = NRZ_NORMAL;
|
||||
cfg.serial_buffer_size = SERIAL_RB_BUFSZ;
|
||||
|
||||
/*aiit board use ch438, so it needs more serial configuration*/
|
||||
#ifdef ADAPTER_BC28_DRIVER_EXTUART
|
||||
cfg.ext_uart_no = ADAPTER_BC28_DRIVER_EXT_PORT;
|
||||
cfg.port_configure = PORT_CFG_INIT;
|
||||
#endif
|
||||
|
||||
struct PrivIoctlCfg ioctl_cfg;
|
||||
ioctl_cfg.ioctl_driver_type = SERIAL_TYPE;
|
||||
ioctl_cfg.args = &cfg;
|
||||
|
||||
PrivIoctl(adapter->fd, OPE_INT, &ioctl_cfg);
|
||||
PrivTaskDelay(1000);
|
||||
|
||||
printf("NBIot uart config ready\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void BC28PowerSet(void)
|
||||
{
|
||||
int pin_fd;
|
||||
pin_fd = PrivOpen(ADAPTER_BC28_PIN_DRIVER, O_RDWR);
|
||||
|
||||
struct PinParam pin_param;
|
||||
pin_param.cmd = GPIO_CONFIG_MODE;
|
||||
pin_param.mode = GPIO_CFG_OUTPUT;
|
||||
pin_param.pin = ADAPTER_BC28_RESETPIN;
|
||||
|
||||
struct PrivIoctlCfg ioctl_cfg;
|
||||
ioctl_cfg.ioctl_driver_type = PIN_TYPE;
|
||||
ioctl_cfg.args = &pin_param;
|
||||
PrivIoctl(pin_fd, OPE_CFG, &ioctl_cfg);
|
||||
|
||||
struct PinStat pin_stat;
|
||||
pin_stat.pin = ADAPTER_BC28_RESETPIN;
|
||||
pin_stat.val = GPIO_HIGH;
|
||||
PrivWrite(pin_fd, &pin_stat, 1);
|
||||
|
||||
PrivTaskDelay(200);//at least 200ms
|
||||
|
||||
pin_stat.val = GPIO_LOW;
|
||||
PrivWrite(pin_fd, &pin_stat, 1);
|
||||
|
||||
PrivClose(pin_fd);
|
||||
}
|
||||
|
||||
int NBIoTStatusCheck(struct Adapter *adapter )
|
||||
{
|
||||
int32 result = 0;
|
||||
|
||||
if (!adapter ){
|
||||
return -1;
|
||||
}
|
||||
|
||||
char at_cmd[64] = {0};
|
||||
|
||||
AtSetReplyEndChar(adapter->agent, 0x4F, 0x4B); /* set receive end flag as 'OK'*/
|
||||
|
||||
memcpy(at_cmd, "AT+CSQ", 6);
|
||||
strcat(at_cmd, "\n");
|
||||
printf("cmd : %s\n", at_cmd);
|
||||
result = AtCmdConfigAndCheck(adapter->agent, at_cmd, "OK");
|
||||
if(result < 0) {
|
||||
printf("%s %d cmd[%s] config failed!\n",__func__,__LINE__,at_cmd);
|
||||
result = -1;
|
||||
}
|
||||
|
||||
memcpy(at_cmd, "AT+CFUN?", 8);
|
||||
strcat(at_cmd, "\n");
|
||||
printf("cmd : %s\n", at_cmd);
|
||||
result = AtCmdConfigAndCheck(adapter->agent, at_cmd, "OK");
|
||||
if(result < 0) {
|
||||
printf("%s %d cmd[%s] config failed!\n",__func__,__LINE__,at_cmd);
|
||||
result = -1;
|
||||
}
|
||||
|
||||
memcpy(at_cmd, "AT+CIMI", 7);
|
||||
strcat(at_cmd, "\n");
|
||||
printf("cmd : %s\n", at_cmd);
|
||||
result = AtCmdConfigAndCheck(adapter->agent, at_cmd, "OK");
|
||||
if(result < 0) {
|
||||
printf("%s %d cmd[%s] config failed!\n",__func__,__LINE__,at_cmd);
|
||||
result = -1;
|
||||
}
|
||||
|
||||
memcpy(at_cmd, "AT+CEREG?", 9);
|
||||
strcat(at_cmd, "\n");
|
||||
printf("cmd : %s\n", at_cmd);
|
||||
result = AtCmdConfigAndCheck(adapter->agent, at_cmd, "OK");
|
||||
if(result < 0) {
|
||||
printf("%s %d cmd[%s] config failed!\n",__func__,__LINE__,at_cmd);
|
||||
result = -1;
|
||||
}
|
||||
|
||||
memcpy(at_cmd, "AT+CGATT?", 9);
|
||||
strcat(at_cmd, "\n");
|
||||
printf("cmd : %s\n", at_cmd);
|
||||
result = AtCmdConfigAndCheck(adapter->agent, at_cmd, "OK");
|
||||
if(result < 0) {
|
||||
printf("%s %d cmd[%s] config failed!\n",__func__,__LINE__,at_cmd);
|
||||
result = -1;
|
||||
}
|
||||
|
||||
memcpy(at_cmd, "AT+CGPADDR", 10);
|
||||
strcat(at_cmd, "\n");
|
||||
printf("cmd : %s\n", at_cmd);
|
||||
result = AtCmdConfigAndCheck(adapter->agent, at_cmd, "OK");
|
||||
if(result < 0) {
|
||||
printf("%s %d cmd[%s] config failed!\n",__func__,__LINE__,at_cmd);
|
||||
result = -1;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
/**
|
||||
* @description: NBIoT device create a socket connection
|
||||
* @param adapter - NBIoT adapter AT
|
||||
* @param socket_fd - socket file description
|
||||
* @param type - socket type
|
||||
* @param af_type - IPv4 or IPv6
|
||||
* @return success: EOK, failure: -ERROR
|
||||
*/
|
||||
int NBIoTSocketCreate(struct Adapter *adapter, struct Socket *socket )
|
||||
{
|
||||
int32 result = 0;
|
||||
|
||||
if (!adapter || !socket){
|
||||
return -1;
|
||||
}
|
||||
|
||||
if ( socket->af_type == NET_TYPE_AF_INET6 ) {
|
||||
printf("IPv6 not surport !\n");
|
||||
result = -1;
|
||||
goto out;
|
||||
}
|
||||
|
||||
char *str_af_type = "AF_INET";
|
||||
char *str_type;
|
||||
char str_fd[3] = {1};
|
||||
char *str_protocol ;
|
||||
char at_cmd[64] = {0};
|
||||
char listen_port[] = {0};
|
||||
|
||||
if (socket->socket_id >= 0 && socket->socket_id < 7) {
|
||||
itoa(socket->socket_id, str_fd, 10);
|
||||
adapter->socket.socket_id = socket->socket_id;
|
||||
} else {
|
||||
printf("surport max 0-6, socket_id = [%d] is error!\n",socket->socket_id);
|
||||
result = -1;
|
||||
goto out;
|
||||
}
|
||||
|
||||
if( socket->listen_port >= 0 && socket->listen_port <= 65535){
|
||||
itoa(socket->listen_port, listen_port, 10);
|
||||
}
|
||||
|
||||
adapter->socket.af_type = NET_TYPE_AF_INET;
|
||||
|
||||
if (socket->type == SOCKET_TYPE_STREAM) { //tcp = AT+NSOCR=STREAM,6,0,1,AF_INET
|
||||
adapter->socket.protocal = SOCKET_PROTOCOL_TCP;
|
||||
adapter->socket.type = SOCKET_TYPE_STREAM;
|
||||
str_type = "STREAM";
|
||||
str_protocol = "6";
|
||||
|
||||
} else if ( socket->type == SOCKET_TYPE_DGRAM ){ //udp
|
||||
adapter->socket.type = SOCKET_TYPE_DGRAM;
|
||||
adapter->socket.protocal = SOCKET_PROTOCOL_UDP;
|
||||
str_type = "DGRAM";
|
||||
str_protocol = "17";
|
||||
|
||||
} else {
|
||||
printf("error socket type \n");
|
||||
result = -1;
|
||||
goto out;
|
||||
}
|
||||
|
||||
memcpy(at_cmd, "AT+NSOCR=", 9);
|
||||
strcat(at_cmd, str_type);
|
||||
strcat(at_cmd, ",");
|
||||
strcat(at_cmd, str_protocol);
|
||||
strcat(at_cmd, ",");
|
||||
strcat(at_cmd, listen_port);
|
||||
strcat(at_cmd, ",");
|
||||
strcat(at_cmd, str_fd);
|
||||
strcat(at_cmd, ",");
|
||||
strcat(at_cmd, str_af_type);
|
||||
strcat(at_cmd, "\n");
|
||||
|
||||
printf("cmd : %s\n", at_cmd);
|
||||
|
||||
AtSetReplyEndChar(adapter->agent, 0x4F, 0x4B); /* set receive end flag as 'OK'*/
|
||||
|
||||
result = AtCmdConfigAndCheck(adapter->agent, at_cmd, "OK");
|
||||
if(result < 0) {
|
||||
printf("%s %d cmd[%s] config failed!\n",__func__,__LINE__,at_cmd);
|
||||
result = -1;
|
||||
}
|
||||
|
||||
out:
|
||||
return result;
|
||||
}
|
||||
|
||||
/**
|
||||
* @description: NBIoT device close a socket connection
|
||||
* @param adapter - NBIoT adapter AT
|
||||
* @param socket_fd - socket file description
|
||||
* @return success: EOK, failure: -ERROR
|
||||
*/
|
||||
int NBIoTSocketDelete(struct Adapter *adapter )
|
||||
{
|
||||
|
||||
if (!adapter) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (adapter->socket.socket_id >= 7) {
|
||||
printf("socket fd error \n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
char str_fd[2] = {0};
|
||||
char at_cmd[16] = {0};
|
||||
itoa(adapter->socket.socket_id, str_fd, 10);
|
||||
|
||||
memcpy(at_cmd, "AT+NSOCL=", 9);
|
||||
strcat(at_cmd, str_fd);
|
||||
strcat(at_cmd, "\n");
|
||||
|
||||
printf("cmd : %s\n", at_cmd);
|
||||
AtSetReplyCharNum(adapter->agent, 1);
|
||||
ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, at_cmd);
|
||||
PrivTaskDelay(300);
|
||||
|
||||
adapter->socket.socket_id = SOCKET_INVALID_ID;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int BC28Open(struct Adapter *adapter)
|
||||
{
|
||||
int ret = 0;
|
||||
struct Socket create_socket;
|
||||
|
||||
if (NULL == adapter) {
|
||||
return -1;
|
||||
}
|
||||
/*step1: open BC8 serial port*/
|
||||
ret = BC28UartOpen(adapter);
|
||||
if (ret < 0) {
|
||||
printf("bc18 setup failed.\n");
|
||||
return -1;
|
||||
}
|
||||
/*step2: init AT agent*/
|
||||
if (!adapter->agent) {
|
||||
char *agent_name = "niot_device";
|
||||
if (EOK != InitATAgent(agent_name, adapter->fd, 512)) {
|
||||
printf("at agent init failed !\n");
|
||||
return -1;
|
||||
}
|
||||
ATAgentType at_agent = GetATAgent(agent_name);
|
||||
adapter->agent = at_agent;
|
||||
}
|
||||
create_socket.type = SOCKET_TYPE_STREAM;
|
||||
create_socket.listen_port = 0;
|
||||
create_socket.socket_id = 1;
|
||||
create_socket.af_type = NET_TYPE_AF_INET;
|
||||
|
||||
BC28PowerSet(); /* reset bc28 module by set reset pin */
|
||||
PrivTaskDelay(6000);
|
||||
|
||||
NBIoTStatusCheck(adapter); /* ask module status*/
|
||||
|
||||
/*step3: create a tcp socket default */
|
||||
ret = NBIoTSocketCreate(adapter, &create_socket);
|
||||
if(ret < 0){
|
||||
printf("NBIot create tcp socket failed.\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
printf("NBiot BC28 open successful\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int BC28Close(struct Adapter *adapter)
|
||||
{
|
||||
NBIoTSocketDelete(adapter);
|
||||
PrivClose(adapter->fd);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int BC28Ioctl(struct Adapter *adapter, int cmd, void *args)
|
||||
{
|
||||
int ret = 0;
|
||||
switch (cmd)
|
||||
{
|
||||
case CONFIG_NBIOT_RESET: /* reset nbiot */
|
||||
BC28PowerSet();
|
||||
break;
|
||||
case CONFIG_NBIOT_CREATE_SOCKET: /* create tcp/UDP socket */
|
||||
if(!args){
|
||||
return -1;
|
||||
}
|
||||
struct Socket *create_socket = ( struct Socket *) args;
|
||||
ret = NBIoTSocketCreate(adapter, create_socket);
|
||||
break;
|
||||
case CONFIG_NBIOT_DELETE_SOCKET: /* close socket */
|
||||
ret = NBIoTSocketDelete(adapter);
|
||||
break;
|
||||
default:
|
||||
ret = -1;
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int BC28Connect(struct Adapter *adapter, enum NetRoleType net_role, const char *ip, const char *port, enum IpType ip_type)
|
||||
{
|
||||
int result = 0;
|
||||
|
||||
if (adapter->socket.socket_id > 6) {
|
||||
printf("socket fd error \n");
|
||||
result = -1;
|
||||
goto __exit;
|
||||
}
|
||||
|
||||
if ( ip_type != SOCKET_TYPE_STREAM) {
|
||||
printf("socket type error \n");
|
||||
result = -1;
|
||||
goto __exit;
|
||||
}
|
||||
|
||||
char at_cmd[64] = {0};
|
||||
char str_fd[2] = {0};
|
||||
|
||||
itoa(adapter->socket.socket_id, str_fd, 10);
|
||||
|
||||
memcpy(at_cmd, "AT+NSOCO=", 9);
|
||||
strcat(at_cmd, str_fd);
|
||||
strcat(at_cmd, ",");
|
||||
strcat(at_cmd, ip);
|
||||
strcat(at_cmd, ",");
|
||||
strcat(at_cmd, port);
|
||||
strcat(at_cmd, "\n");
|
||||
|
||||
printf("cmd : %s\n", at_cmd);
|
||||
AtSetReplyEndChar(adapter->agent, 0x4F, 0x4B);
|
||||
result = AtCmdConfigAndCheck(adapter->agent, at_cmd, "OK");
|
||||
if(result < 0) {
|
||||
printf("%s %d cmd[%s] config failed!\n",__func__,__LINE__,at_cmd);
|
||||
result = -1;
|
||||
}
|
||||
|
||||
__exit:
|
||||
return result;
|
||||
}
|
||||
|
||||
static int BC28Send(struct Adapter *adapter, const void *buf, size_t len)
|
||||
{
|
||||
uint32_t result = 0;
|
||||
char at_cmd[64] = {0};
|
||||
char str_fd[2] = {0};
|
||||
|
||||
|
||||
if (adapter->socket.type == SOCKET_TYPE_STREAM ) {
|
||||
|
||||
char size[2] = {0};
|
||||
|
||||
itoa(adapter->socket.socket_id, str_fd, 10);
|
||||
size[0] = len + '0';
|
||||
|
||||
memcpy(at_cmd, "AT+NSOSD=", 9);
|
||||
strcat(at_cmd, str_fd);
|
||||
strcat(at_cmd, ",");
|
||||
strcat(at_cmd, size);
|
||||
strcat(at_cmd, ",");
|
||||
strcat(at_cmd, buf);
|
||||
strcat(at_cmd, "\n");
|
||||
|
||||
} else if(adapter->socket.type == SOCKET_TYPE_DGRAM ) {
|
||||
|
||||
char listen_port[] = {0};
|
||||
|
||||
itoa(adapter->socket.socket_id, str_fd, 10);
|
||||
|
||||
itoa(adapter->socket.listen_port, listen_port, 10);
|
||||
|
||||
memcpy(at_cmd, "AT+NSOST=", 9);
|
||||
strcat(at_cmd, str_fd);
|
||||
strcat(at_cmd, ",");
|
||||
strcat(at_cmd, adapter->socket.dst_ip_addr);
|
||||
strcat(at_cmd, ",");
|
||||
strcat(at_cmd, listen_port);
|
||||
strcat(at_cmd, ",");
|
||||
strcat(at_cmd, buf);
|
||||
strcat(at_cmd, "\n");
|
||||
|
||||
}
|
||||
|
||||
printf("cmd : %s\n", at_cmd);
|
||||
AtSetReplyEndChar(adapter->agent, 0x4F, 0x4B);
|
||||
result = AtCmdConfigAndCheck(adapter->agent, at_cmd, "OK");
|
||||
if(result < 0) {
|
||||
printf("%s %d cmd[%s] config failed!\n",__func__,__LINE__,at_cmd);
|
||||
result = -1;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
static int BC28Recv(struct Adapter *adapter, void *buf, size_t len)
|
||||
{
|
||||
char at_cmd[64] = {0};
|
||||
char str_fd[2] = {0};
|
||||
char size[2] = {0};
|
||||
char *result = NULL;
|
||||
|
||||
ATReplyType reply = CreateATReply(64);
|
||||
if (NULL == reply) {
|
||||
printf("at create failed ! \n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
itoa(adapter->socket.socket_id, str_fd, 10);
|
||||
itoa(len, size, 10);
|
||||
|
||||
memcpy(at_cmd, "AT+NSORF=", 9);
|
||||
strcat(at_cmd, str_fd);
|
||||
strcat(at_cmd, ",");
|
||||
strcat(at_cmd, size);
|
||||
strcat(at_cmd, "\n");
|
||||
|
||||
printf("cmd : %s\n", at_cmd);
|
||||
ATOrderSend(adapter->agent, REPLY_TIME_OUT, reply, at_cmd);
|
||||
PrivTaskDelay(300);
|
||||
|
||||
result = GetReplyText(reply);
|
||||
if (!result) {
|
||||
printf("%s %n get reply failed.\n",__func__,__LINE__);
|
||||
}
|
||||
memcpy(buf, result, reply->reply_len);
|
||||
|
||||
if (reply) {
|
||||
DeleteATReply(reply);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int BC28Disconnect(struct Adapter *adapter)
|
||||
{
|
||||
if (!adapter) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
return NBIoTSocketDelete(adapter);
|
||||
}
|
||||
|
||||
static const struct IpProtocolDone BC28_done =
|
||||
{
|
||||
.open = BC28Open,
|
||||
.close = BC28Close,
|
||||
.ioctl = BC28Ioctl,
|
||||
.setup = NULL,
|
||||
.setdown = NULL,
|
||||
.setaddr = NULL,
|
||||
.setdns = NULL,
|
||||
.setdhcp = NULL,
|
||||
.ping = NULL,
|
||||
.netstat = NULL,
|
||||
.connect = BC28Connect,
|
||||
.send = BC28Send,
|
||||
.recv = BC28Recv,
|
||||
.disconnect = BC28Disconnect,
|
||||
};
|
||||
|
||||
AdapterProductInfoType BC28Attach(struct Adapter *adapter)
|
||||
{
|
||||
struct AdapterProductInfo *product_info = malloc(sizeof(struct AdapterProductInfo));
|
||||
if (!product_info) {
|
||||
printf("BC28Attach malloc product_info error\n");
|
||||
return NULL;
|
||||
}
|
||||
memset(product_info, 0, sizeof(struct AdapterProductInfo));
|
||||
|
||||
strncpy(product_info->model_name, ADAPTER_NBIOT_BC28,sizeof(product_info->model_name));
|
||||
product_info->model_done = (void *)&BC28_done;
|
||||
|
||||
return product_info;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
|
@ -116,7 +116,7 @@ static int Hfa21WifiReceive(struct Adapter *adapter, void *rev_buffer, size_t bu
|
|||
printf("hfa21 receive waiting ... \n");
|
||||
|
||||
if (adapter->agent) {
|
||||
return EntmRecv(adapter->agent, (char *)rev_buffer, buffer_len, 40000);
|
||||
return EntmRecv(adapter->agent, (char *)rev_buffer, buffer_len, 40);
|
||||
} else {
|
||||
printf("Hfa21WifiReceive can not find agent!\n");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -211,7 +211,9 @@ static int E18Open(struct Adapter *adapter)
|
|||
ATAgentType at_agent = GetATAgent(agent_name);
|
||||
adapter->agent = at_agent;
|
||||
}
|
||||
|
||||
|
||||
AtSetReplyLrEnd(adapter->agent, 1);
|
||||
|
||||
try_again:
|
||||
while(try_times--){
|
||||
ret = E18NetRoleConfig(adapter);
|
||||
|
|
@ -355,7 +357,7 @@ static int E18Recv(struct Adapter *adapter, void *buf, size_t len)
|
|||
if(!adapter->agent){
|
||||
PrivRead(adapter->fd, buf, len);
|
||||
} else {
|
||||
EntmRecv(adapter->agent, buf, len, 3000);/* wait timeout 3000ms*/
|
||||
EntmRecv(adapter->agent, buf, len, 3);/* wait timeout 3000ms*/
|
||||
}
|
||||
break;
|
||||
case STT_MODE2:
|
||||
|
|
@ -405,7 +407,8 @@ AdapterProductInfoType E18Attach(struct Adapter *adapter)
|
|||
printf("E18Attach malloc product_info error\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
memset(product_info, 0, sizeof(struct AdapterProductInfo));
|
||||
|
||||
strncpy(product_info->model_name, ADAPTER_ZIGBEE_E18,sizeof(product_info->model_name));
|
||||
product_info->model_done = (void *)&E18_done;
|
||||
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@ CONFIG_BOARD_K210_EVB=y
|
|||
# RT-Thread Kernel
|
||||
#
|
||||
CONFIG_RT_NAME_MAX=8
|
||||
# CONFIG_RT_USING_BIG_ENDIAN is not set
|
||||
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
|
||||
CONFIG_RT_USING_SMP=y
|
||||
CONFIG_RT_CPUS_NR=2
|
||||
|
|
@ -102,7 +103,8 @@ CONFIG_RT_MAIN_THREAD_PRIORITY=10
|
|||
#
|
||||
# C++ features
|
||||
#
|
||||
# CONFIG_RT_USING_CPLUSPLUS is not set
|
||||
CONFIG_RT_USING_CPLUSPLUS=y
|
||||
# CONFIG_RT_USING_CPLUSPLUS11 is not set
|
||||
|
||||
#
|
||||
# Command shell
|
||||
|
|
@ -185,7 +187,9 @@ CONFIG_RT_USING_PIN=y
|
|||
# CONFIG_RT_USING_MTD_NOR is not set
|
||||
# CONFIG_RT_USING_MTD_NAND is not set
|
||||
# CONFIG_RT_USING_PM is not set
|
||||
# CONFIG_RT_USING_RTC is not set
|
||||
CONFIG_RT_USING_RTC=y
|
||||
# CONFIG_RT_USING_ALARM is not set
|
||||
# CONFIG_RT_USING_SOFT_RTC is not set
|
||||
# CONFIG_RT_USING_SDIO is not set
|
||||
CONFIG_RT_USING_SPI=y
|
||||
# CONFIG_RT_USING_QSPI is not set
|
||||
|
|
@ -268,8 +272,7 @@ CONFIG_RT_USING_SAL=y
|
|||
# protocol stack implement
|
||||
#
|
||||
CONFIG_SAL_USING_LWIP=y
|
||||
# CONFIG_SAL_USING_POSIX is not set
|
||||
CONFIG_SAL_SOCKETS_NUM=16
|
||||
CONFIG_SAL_USING_POSIX=y
|
||||
|
||||
#
|
||||
# Network interface device
|
||||
|
|
@ -472,6 +475,7 @@ CONFIG_MAIN_KTASK_STACK_SIZE=1024
|
|||
# knowing app
|
||||
#
|
||||
CONFIG_APPLICATION_KNOWING=y
|
||||
CONFIG_APP_MNIST=y
|
||||
CONFIG_FACE_DETECT=y
|
||||
# CONFIG_INSTRUSION_DETECT is not set
|
||||
# CONFIG_HELMET_DETECT is not set
|
||||
|
|
@ -508,7 +512,10 @@ CONFIG_SENSOR_DEVICE_D124_DEV="/dev/uar2"
|
|||
# CONFIG_SENSOR_HUMIDITY is not set
|
||||
# CONFIG_SUPPORT_CONNECTION_FRAMEWORK is not set
|
||||
CONFIG_SUPPORT_KNOWING_FRAMEWORK=y
|
||||
# CONFIG_USING_TENSORFLOWLITEMICRO is not set
|
||||
CONFIG_USING_TENSORFLOWLITEMICRO=y
|
||||
CONFIG_USING_TENSORFLOWLITEMICRO_NORMAL=y
|
||||
# CONFIG_USING_TENSORFLOWLITEMICRO_CMSISNN is not set
|
||||
# CONFIG_USING_TENSORFLOWLITEMICRO_DEMOAPP is not set
|
||||
CONFIG_USING_KPU_POSTPROCESSING=y
|
||||
CONFIG_USING_YOLOV2=y
|
||||
# CONFIG_USING_KNOWING_FILTER is not set
|
||||
|
|
|
|||
|
|
@ -71,6 +71,7 @@
|
|||
|
||||
/* C++ features */
|
||||
|
||||
#define RT_USING_CPLUSPLUS
|
||||
|
||||
/* Command shell */
|
||||
|
||||
|
|
@ -124,6 +125,7 @@
|
|||
#define RT_SERIAL_USING_DMA
|
||||
#define RT_SERIAL_RB_BUFSZ 64
|
||||
#define RT_USING_PIN
|
||||
#define RT_USING_RTC
|
||||
#define RT_USING_SPI
|
||||
#define RT_USING_SPI_MSD
|
||||
#define RT_USING_SFUD
|
||||
|
|
@ -178,7 +180,7 @@
|
|||
/* protocol stack implement */
|
||||
|
||||
#define SAL_USING_LWIP
|
||||
#define SAL_SOCKETS_NUM 16
|
||||
#define SAL_USING_POSIX
|
||||
|
||||
/* Network interface device */
|
||||
|
||||
|
|
@ -323,6 +325,7 @@
|
|||
/* knowing app */
|
||||
|
||||
#define APPLICATION_KNOWING
|
||||
#define APP_MNIST
|
||||
#define FACE_DETECT
|
||||
|
||||
/* sensor app */
|
||||
|
|
@ -342,6 +345,8 @@
|
|||
#define SENSOR_QUANTITY_D124_VOICE "voice_1"
|
||||
#define SENSOR_DEVICE_D124_DEV "/dev/uar2"
|
||||
#define SUPPORT_KNOWING_FRAMEWORK
|
||||
#define USING_TENSORFLOWLITEMICRO
|
||||
#define USING_TENSORFLOWLITEMICRO_NORMAL
|
||||
#define USING_KPU_POSTPROCESSING
|
||||
#define USING_YOLOV2
|
||||
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
Subproject commit 06fdc108b420f34044a132a19c9adbebf86a7a90
|
||||
Subproject commit 0b6b8b0088dd6aa69d1533e7187e670c5820e0f8
|
||||
|
|
@ -5,7 +5,7 @@ MAKEFLAGS += --no-print-directory
|
|||
.PHONY:COMPILE_APP COMPILE_KERNEL
|
||||
|
||||
|
||||
support :=kd233 stm32f407-st-discovery maix-go stm32f407zgt6 aiit-riscv64-board aiit-arm32-board hifive1-rev-B hifive1-emulator k210-emulator cortex-m3-emulator ok1052-c gapuino
|
||||
support :=kd233 stm32f407-st-discovery maix-go stm32f407zgt6 aiit-riscv64-board aiit-arm32-board hifive1-rev-B hifive1-emulator k210-emulator cortex-m3-emulator cortex-m4-emulator ok1052-c gapuino
|
||||
SRC_DIR:=
|
||||
|
||||
export BOARD ?=kd233
|
||||
|
|
|
|||
|
|
@ -9,6 +9,10 @@ ifeq ($(CONFIG_BOARD_STM32F407_EVB),y)
|
|||
SRC_DIR +=cortex-m4
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BOARD_CORTEX_M4_EVB),y)
|
||||
SRC_DIR +=cortex-m4
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BOARD_CORTEX_M7_EVB),y)
|
||||
SRC_DIR +=cortex-m7
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -105,6 +105,7 @@ BSSInit:
|
|||
|
||||
BSSInitEnd:
|
||||
bl SystemInit
|
||||
bl stm32f407_start
|
||||
|
||||
bl entry
|
||||
bx lr
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
mainmenu "XiUOS Project Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config KERNEL_DIR
|
||||
string
|
||||
option env="KERNEL_ROOT"
|
||||
default "../.."
|
||||
|
||||
config BOARD_STM32F407_EVB
|
||||
bool
|
||||
select ARCH_ARM
|
||||
default y
|
||||
|
||||
source "$KERNEL_DIR/arch/Kconfig"
|
||||
|
||||
menu "stm32f407-st-discovery feature"
|
||||
source "$BSP_DIR/third_party_driver/Kconfig"
|
||||
|
||||
menu "config default board resources"
|
||||
menu "config board app name"
|
||||
config BOARD_APP_NAME
|
||||
string "config board app name"
|
||||
default "/XiUOS_stm32f407-st-discovery_app.bin"
|
||||
endmenu
|
||||
|
||||
menu "config board service table"
|
||||
config SERVICE_TABLE_ADDRESS
|
||||
hex "board service table address"
|
||||
default 0x20000000
|
||||
endmenu
|
||||
|
||||
menu "config hardware resources for connection"
|
||||
if CONNECTION_COMMUNICATION_ETHERNET
|
||||
config ETHERNET_UART_NAME
|
||||
string "ethernet uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
if CONNECTION_COMMUNICATION_WIFI
|
||||
config WIFI_UART_NAME
|
||||
string "wifi uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
|
||||
menu "Hardware feature"
|
||||
source "$KERNEL_DIR/resources/Kconfig"
|
||||
endmenu
|
||||
|
||||
source "$KERNEL_DIR/Kconfig"
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
mainmenu "XiUOS Project Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config KERNEL_DIR
|
||||
string
|
||||
option env="KERNEL_ROOT"
|
||||
default "../.."
|
||||
|
||||
config BOARD_CORTEX_M4_EVB
|
||||
bool
|
||||
select ARCH_ARM
|
||||
default y
|
||||
|
||||
source "$KERNEL_DIR/arch/Kconfig"
|
||||
|
||||
menu "stm32f407-st-discovery feature"
|
||||
source "$BSP_DIR/third_party_driver/Kconfig"
|
||||
|
||||
menu "config default board resources"
|
||||
menu "config board app name"
|
||||
config BOARD_APP_NAME
|
||||
string "config board app name"
|
||||
default "/XiUOS_stm32f407-st-discovery_app.bin"
|
||||
endmenu
|
||||
|
||||
menu "config board service table"
|
||||
config SERVICE_TABLE_ADDRESS
|
||||
hex "board service table address"
|
||||
default 0x20000000
|
||||
endmenu
|
||||
|
||||
menu "config hardware resources for connection"
|
||||
if CONNECTION_COMMUNICATION_ETHERNET
|
||||
config ETHERNET_UART_NAME
|
||||
string "ethernet uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
if CONNECTION_COMMUNICATION_WIFI
|
||||
config WIFI_UART_NAME
|
||||
string "wifi uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
|
||||
menu "Hardware feature"
|
||||
source "$KERNEL_DIR/resources/Kconfig"
|
||||
endmenu
|
||||
|
||||
source "$KERNEL_DIR/Kconfig"
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
mainmenu "XiUOS Project Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config KERNEL_DIR
|
||||
string
|
||||
option env="KERNEL_ROOT"
|
||||
default "../.."
|
||||
|
||||
config BOARD_CORTEX_M4_EVB
|
||||
bool
|
||||
select ARCH_ARM
|
||||
default y
|
||||
|
||||
source "$KERNEL_DIR/arch/Kconfig"
|
||||
|
||||
menu "stm32f407-st-discovery feature"
|
||||
source "$BSP_DIR/third_party_driver/Kconfig"
|
||||
|
||||
menu "config default board resources"
|
||||
menu "config board app name"
|
||||
config BOARD_APP_NAME
|
||||
string "config board app name"
|
||||
default "/XiUOS_stm32f407-st-discovery_app.bin"
|
||||
endmenu
|
||||
|
||||
menu "config board service table"
|
||||
config SERVICE_TABLE_ADDRESS
|
||||
hex "board service table address"
|
||||
default 0x20000000
|
||||
endmenu
|
||||
|
||||
menu "config hardware resources for connection"
|
||||
if CONNECTION_COMMUNICATION_ETHERNET
|
||||
config ETHERNET_UART_NAME
|
||||
string "ethernet uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
if CONNECTION_COMMUNICATION_WIFI
|
||||
config WIFI_UART_NAME
|
||||
string "wifi uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
|
||||
menu "Hardware feature"
|
||||
source "$KERNEL_DIR/resources/Kconfig"
|
||||
endmenu
|
||||
|
||||
source "$KERNEL_DIR/Kconfig"
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
mainmenu "XiUOS Project Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config KERNEL_DIR
|
||||
string
|
||||
option env="KERNEL_ROOT"
|
||||
default "../.."
|
||||
|
||||
config BOARD_CORTEX_M4_EVB
|
||||
bool
|
||||
select ARCH_ARM
|
||||
default y
|
||||
|
||||
source "$KERNEL_DIR/arch/Kconfig"
|
||||
|
||||
menu "cortex-m4 emulator feature"
|
||||
source "$BSP_DIR/third_party_driver/Kconfig"
|
||||
|
||||
menu "config default board resources"
|
||||
menu "config board app name"
|
||||
config BOARD_APP_NAME
|
||||
string "config board app name"
|
||||
default "/XiUOS_stm32f407-st-discovery_app.bin"
|
||||
endmenu
|
||||
|
||||
menu "config board service table"
|
||||
config SERVICE_TABLE_ADDRESS
|
||||
hex "board service table address"
|
||||
default 0x20000000
|
||||
endmenu
|
||||
|
||||
menu "config hardware resources for connection"
|
||||
if CONNECTION_COMMUNICATION_ETHERNET
|
||||
config ETHERNET_UART_NAME
|
||||
string "ethernet uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
if CONNECTION_COMMUNICATION_WIFI
|
||||
config WIFI_UART_NAME
|
||||
string "wifi uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
|
||||
menu "Hardware feature"
|
||||
source "$KERNEL_DIR/resources/Kconfig"
|
||||
endmenu
|
||||
|
||||
source "$KERNEL_DIR/Kconfig"
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
mainmenu "XiUOS Project Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config KERNEL_DIR
|
||||
string
|
||||
option env="KERNEL_ROOT"
|
||||
default "../.."
|
||||
|
||||
config BOARD_CORTEX_M4_EVB
|
||||
bool
|
||||
select ARCH_ARM
|
||||
default y
|
||||
|
||||
source "$KERNEL_DIR/arch/Kconfig"
|
||||
|
||||
menu "cortex-m4 emulator feature"
|
||||
source "$BSP_DIR/third_party_driver/Kconfig"
|
||||
|
||||
menu "config default board resources"
|
||||
menu "config board app name"
|
||||
config BOARD_APP_NAME
|
||||
string "config board app name"
|
||||
default "//XiUOS_cortex-m4-emulator_app.bin"
|
||||
endmenu
|
||||
|
||||
menu "config board service table"
|
||||
config SERVICE_TABLE_ADDRESS
|
||||
hex "board service table address"
|
||||
default 0x20000000
|
||||
endmenu
|
||||
|
||||
menu "config hardware resources for connection"
|
||||
if CONNECTION_COMMUNICATION_ETHERNET
|
||||
config ETHERNET_UART_NAME
|
||||
string "ethernet uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
if CONNECTION_COMMUNICATION_WIFI
|
||||
config WIFI_UART_NAME
|
||||
string "wifi uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
|
||||
menu "Hardware feature"
|
||||
source "$KERNEL_DIR/resources/Kconfig"
|
||||
endmenu
|
||||
|
||||
source "$KERNEL_DIR/Kconfig"
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
mainmenu "XiUOS Project Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config KERNEL_DIR
|
||||
string
|
||||
option env="KERNEL_ROOT"
|
||||
default "../.."
|
||||
|
||||
config BOARD_CORTEX_M4_EVB
|
||||
bool
|
||||
select ARCH_ARM
|
||||
default y
|
||||
|
||||
source "$KERNEL_DIR/arch/Kconfig"
|
||||
|
||||
menu "cortex-m4 emulator feature"
|
||||
source "$BSP_DIR/third_party_driver/Kconfig"
|
||||
|
||||
menu "config default board resources"
|
||||
menu "config board app name"
|
||||
config BOARD_APP_NAME
|
||||
string "config board app name"
|
||||
default "//XiUOS_cortex-m4-emulator_app.bin"
|
||||
endmenu
|
||||
|
||||
menu "config board service table"
|
||||
config SERVICE_TABLE_ADDRESS
|
||||
hex "board service table address"
|
||||
default 0x20000000
|
||||
endmenu
|
||||
|
||||
menu "config hardware resources for connection"
|
||||
if CONNECTION_COMMUNICATION_ETHERNET
|
||||
config ETHERNET_UART_NAME
|
||||
string "ethernet uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
if CONNECTION_COMMUNICATION_WIFI
|
||||
config WIFI_UART_NAME
|
||||
string "wifi uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
config __STACKSIZE__
|
||||
int "stack size for interrupt"
|
||||
default 4096
|
||||
|
||||
endmenu
|
||||
|
||||
|
||||
menu "Hardware feature"
|
||||
source "$KERNEL_DIR/resources/Kconfig"
|
||||
endmenu
|
||||
|
||||
source "$KERNEL_DIR/Kconfig"
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
mainmenu "XiUOS Project Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config KERNEL_DIR
|
||||
string
|
||||
option env="KERNEL_ROOT"
|
||||
default "../.."
|
||||
|
||||
config BOARD_CORTEX_M4_EVB
|
||||
bool
|
||||
select ARCH_ARM
|
||||
default y
|
||||
|
||||
source "$KERNEL_DIR/arch/Kconfig"
|
||||
|
||||
menu "cortex-m4 emulator feature"
|
||||
source "$BSP_DIR/third_party_driver/Kconfig"
|
||||
|
||||
menu "config default board resources"
|
||||
menu "config board app name"
|
||||
config BOARD_APP_NAME
|
||||
string "config board app name"
|
||||
default "//XiUOS_cortex-m4-emulator_app.bin"
|
||||
endmenu
|
||||
|
||||
menu "config board service table"
|
||||
config SERVICE_TABLE_ADDRESS
|
||||
hex "board service table address"
|
||||
default 0x20000000
|
||||
endmenu
|
||||
|
||||
menu "config hardware resources for connection"
|
||||
if CONNECTION_COMMUNICATION_ETHERNET
|
||||
config ETHERNET_UART_NAME
|
||||
string "ethernet uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
if CONNECTION_COMMUNICATION_WIFI
|
||||
config WIFI_UART_NAME
|
||||
string "wifi uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
config __STACKSIZE__
|
||||
int "stack size for interrupt"
|
||||
default 4096
|
||||
|
||||
endmenu
|
||||
|
||||
|
||||
menu "Hardware feature"
|
||||
source "$KERNEL_DIR/resources/Kconfig"
|
||||
endmenu
|
||||
|
||||
source "$KERNEL_DIR/Kconfig"
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
mainmenu "XiUOS Project Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config KERNEL_DIR
|
||||
string
|
||||
option env="KERNEL_ROOT"
|
||||
default "../.."
|
||||
|
||||
config BOARD_CORTEX_M4_EVB
|
||||
bool
|
||||
select ARCH_ARM
|
||||
default y
|
||||
|
||||
source "$KERNEL_DIR/arch/Kconfig"
|
||||
|
||||
menu "cortex-m4 emulator feature"
|
||||
source "$BSP_DIR/third_party_driver/Kconfig"
|
||||
|
||||
menu "config default board resources"
|
||||
menu "config board app name"
|
||||
config BOARD_APP_NAME
|
||||
string "config board app name"
|
||||
default "//XiUOS_cortex-m4-emulator_app.bin"
|
||||
endmenu
|
||||
|
||||
menu "config board service table"
|
||||
config SERVICE_TABLE_ADDRESS
|
||||
hex "board service table address"
|
||||
default 0x20000000
|
||||
endmenu
|
||||
|
||||
menu "config hardware resources for connection"
|
||||
if CONNECTION_COMMUNICATION_ETHERNET
|
||||
config ETHERNET_UART_NAME
|
||||
string "ethernet uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
if CONNECTION_COMMUNICATION_WIFI
|
||||
config WIFI_UART_NAME
|
||||
string "wifi uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
config __STACKSIZE__
|
||||
int "stack size for interrupt"
|
||||
default 4096
|
||||
|
||||
endmenu
|
||||
|
||||
|
||||
menu "Hardware feature"
|
||||
source "$KERNEL_DIR/resources/Kconfig"
|
||||
endmenu
|
||||
|
||||
source "$KERNEL_DIR/Kconfig"
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
mainmenu "XiUOS Project Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config KERNEL_DIR
|
||||
string
|
||||
option env="KERNEL_ROOT"
|
||||
default "../.."
|
||||
|
||||
config BOARD_CORTEX_M4_EVB
|
||||
bool
|
||||
select ARCH_ARM
|
||||
default y
|
||||
|
||||
source "$KERNEL_DIR/arch/Kconfig"
|
||||
|
||||
menu "cortex-m4 emulator feature"
|
||||
source "$BSP_DIR/third_party_driver/Kconfig"
|
||||
|
||||
menu "config default board resources"
|
||||
menu "config board app name"
|
||||
config BOARD_APP_NAME
|
||||
string "config board app name"
|
||||
default "//XiUOS_cortex-m4-emulator_app.bin"
|
||||
endmenu
|
||||
|
||||
menu "config board service table"
|
||||
config SERVICE_TABLE_ADDRESS
|
||||
hex "board service table address"
|
||||
default 0x20000000
|
||||
endmenu
|
||||
|
||||
menu "config hardware resources for connection"
|
||||
if CONNECTION_COMMUNICATION_ETHERNET
|
||||
config ETHERNET_UART_NAME
|
||||
string "ethernet uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
if CONNECTION_COMMUNICATION_WIFI
|
||||
config WIFI_UART_NAME
|
||||
string "wifi uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
config __STACKSIZE__
|
||||
int "stack size for interrupt"
|
||||
default 4096
|
||||
|
||||
endmenu
|
||||
|
||||
|
||||
menu "Hardware feature"
|
||||
source "$KERNEL_DIR/resources/Kconfig"
|
||||
endmenu
|
||||
|
||||
source "$KERNEL_DIR/Kconfig"
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
mainmenu "XiUOS Project Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config KERNEL_DIR
|
||||
string
|
||||
option env="KERNEL_ROOT"
|
||||
default "../.."
|
||||
|
||||
config BOARD_CORTEX_M4_EVB
|
||||
bool
|
||||
select ARCH_ARM
|
||||
default y
|
||||
|
||||
source "$KERNEL_DIR/arch/Kconfig"
|
||||
|
||||
menu "cortex-m4 emulator feature"
|
||||
source "$BSP_DIR/third_party_driver/Kconfig"
|
||||
|
||||
menu "config default board resources"
|
||||
menu "config board app name"
|
||||
config BOARD_APP_NAME
|
||||
string "config board app name"
|
||||
default "//XiUOS_cortex-m4-emulator_app.bin"
|
||||
endmenu
|
||||
|
||||
menu "config board service table"
|
||||
config SERVICE_TABLE_ADDRESS
|
||||
hex "board service table address"
|
||||
default 0x20000000
|
||||
endmenu
|
||||
|
||||
menu "config hardware resources for connection"
|
||||
if CONNECTION_COMMUNICATION_ETHERNET
|
||||
config ETHERNET_UART_NAME
|
||||
string "ethernet uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
if CONNECTION_COMMUNICATION_WIFI
|
||||
config WIFI_UART_NAME
|
||||
string "wifi uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
config __STACKSIZE__
|
||||
int "stack size for interrupt"
|
||||
default 4096
|
||||
|
||||
endmenu
|
||||
|
||||
|
||||
menu "Hardware feature"
|
||||
source "$KERNEL_DIR/resources/Kconfig"
|
||||
endmenu
|
||||
|
||||
source "$KERNEL_DIR/Kconfig"
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
mainmenu "XiUOS Project Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config KERNEL_DIR
|
||||
string
|
||||
option env="KERNEL_ROOT"
|
||||
default "../.."
|
||||
|
||||
config BOARD_CORTEX_M4_EVB
|
||||
bool
|
||||
select ARCH_ARM
|
||||
default y
|
||||
|
||||
source "$KERNEL_DIR/arch/Kconfig"
|
||||
|
||||
menu "cortex-m4 emulator feature"
|
||||
source "$BSP_DIR/third_party_driver/Kconfig"
|
||||
|
||||
menu "config default board resources"
|
||||
menu "config board app name"
|
||||
config BOARD_APP_NAME
|
||||
string "config board app name"
|
||||
default "//XiUOS_cortex-m4-emulator_app.bin"
|
||||
endmenu
|
||||
|
||||
menu "config board service table"
|
||||
config SERVICE_TABLE_ADDRESS
|
||||
hex "board service table address"
|
||||
default 0x20000000
|
||||
endmenu
|
||||
|
||||
menu "config hardware resources for connection"
|
||||
if CONNECTION_COMMUNICATION_ETHERNET
|
||||
config ETHERNET_UART_NAME
|
||||
string "ethernet uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
if CONNECTION_COMMUNICATION_WIFI
|
||||
config WIFI_UART_NAME
|
||||
string "wifi uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
config __STACKSIZE__
|
||||
int "stack size for interrupt"
|
||||
default 4096
|
||||
|
||||
endmenu
|
||||
|
||||
|
||||
menu "Hardware feature"
|
||||
source "$KERNEL_DIR/resources/Kconfig"
|
||||
endmenu
|
||||
|
||||
source "$KERNEL_DIR/Kconfig"
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
mainmenu "XiUOS Project Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config KERNEL_DIR
|
||||
string
|
||||
option env="KERNEL_ROOT"
|
||||
default "../.."
|
||||
|
||||
config BOARD_CORTEX_M4_EVB
|
||||
bool
|
||||
select ARCH_ARM
|
||||
default y
|
||||
|
||||
source "$KERNEL_DIR/arch/Kconfig"
|
||||
|
||||
menu "cortex-m4 emulator feature"
|
||||
source "$BSP_DIR/third_party_driver/Kconfig"
|
||||
|
||||
menu "config default board resources"
|
||||
menu "config board app name"
|
||||
config BOARD_APP_NAME
|
||||
string "config board app name"
|
||||
default "//XiUOS_cortex-m4-emulator_app.bin"
|
||||
endmenu
|
||||
|
||||
menu "config board service table"
|
||||
config SERVICE_TABLE_ADDRESS
|
||||
hex "board service table address"
|
||||
default 0x20000000
|
||||
endmenu
|
||||
|
||||
menu "config hardware resources for connection"
|
||||
if CONNECTION_COMMUNICATION_ETHERNET
|
||||
config ETHERNET_UART_NAME
|
||||
string "ethernet uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
if CONNECTION_COMMUNICATION_WIFI
|
||||
config WIFI_UART_NAME
|
||||
string "wifi uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
config __STACKSIZE__
|
||||
int "stack size for interrupt"
|
||||
default 4096
|
||||
|
||||
endmenu
|
||||
|
||||
|
||||
menu "Hardware feature"
|
||||
source "$KERNEL_DIR/resources/Kconfig"
|
||||
endmenu
|
||||
|
||||
source "$KERNEL_DIR/Kconfig"
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
mainmenu "XiUOS Project Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config KERNEL_DIR
|
||||
string
|
||||
option env="KERNEL_ROOT"
|
||||
default "../.."
|
||||
|
||||
config BOARD_CORTEX_M4_EVB
|
||||
bool
|
||||
select ARCH_ARM
|
||||
default y
|
||||
|
||||
source "$KERNEL_DIR/arch/Kconfig"
|
||||
|
||||
menu "cortex-m4 emulator feature"
|
||||
source "$BSP_DIR/third_party_driver/Kconfig"
|
||||
|
||||
menu "config default board resources"
|
||||
menu "config board app name"
|
||||
config BOARD_APP_NAME
|
||||
string "config board app name"
|
||||
default "//XiUOS_cortex-m4-emulator_app.bin"
|
||||
endmenu
|
||||
|
||||
menu "config board service table"
|
||||
config SERVICE_TABLE_ADDRESS
|
||||
hex "board service table address"
|
||||
default 0x20000000
|
||||
endmenu
|
||||
|
||||
menu "config hardware resources for connection"
|
||||
if CONNECTION_COMMUNICATION_ETHERNET
|
||||
config ETHERNET_UART_NAME
|
||||
string "ethernet uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
if CONNECTION_COMMUNICATION_WIFI
|
||||
config WIFI_UART_NAME
|
||||
string "wifi uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
config __STACKSIZE__
|
||||
int "stack size for interrupt"
|
||||
default 4096
|
||||
|
||||
endmenu
|
||||
|
||||
|
||||
menu "Hardware feature"
|
||||
source "$KERNEL_DIR/resources/Kconfig"
|
||||
endmenu
|
||||
|
||||
source "$KERNEL_DIR/Kconfig"
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
mainmenu "XiUOS Project Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config KERNEL_DIR
|
||||
string
|
||||
option env="KERNEL_ROOT"
|
||||
default "../.."
|
||||
|
||||
config BOARD_CORTEX_M4_EVB
|
||||
bool
|
||||
select ARCH_ARM
|
||||
default y
|
||||
|
||||
source "$KERNEL_DIR/arch/Kconfig"
|
||||
|
||||
menu "cortex-m4 emulator feature"
|
||||
source "$BSP_DIR/third_party_driver/Kconfig"
|
||||
|
||||
menu "config default board resources"
|
||||
menu "config board app name"
|
||||
config BOARD_APP_NAME
|
||||
string "config board app name"
|
||||
default "//XiUOS_cortex-m4-emulator_app.bin"
|
||||
endmenu
|
||||
|
||||
menu "config board service table"
|
||||
config SERVICE_TABLE_ADDRESS
|
||||
hex "board service table address"
|
||||
default 0x20000000
|
||||
endmenu
|
||||
|
||||
menu "config hardware resources for connection"
|
||||
if CONNECTION_COMMUNICATION_ETHERNET
|
||||
config ETHERNET_UART_NAME
|
||||
string "ethernet uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
if CONNECTION_COMMUNICATION_WIFI
|
||||
config WIFI_UART_NAME
|
||||
string "wifi uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
config __STACKSIZE__
|
||||
int "stack size for interrupt"
|
||||
default 4096
|
||||
|
||||
endmenu
|
||||
|
||||
|
||||
menu "Hardware feature"
|
||||
source "$KERNEL_DIR/resources/Kconfig"
|
||||
endmenu
|
||||
|
||||
source "$KERNEL_DIR/Kconfig"
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
mainmenu "XiUOS Project Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config KERNEL_DIR
|
||||
string
|
||||
option env="KERNEL_ROOT"
|
||||
default "../.."
|
||||
|
||||
config BOARD_CORTEX_M4_EVB
|
||||
bool
|
||||
select ARCH_ARM
|
||||
default y
|
||||
|
||||
source "$KERNEL_DIR/arch/Kconfig"
|
||||
|
||||
menu "cortex-m4 emulator feature"
|
||||
source "$BSP_DIR/third_party_driver/Kconfig"
|
||||
|
||||
menu "config default board resources"
|
||||
menu "config board app name"
|
||||
config BOARD_APP_NAME
|
||||
string "config board app name"
|
||||
default "//XiUOS_cortex-m4-emulator_app.bin"
|
||||
endmenu
|
||||
|
||||
menu "config board service table"
|
||||
config SERVICE_TABLE_ADDRESS
|
||||
hex "board service table address"
|
||||
default 0x20000000
|
||||
endmenu
|
||||
|
||||
menu "config hardware resources for connection"
|
||||
if CONNECTION_COMMUNICATION_ETHERNET
|
||||
config ETHERNET_UART_NAME
|
||||
string "ethernet uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
if CONNECTION_COMMUNICATION_WIFI
|
||||
config WIFI_UART_NAME
|
||||
string "wifi uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
config __STACKSIZE__
|
||||
int "stack size for interrupt"
|
||||
default 4096
|
||||
|
||||
endmenu
|
||||
|
||||
|
||||
menu "Hardware feature"
|
||||
source "$KERNEL_DIR/resources/Kconfig"
|
||||
endmenu
|
||||
|
||||
source "$KERNEL_DIR/Kconfig"
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
mainmenu "XiUOS Project Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config KERNEL_DIR
|
||||
string
|
||||
option env="KERNEL_ROOT"
|
||||
default "../.."
|
||||
|
||||
config BOARD_CORTEX_M4_EVB
|
||||
bool
|
||||
select ARCH_ARM
|
||||
default y
|
||||
|
||||
source "$KERNEL_DIR/arch/Kconfig"
|
||||
|
||||
menu "cortex-m4 emulator feature"
|
||||
source "$BSP_DIR/third_party_driver/Kconfig"
|
||||
|
||||
menu "config default board resources"
|
||||
menu "config board app name"
|
||||
config BOARD_APP_NAME
|
||||
string "config board app name"
|
||||
default "//XiUOS_cortex-m4-emulator_app.bin"
|
||||
endmenu
|
||||
|
||||
menu "config board service table"
|
||||
config SERVICE_TABLE_ADDRESS
|
||||
hex "board service table address"
|
||||
default 0x20000000
|
||||
endmenu
|
||||
|
||||
menu "config hardware resources for connection"
|
||||
if CONNECTION_COMMUNICATION_ETHERNET
|
||||
config ETHERNET_UART_NAME
|
||||
string "ethernet uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
if CONNECTION_COMMUNICATION_WIFI
|
||||
config WIFI_UART_NAME
|
||||
string "wifi uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
config __STACKSIZE__
|
||||
int "stack size for interrupt"
|
||||
default 4096
|
||||
|
||||
endmenu
|
||||
|
||||
|
||||
menu "Hardware feature"
|
||||
source "$KERNEL_DIR/resources/Kconfig"
|
||||
endmenu
|
||||
|
||||
source "$KERNEL_DIR/Kconfig"
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
mainmenu "XiUOS Project Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config KERNEL_DIR
|
||||
string
|
||||
option env="KERNEL_ROOT"
|
||||
default "../.."
|
||||
|
||||
config BOARD_CORTEX_M4_EVB
|
||||
bool
|
||||
select ARCH_ARM
|
||||
default y
|
||||
|
||||
source "$KERNEL_DIR/arch/Kconfig"
|
||||
|
||||
menu "cortex-m4 emulator feature"
|
||||
source "$BSP_DIR/third_party_driver/Kconfig"
|
||||
|
||||
menu "config default board resources"
|
||||
menu "config board app name"
|
||||
config BOARD_APP_NAME
|
||||
string "config board app name"
|
||||
default "//XiUOS_cortex-m4-emulator_app.bin"
|
||||
endmenu
|
||||
|
||||
menu "config board service table"
|
||||
config SERVICE_TABLE_ADDRESS
|
||||
hex "board service table address"
|
||||
default 0x20000000
|
||||
endmenu
|
||||
|
||||
menu "config hardware resources for connection"
|
||||
if CONNECTION_COMMUNICATION_ETHERNET
|
||||
config ETHERNET_UART_NAME
|
||||
string "ethernet uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
if CONNECTION_COMMUNICATION_WIFI
|
||||
config WIFI_UART_NAME
|
||||
string "wifi uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
|
||||
menu "Hardware feature"
|
||||
source "$KERNEL_DIR/resources/Kconfig"
|
||||
endmenu
|
||||
|
||||
source "$KERNEL_DIR/Kconfig"
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
mainmenu "XiUOS Project Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config KERNEL_DIR
|
||||
string
|
||||
option env="KERNEL_ROOT"
|
||||
default "../.."
|
||||
|
||||
config BOARD_CORTEX_M4_EVB
|
||||
bool
|
||||
select ARCH_ARM
|
||||
default y
|
||||
|
||||
source "$KERNEL_DIR/arch/Kconfig"
|
||||
|
||||
menu "cortex-m4 emulator feature"
|
||||
source "$BSP_DIR/third_party_driver/Kconfig"
|
||||
|
||||
menu "config default board resources"
|
||||
menu "config board app name"
|
||||
config BOARD_APP_NAME
|
||||
string "config board app name"
|
||||
default "//XiUOS_cortex-m4-emulator_app.bin"
|
||||
endmenu
|
||||
|
||||
menu "config board service table"
|
||||
config SERVICE_TABLE_ADDRESS
|
||||
hex "board service table address"
|
||||
default 0x20000000
|
||||
endmenu
|
||||
|
||||
menu "config hardware resources for connection"
|
||||
if CONNECTION_COMMUNICATION_ETHERNET
|
||||
config ETHERNET_UART_NAME
|
||||
string "ethernet uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
if CONNECTION_COMMUNICATION_WIFI
|
||||
config WIFI_UART_NAME
|
||||
string "wifi uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
|
||||
menu "Hardware feature"
|
||||
source "$KERNEL_DIR/resources/Kconfig"
|
||||
endmenu
|
||||
|
||||
source "$KERNEL_DIR/Kconfig"
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
mainmenu "XiUOS Project Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config KERNEL_DIR
|
||||
string
|
||||
option env="KERNEL_ROOT"
|
||||
default "../.."
|
||||
|
||||
config BOARD_CORTEX_M4_EVB
|
||||
bool
|
||||
select ARCH_ARM
|
||||
default y
|
||||
|
||||
source "$KERNEL_DIR/arch/Kconfig"
|
||||
|
||||
menu "cortex-m4 emulator feature"
|
||||
source "$BSP_DIR/third_party_driver/Kconfig"
|
||||
|
||||
menu "config default board resources"
|
||||
menu "config board app name"
|
||||
config BOARD_APP_NAME
|
||||
string "config board app name"
|
||||
default "//XiUOS_cortex-m4-emulator_app.bin"
|
||||
endmenu
|
||||
|
||||
menu "config board service table"
|
||||
config SERVICE_TABLE_ADDRESS
|
||||
hex "board service table address"
|
||||
default 0x20000000
|
||||
endmenu
|
||||
|
||||
menu "config hardware resources for connection"
|
||||
if CONNECTION_COMMUNICATION_ETHERNET
|
||||
config ETHERNET_UART_NAME
|
||||
string "ethernet uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
if CONNECTION_COMMUNICATION_WIFI
|
||||
config WIFI_UART_NAME
|
||||
string "wifi uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
config __STACKSIZE__
|
||||
int "stack size for interrupt"
|
||||
default 4096
|
||||
|
||||
endmenu
|
||||
|
||||
|
||||
menu "Hardware feature"
|
||||
source "$KERNEL_DIR/resources/Kconfig"
|
||||
endmenu
|
||||
|
||||
source "$KERNEL_DIR/Kconfig"
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
mainmenu "XiUOS Project Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config KERNEL_DIR
|
||||
string
|
||||
option env="KERNEL_ROOT"
|
||||
default "../.."
|
||||
|
||||
config BOARD_CORTEX_M4_EVB
|
||||
bool
|
||||
select ARCH_ARM
|
||||
default y
|
||||
|
||||
source "$KERNEL_DIR/arch/Kconfig"
|
||||
|
||||
menu "cortex-m4 emulator feature"
|
||||
source "$BSP_DIR/third_party_driver/Kconfig"
|
||||
|
||||
menu "config default board resources"
|
||||
menu "config board app name"
|
||||
config BOARD_APP_NAME
|
||||
string "config board app name"
|
||||
default "//XiUOS_cortex-m4-emulator_app.bin"
|
||||
endmenu
|
||||
|
||||
menu "config board service table"
|
||||
config SERVICE_TABLE_ADDRESS
|
||||
hex "board service table address"
|
||||
default 0x20000000
|
||||
endmenu
|
||||
|
||||
menu "config hardware resources for connection"
|
||||
if CONNECTION_COMMUNICATION_ETHERNET
|
||||
config ETHERNET_UART_NAME
|
||||
string "ethernet uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
if CONNECTION_COMMUNICATION_WIFI
|
||||
config WIFI_UART_NAME
|
||||
string "wifi uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
config __STACKSIZE__
|
||||
int "stack size for interrupt"
|
||||
default 4096
|
||||
|
||||
endmenu
|
||||
|
||||
|
||||
menu "Hardware feature"
|
||||
source "$KERNEL_DIR/resources/Kconfig"
|
||||
endmenu
|
||||
|
||||
source "$KERNEL_DIR/Kconfig"
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
mainmenu "XiUOS Project Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config KERNEL_DIR
|
||||
string
|
||||
option env="KERNEL_ROOT"
|
||||
default "../.."
|
||||
|
||||
config BOARD_CORTEX_M4_EVB
|
||||
bool
|
||||
select ARCH_ARM
|
||||
default y
|
||||
|
||||
source "$KERNEL_DIR/arch/Kconfig"
|
||||
|
||||
menu "cortex-m4 emulator feature"
|
||||
source "$BSP_DIR/third_party_driver/Kconfig"
|
||||
|
||||
menu "config default board resources"
|
||||
menu "config board app name"
|
||||
config BOARD_APP_NAME
|
||||
string "config board app name"
|
||||
default "/XiUOS_cortex-m4-emulator_app.bin"
|
||||
endmenu
|
||||
|
||||
menu "config board service table"
|
||||
config SERVICE_TABLE_ADDRESS
|
||||
hex "board service table address"
|
||||
default 0x20000000
|
||||
endmenu
|
||||
|
||||
menu "config hardware resources for connection"
|
||||
if CONNECTION_COMMUNICATION_ETHERNET
|
||||
config ETHERNET_UART_NAME
|
||||
string "ethernet uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
if CONNECTION_COMMUNICATION_WIFI
|
||||
config WIFI_UART_NAME
|
||||
string "wifi uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
config __STACKSIZE__
|
||||
int "stack size for interrupt"
|
||||
default 4096
|
||||
|
||||
endmenu
|
||||
|
||||
|
||||
menu "Hardware feature"
|
||||
source "$KERNEL_DIR/resources/Kconfig"
|
||||
endmenu
|
||||
|
||||
source "$KERNEL_DIR/Kconfig"
|
||||
|
|
@ -0,0 +1,125 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file board.c
|
||||
* @brief support stm32f407-st-discovery-board init configure and start-up
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-04-25
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: board.c
|
||||
Description: support stm32f407-st-discovery-board init configure and driver/task/... init
|
||||
Others:
|
||||
History:
|
||||
1. Date: 2021-04-25
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. support stm32f407-st-discovery-board InitBoardHardware
|
||||
*************************************************/
|
||||
|
||||
#include <xiuos.h>
|
||||
#include "hardware_rcc.h"
|
||||
#include "board.h"
|
||||
#include "connect_usart.h"
|
||||
#include "misc.h"
|
||||
#include <xs_service.h>
|
||||
|
||||
|
||||
|
||||
static void ClockConfiguration()
|
||||
{
|
||||
int cr,cfgr,pllcfgr;
|
||||
int cr1,cfgr1,pllcfgr1;
|
||||
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
|
||||
PWR->CR |= PWR_CR_VOS;
|
||||
RCC_HSEConfig(RCC_HSE_ON);
|
||||
if (RCC_WaitForHSEStartUp() == SUCCESS)
|
||||
{
|
||||
RCC_HCLKConfig(RCC_SYSCLK_Div1);
|
||||
RCC_PCLK2Config(RCC_HCLK_Div2);
|
||||
RCC_PCLK1Config(RCC_HCLK_Div4);
|
||||
RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7);
|
||||
|
||||
RCC_PLLCmd(ENABLE);
|
||||
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
|
||||
|
||||
FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
|
||||
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
|
||||
|
||||
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
|
||||
}
|
||||
SystemCoreClockUpdate();
|
||||
}
|
||||
|
||||
void NVIC_Configuration(void)
|
||||
{
|
||||
#ifdef VECT_TAB_RAM
|
||||
NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
|
||||
#else
|
||||
NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
|
||||
#endif
|
||||
|
||||
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
|
||||
}
|
||||
|
||||
void SysTickConfiguration(void)
|
||||
{
|
||||
RCC_ClocksTypeDef rcc_clocks;
|
||||
uint32 cnts;
|
||||
|
||||
RCC_GetClocksFreq(&rcc_clocks);
|
||||
|
||||
cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND;
|
||||
cnts = cnts / 8;
|
||||
|
||||
SysTick_Config(cnts);
|
||||
SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
|
||||
}
|
||||
|
||||
void SysTick_Handler(int irqn, void *arg)
|
||||
{
|
||||
|
||||
TickAndTaskTimesliceUpdate();
|
||||
|
||||
}
|
||||
DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE);
|
||||
|
||||
|
||||
void InitBoardHardware()
|
||||
{
|
||||
int i = 0;
|
||||
int ret = 0;
|
||||
ClockConfiguration();
|
||||
|
||||
NVIC_Configuration();
|
||||
|
||||
SysTickConfiguration();
|
||||
#ifdef BSP_USING_UART
|
||||
Stm32HwUsartInit();
|
||||
#endif
|
||||
#ifdef KERNEL_CONSOLE
|
||||
InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
|
||||
|
||||
RCC_ClocksTypeDef rcc_clocks;
|
||||
RCC_GetClocksFreq(&rcc_clocks);
|
||||
KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency);
|
||||
|
||||
KPrintf("\nconsole init completed.\n");
|
||||
KPrintf("board initialization......\n");
|
||||
#endif
|
||||
|
||||
InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file board.h
|
||||
* @brief define stm32f407-st-discovery-board init configure and start-up function
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-04-25
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: board.h
|
||||
Description: define stm32f407-st-discovery-board board init function and struct
|
||||
Others:
|
||||
History:
|
||||
1. Date: 2021-04-25
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. define stm32f407-st-discovery-board InitBoardHardware
|
||||
2. define stm32f407-st-discovery-board data and bss struct
|
||||
*************************************************/
|
||||
|
||||
#ifndef BOARD_H
|
||||
#define BOARD_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
extern int __stack_end__;
|
||||
extern unsigned int g_service_table_start;
|
||||
extern unsigned int g_service_table_end;
|
||||
|
||||
#define SURPORT_MPU
|
||||
|
||||
#define MEMORY_START_ADDRESS (&__stack_end__)
|
||||
#define MEM_OFFSET 128
|
||||
#define MEMORY_END_ADDRESS (0x20000000 + MEM_OFFSET * 1024)
|
||||
|
||||
|
||||
#ifdef SEPARATE_COMPILE
|
||||
typedef int (*main_t)(int argc, char *argv[]);
|
||||
typedef void (*exit_t)(void);
|
||||
struct userspace_s
|
||||
{
|
||||
main_t us_entrypoint;
|
||||
exit_t us_taskquit;
|
||||
uintptr_t us_textstart;
|
||||
uintptr_t us_textend;
|
||||
uintptr_t us_datasource;
|
||||
uintptr_t us_datastart;
|
||||
uintptr_t us_dataend;
|
||||
uintptr_t us_bssstart;
|
||||
uintptr_t us_bssend;
|
||||
uintptr_t us_heapend;
|
||||
};
|
||||
#define USERSPACE (( struct userspace_s *)(0x08080000))
|
||||
|
||||
#ifndef SERVICE_TABLE_ADDRESS
|
||||
#define SERVICE_TABLE_ADDRESS (0x20000000)
|
||||
#endif
|
||||
|
||||
#define USER_SRAM_SIZE 64
|
||||
#define USER_MEMORY_START_ADDRESS (USERSPACE->us_bssend)
|
||||
#define USER_MEMORY_END_ADDRESS (0x10000000 + USER_SRAM_SIZE * 1024)
|
||||
#endif
|
||||
|
||||
void InitBoardHardware(void);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,125 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file board.c
|
||||
* @brief support stm32f407-st-discovery-board init configure and start-up
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-04-25
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: board.c
|
||||
Description: support stm32f407-st-discovery-board init configure and driver/task/... init
|
||||
Others:
|
||||
History:
|
||||
1. Date: 2021-04-25
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. support stm32f407-st-discovery-board InitBoardHardware
|
||||
*************************************************/
|
||||
|
||||
#include <xiuos.h>
|
||||
#include "hardware_rcc.h"
|
||||
#include "board.h"
|
||||
#include "connect_usart.h"
|
||||
#include "misc.h"
|
||||
#include <xs_service.h>
|
||||
|
||||
|
||||
|
||||
static void ClockConfiguration()
|
||||
{
|
||||
int cr,cfgr,pllcfgr;
|
||||
int cr1,cfgr1,pllcfgr1;
|
||||
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
|
||||
PWR->CR |= PWR_CR_VOS;
|
||||
RCC_HSEConfig(RCC_HSE_ON);
|
||||
if (RCC_WaitForHSEStartUp() == SUCCESS)
|
||||
{
|
||||
RCC_HCLKConfig(RCC_SYSCLK_Div1);
|
||||
RCC_PCLK2Config(RCC_HCLK_Div2);
|
||||
RCC_PCLK1Config(RCC_HCLK_Div4);
|
||||
RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7);
|
||||
|
||||
RCC_PLLCmd(ENABLE);
|
||||
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
|
||||
|
||||
FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
|
||||
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
|
||||
|
||||
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
|
||||
}
|
||||
SystemCoreClockUpdate();
|
||||
}
|
||||
|
||||
void NVIC_Configuration(void)
|
||||
{
|
||||
#ifdef VECT_TAB_RAM
|
||||
NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
|
||||
#else
|
||||
NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
|
||||
#endif
|
||||
|
||||
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
|
||||
}
|
||||
|
||||
void SysTickConfiguration(void)
|
||||
{
|
||||
RCC_ClocksTypeDef rcc_clocks;
|
||||
uint32 cnts;
|
||||
|
||||
RCC_GetClocksFreq(&rcc_clocks);
|
||||
|
||||
cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND;
|
||||
cnts = cnts / 8;
|
||||
|
||||
SysTick_Config(cnts);
|
||||
SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
|
||||
}
|
||||
|
||||
void SysTick_Handler(int irqn, void *arg)
|
||||
{
|
||||
|
||||
TickAndTaskTimesliceUpdate();
|
||||
|
||||
}
|
||||
DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE);
|
||||
|
||||
|
||||
void InitBoardHardware()
|
||||
{
|
||||
int i = 0;
|
||||
int ret = 0;
|
||||
ClockConfiguration();
|
||||
|
||||
NVIC_Configuration();
|
||||
|
||||
SysTickConfiguration();
|
||||
#ifdef BSP_USING_UART
|
||||
InitHwUsart();
|
||||
#endif
|
||||
#ifdef KERNEL_CONSOLE
|
||||
InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
|
||||
|
||||
RCC_ClocksTypeDef rcc_clocks;
|
||||
RCC_GetClocksFreq(&rcc_clocks);
|
||||
KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency);
|
||||
|
||||
KPrintf("\nconsole init completed.\n");
|
||||
KPrintf("board initialization......\n");
|
||||
#endif
|
||||
|
||||
InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,125 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file board.c
|
||||
* @brief support stm32f407-st-discovery-board init configure and start-up
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-04-25
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: board.c
|
||||
Description: support stm32f407-st-discovery-board init configure and driver/task/... init
|
||||
Others:
|
||||
History:
|
||||
1. Date: 2021-04-25
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. support stm32f407-st-discovery-board InitBoardHardware
|
||||
*************************************************/
|
||||
|
||||
#include <xiuos.h>
|
||||
#include "hardware_rcc.h"
|
||||
#include "board.h"
|
||||
#include "connect_usart.h"
|
||||
#include "misc.h"
|
||||
#include <xs_service.h>
|
||||
|
||||
|
||||
|
||||
static void ClockConfiguration()
|
||||
{
|
||||
int cr,cfgr,pllcfgr;
|
||||
int cr1,cfgr1,pllcfgr1;
|
||||
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
|
||||
PWR->CR |= PWR_CR_VOS;
|
||||
RCC_HSEConfig(RCC_HSE_ON);
|
||||
if (RCC_WaitForHSEStartUp() == SUCCESS)
|
||||
{
|
||||
RCC_HCLKConfig(RCC_SYSCLK_Div1);
|
||||
RCC_PCLK2Config(RCC_HCLK_Div2);
|
||||
RCC_PCLK1Config(RCC_HCLK_Div4);
|
||||
RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7);
|
||||
|
||||
RCC_PLLCmd(ENABLE);
|
||||
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
|
||||
|
||||
FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
|
||||
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
|
||||
|
||||
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
|
||||
}
|
||||
SystemCoreClockUpdate();
|
||||
}
|
||||
|
||||
void NVIC_Configuration(void)
|
||||
{
|
||||
#ifdef VECT_TAB_RAM
|
||||
NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
|
||||
#else
|
||||
NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
|
||||
#endif
|
||||
|
||||
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
|
||||
}
|
||||
|
||||
void SysTickConfiguration(void)
|
||||
{
|
||||
RCC_ClocksTypeDef rcc_clocks;
|
||||
uint32 cnts;
|
||||
|
||||
RCC_GetClocksFreq(&rcc_clocks);
|
||||
|
||||
cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND;
|
||||
cnts = cnts / 8;
|
||||
|
||||
SysTick_Config(cnts);
|
||||
SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
|
||||
}
|
||||
|
||||
void SysTick_Handler(int irqn, void *arg)
|
||||
{
|
||||
|
||||
TickAndTaskTimesliceUpdate();
|
||||
|
||||
}
|
||||
DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE);
|
||||
|
||||
|
||||
void InitBoardHardware()
|
||||
{
|
||||
int i = 0;
|
||||
int ret = 0;
|
||||
ClockConfiguration();
|
||||
|
||||
NVIC_Configuration();
|
||||
|
||||
SysTickConfiguration();
|
||||
#ifdef BSP_USING_UART
|
||||
InitHwUsart();
|
||||
#endif
|
||||
#ifdef KERNEL_CONSOLE
|
||||
InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
|
||||
|
||||
RCC_ClocksTypeDef rcc_clocks;
|
||||
RCC_GetClocksFreq(&rcc_clocks);
|
||||
KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency);
|
||||
|
||||
KPrintf("\nconsole init completed.\n");
|
||||
KPrintf("board initialization......\n");
|
||||
#endif
|
||||
|
||||
InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,125 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file board.c
|
||||
* @brief support stm32f407-st-discovery-board init configure and start-up
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-04-25
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: board.c
|
||||
Description: support stm32f407-st-discovery-board init configure and driver/task/... init
|
||||
Others:
|
||||
History:
|
||||
1. Date: 2021-04-25
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. support stm32f407-st-discovery-board InitBoardHardware
|
||||
*************************************************/
|
||||
|
||||
#include <xiuos.h>
|
||||
#include "hardware_rcc.h"
|
||||
#include "board.h"
|
||||
#include "connect_usart.h"
|
||||
#include "misc.h"
|
||||
#include <xs_service.h>
|
||||
|
||||
|
||||
|
||||
static void ClockConfiguration()
|
||||
{
|
||||
int cr,cfgr,pllcfgr;
|
||||
int cr1,cfgr1,pllcfgr1;
|
||||
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
|
||||
PWR->CR |= PWR_CR_VOS;
|
||||
RCC_HSEConfig(RCC_HSE_ON);
|
||||
if (RCC_WaitForHSEStartUp() == SUCCESS)
|
||||
{
|
||||
RCC_HCLKConfig(RCC_SYSCLK_Div1);
|
||||
RCC_PCLK2Config(RCC_HCLK_Div2);
|
||||
RCC_PCLK1Config(RCC_HCLK_Div4);
|
||||
RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7);
|
||||
|
||||
RCC_PLLCmd(ENABLE);
|
||||
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
|
||||
|
||||
FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
|
||||
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
|
||||
|
||||
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
|
||||
}
|
||||
SystemCoreClockUpdate();
|
||||
}
|
||||
|
||||
void NVIC_Configuration(void)
|
||||
{
|
||||
#ifdef VECT_TAB_RAM
|
||||
NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
|
||||
#else
|
||||
NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
|
||||
#endif
|
||||
|
||||
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
|
||||
}
|
||||
|
||||
void SysTickConfiguration(void)
|
||||
{
|
||||
RCC_ClocksTypeDef rcc_clocks;
|
||||
uint32 cnts;
|
||||
|
||||
RCC_GetClocksFreq(&rcc_clocks);
|
||||
|
||||
cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND;
|
||||
cnts = cnts / 8;
|
||||
|
||||
SysTick_Config(cnts);
|
||||
SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
|
||||
}
|
||||
|
||||
void SysTick_Handler(int irqn, void *arg)
|
||||
{
|
||||
|
||||
TickAndTaskTimesliceUpdate();
|
||||
|
||||
}
|
||||
DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE);
|
||||
|
||||
|
||||
void InitBoardHardware()
|
||||
{
|
||||
int i = 0;
|
||||
int ret = 0;
|
||||
ClockConfiguration();
|
||||
|
||||
NVIC_Configuration();
|
||||
|
||||
SysTickConfiguration();
|
||||
#ifdef BSP_USING_UART
|
||||
InitHwUsart();
|
||||
#endif
|
||||
#ifdef KERNEL_CONSOLE
|
||||
InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
|
||||
|
||||
RCC_ClocksTypeDef rcc_clocks;
|
||||
RCC_GetClocksFreq(&rcc_clocks);
|
||||
KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency);
|
||||
|
||||
KPrintf("\nconsole init completed.\n");
|
||||
KPrintf("board initialization......\n");
|
||||
#endif
|
||||
|
||||
InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,125 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file board.c
|
||||
* @brief support stm32f407-st-discovery-board init configure and start-up
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-04-25
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: board.c
|
||||
Description: support stm32f407-st-discovery-board init configure and driver/task/... init
|
||||
Others:
|
||||
History:
|
||||
1. Date: 2021-04-25
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. support stm32f407-st-discovery-board InitBoardHardware
|
||||
*************************************************/
|
||||
|
||||
#include <xiuos.h>
|
||||
#include "hardware_rcc.h"
|
||||
#include "board.h"
|
||||
#include "connect_usart.h"
|
||||
#include "misc.h"
|
||||
#include <xs_service.h>
|
||||
|
||||
|
||||
|
||||
static void ClockConfiguration()
|
||||
{
|
||||
int cr,cfgr,pllcfgr;
|
||||
int cr1,cfgr1,pllcfgr1;
|
||||
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
|
||||
PWR->CR |= PWR_CR_VOS;
|
||||
RCC_HSEConfig(RCC_HSE_ON);
|
||||
if (RCC_WaitForHSEStartUp() == SUCCESS)
|
||||
{
|
||||
RCC_HCLKConfig(RCC_SYSCLK_Div1);
|
||||
RCC_PCLK2Config(RCC_HCLK_Div2);
|
||||
RCC_PCLK1Config(RCC_HCLK_Div4);
|
||||
RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7);
|
||||
|
||||
RCC_PLLCmd(ENABLE);
|
||||
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
|
||||
|
||||
FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
|
||||
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
|
||||
|
||||
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
|
||||
}
|
||||
SystemCoreClockUpdate();
|
||||
}
|
||||
|
||||
void NVIC_Configuration(void)
|
||||
{
|
||||
#ifdef VECT_TAB_RAM
|
||||
NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
|
||||
#else
|
||||
NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
|
||||
#endif
|
||||
|
||||
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
|
||||
}
|
||||
|
||||
void SysTickConfiguration(void)
|
||||
{
|
||||
RCC_ClocksTypeDef rcc_clocks;
|
||||
uint32 cnts;
|
||||
|
||||
RCC_GetClocksFreq(&rcc_clocks);
|
||||
|
||||
cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND;
|
||||
cnts = cnts / 8;
|
||||
|
||||
SysTick_Config(cnts);
|
||||
SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
|
||||
}
|
||||
|
||||
void SysTick_Handler(int irqn, void *arg)
|
||||
{
|
||||
|
||||
TickAndTaskTimesliceUpdate();
|
||||
|
||||
}
|
||||
DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE);
|
||||
|
||||
|
||||
void InitBoardHardware()
|
||||
{
|
||||
int i = 0;
|
||||
int ret = 0;
|
||||
ClockConfiguration();
|
||||
|
||||
NVIC_Configuration();
|
||||
|
||||
SysTickConfiguration();
|
||||
#ifdef BSP_USING_UART
|
||||
InitHwUsart();
|
||||
#endif
|
||||
#ifdef KERNEL_CONSOLE
|
||||
InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
|
||||
|
||||
RCC_ClocksTypeDef rcc_clocks;
|
||||
RCC_GetClocksFreq(&rcc_clocks);
|
||||
KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency);
|
||||
|
||||
KPrintf("\nconsole init completed.\n");
|
||||
KPrintf("board initialization......\n");
|
||||
#endif
|
||||
|
||||
InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file board.h
|
||||
* @brief define stm32f407-st-discovery-board init configure and start-up function
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-04-25
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: board.h
|
||||
Description: define stm32f407-st-discovery-board board init function and struct
|
||||
Others:
|
||||
History:
|
||||
1. Date: 2021-04-25
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. define stm32f407-st-discovery-board InitBoardHardware
|
||||
2. define stm32f407-st-discovery-board data and bss struct
|
||||
*************************************************/
|
||||
|
||||
#ifndef BOARD_H
|
||||
#define BOARD_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
extern int __stack_end__;
|
||||
extern unsigned int g_service_table_start;
|
||||
extern unsigned int g_service_table_end;
|
||||
|
||||
#define SURPORT_MPU
|
||||
|
||||
#define MEMORY_START_ADDRESS (&__stack_end__)
|
||||
#define MEM_OFFSET 128
|
||||
#define MEMORY_END_ADDRESS (0x20000000 + MEM_OFFSET * 1024)
|
||||
|
||||
|
||||
#ifdef SEPARATE_COMPILE
|
||||
typedef int (*main_t)(int argc, char *argv[]);
|
||||
typedef void (*exit_t)(void);
|
||||
struct userspace_s
|
||||
{
|
||||
main_t us_entrypoint;
|
||||
exit_t us_taskquit;
|
||||
uintptr_t us_textstart;
|
||||
uintptr_t us_textend;
|
||||
uintptr_t us_datasource;
|
||||
uintptr_t us_datastart;
|
||||
uintptr_t us_dataend;
|
||||
uintptr_t us_bssstart;
|
||||
uintptr_t us_bssend;
|
||||
uintptr_t us_heapend;
|
||||
};
|
||||
#define USERSPACE (( struct userspace_s *)(0x08080000))
|
||||
|
||||
#ifndef SERVICE_TABLE_ADDRESS
|
||||
#define SERVICE_TABLE_ADDRESS (0x20000000)
|
||||
#endif
|
||||
|
||||
#define USER_SRAM_SIZE 64
|
||||
#define USER_MEMORY_START_ADDRESS (USERSPACE->us_bssend)
|
||||
#define USER_MEMORY_END_ADDRESS (0x10000000 + USER_SRAM_SIZE * 1024)
|
||||
#endif
|
||||
|
||||
void InitBoardHardware(void);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,125 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file board.c
|
||||
* @brief support stm32f407-st-discovery-board init configure and start-up
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-04-25
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: board.c
|
||||
Description: support stm32f407-st-discovery-board init configure and driver/task/... init
|
||||
Others:
|
||||
History:
|
||||
1. Date: 2021-04-25
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. support stm32f407-st-discovery-board InitBoardHardware
|
||||
*************************************************/
|
||||
|
||||
#include <xiuos.h>
|
||||
#include "hardware_rcc.h"
|
||||
#include "board.h"
|
||||
#include "connect_usart.h"
|
||||
#include "misc.h"
|
||||
#include <xs_service.h>
|
||||
|
||||
|
||||
|
||||
static void ClockConfiguration()
|
||||
{
|
||||
int cr,cfgr,pllcfgr;
|
||||
int cr1,cfgr1,pllcfgr1;
|
||||
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
|
||||
PWR->CR |= PWR_CR_VOS;
|
||||
RCC_HSEConfig(RCC_HSE_ON);
|
||||
if (RCC_WaitForHSEStartUp() == SUCCESS)
|
||||
{
|
||||
RCC_HCLKConfig(RCC_SYSCLK_Div1);
|
||||
RCC_PCLK2Config(RCC_HCLK_Div2);
|
||||
RCC_PCLK1Config(RCC_HCLK_Div4);
|
||||
RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7);
|
||||
|
||||
RCC_PLLCmd(ENABLE);
|
||||
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
|
||||
|
||||
FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
|
||||
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
|
||||
|
||||
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
|
||||
}
|
||||
SystemCoreClockUpdate();
|
||||
}
|
||||
|
||||
void NVIC_Configuration(void)
|
||||
{
|
||||
#ifdef VECT_TAB_RAM
|
||||
NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
|
||||
#else
|
||||
NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
|
||||
#endif
|
||||
|
||||
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
|
||||
}
|
||||
|
||||
void SysTickConfiguration(void)
|
||||
{
|
||||
RCC_ClocksTypeDef rcc_clocks;
|
||||
uint32 cnts;
|
||||
|
||||
RCC_GetClocksFreq(&rcc_clocks);
|
||||
|
||||
cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND;
|
||||
cnts = cnts / 8;
|
||||
|
||||
SysTick_Config(cnts);
|
||||
SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
|
||||
}
|
||||
|
||||
void SysTick_Handler(int irqn, void *arg)
|
||||
{
|
||||
|
||||
TickAndTaskTimesliceUpdate();
|
||||
|
||||
}
|
||||
DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE);
|
||||
|
||||
|
||||
void InitBoardHardware()
|
||||
{
|
||||
int i = 0;
|
||||
int ret = 0;
|
||||
ClockConfiguration();
|
||||
|
||||
NVIC_Configuration();
|
||||
|
||||
SysTickConfiguration();
|
||||
#ifdef BSP_USING_UART
|
||||
Stm32HwUsartInit();
|
||||
#endif
|
||||
#ifdef KERNEL_CONSOLE
|
||||
InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
|
||||
|
||||
RCC_ClocksTypeDef rcc_clocks;
|
||||
RCC_GetClocksFreq(&rcc_clocks);
|
||||
KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency);
|
||||
|
||||
KPrintf("\nconsole init completed.\n");
|
||||
KPrintf("board initialization......\n");
|
||||
#endif
|
||||
|
||||
InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,125 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file board.c
|
||||
* @brief support stm32f407-st-discovery-board init configure and start-up
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-04-25
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: board.c
|
||||
Description: support stm32f407-st-discovery-board init configure and driver/task/... init
|
||||
Others:
|
||||
History:
|
||||
1. Date: 2021-04-25
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. support stm32f407-st-discovery-board InitBoardHardware
|
||||
*************************************************/
|
||||
|
||||
#include <xiuos.h>
|
||||
#include "hardware_rcc.h"
|
||||
#include "board.h"
|
||||
#include "connect_usart.h"
|
||||
#include "misc.h"
|
||||
#include <xs_service.h>
|
||||
|
||||
|
||||
|
||||
static void ClockConfiguration()
|
||||
{
|
||||
int cr,cfgr,pllcfgr;
|
||||
int cr1,cfgr1,pllcfgr1;
|
||||
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
|
||||
PWR->CR |= PWR_CR_VOS;
|
||||
RCC_HSEConfig(RCC_HSE_ON);
|
||||
if (RCC_WaitForHSEStartUp() == SUCCESS)
|
||||
{
|
||||
RCC_HCLKConfig(RCC_SYSCLK_Div1);
|
||||
RCC_PCLK2Config(RCC_HCLK_Div2);
|
||||
RCC_PCLK1Config(RCC_HCLK_Div4);
|
||||
RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7);
|
||||
|
||||
RCC_PLLCmd(ENABLE);
|
||||
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
|
||||
|
||||
FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
|
||||
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
|
||||
|
||||
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
|
||||
}
|
||||
SystemCoreClockUpdate();
|
||||
}
|
||||
|
||||
void NVIC_Configuration(void)
|
||||
{
|
||||
#ifdef VECT_TAB_RAM
|
||||
NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
|
||||
#else
|
||||
NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
|
||||
#endif
|
||||
|
||||
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
|
||||
}
|
||||
|
||||
void SysTickConfiguration(void)
|
||||
{
|
||||
RCC_ClocksTypeDef rcc_clocks;
|
||||
uint32 cnts;
|
||||
|
||||
RCC_GetClocksFreq(&rcc_clocks);
|
||||
|
||||
cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND;
|
||||
cnts = cnts / 8;
|
||||
|
||||
SysTick_Config(cnts);
|
||||
SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
|
||||
}
|
||||
|
||||
void SysTick_Handler(int irqn, void *arg)
|
||||
{
|
||||
|
||||
TickAndTaskTimesliceUpdate();
|
||||
|
||||
}
|
||||
DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE);
|
||||
|
||||
|
||||
void InitBoardHardware()
|
||||
{
|
||||
int i = 0;
|
||||
int ret = 0;
|
||||
ClockConfiguration();
|
||||
|
||||
NVIC_Configuration();
|
||||
|
||||
SysTickConfiguration();
|
||||
#ifdef BSP_USING_UART
|
||||
Stm32HwUsartInit();
|
||||
#endif
|
||||
#ifdef KERNEL_CONSOLE
|
||||
InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
|
||||
|
||||
RCC_ClocksTypeDef rcc_clocks;
|
||||
RCC_GetClocksFreq(&rcc_clocks);
|
||||
KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency);
|
||||
|
||||
KPrintf("\nconsole init completed.\n");
|
||||
KPrintf("board initialization......\n");
|
||||
#endif
|
||||
|
||||
InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,125 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file board.c
|
||||
* @brief support stm32f407-st-discovery-board init configure and start-up
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-04-25
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: board.c
|
||||
Description: support stm32f407-st-discovery-board init configure and driver/task/... init
|
||||
Others:
|
||||
History:
|
||||
1. Date: 2021-04-25
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. support stm32f407-st-discovery-board InitBoardHardware
|
||||
*************************************************/
|
||||
|
||||
#include <xiuos.h>
|
||||
#include "hardware_rcc.h"
|
||||
#include "board.h"
|
||||
#include "connect_usart.h"
|
||||
#include "misc.h"
|
||||
#include <xs_service.h>
|
||||
|
||||
|
||||
|
||||
static void ClockConfiguration()
|
||||
{
|
||||
int cr,cfgr,pllcfgr;
|
||||
int cr1,cfgr1,pllcfgr1;
|
||||
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
|
||||
PWR->CR |= PWR_CR_VOS;
|
||||
RCC_HSEConfig(RCC_HSE_ON);
|
||||
if (RCC_WaitForHSEStartUp() == SUCCESS)
|
||||
{
|
||||
RCC_HCLKConfig(RCC_SYSCLK_Div1);
|
||||
RCC_PCLK2Config(RCC_HCLK_Div2);
|
||||
RCC_PCLK1Config(RCC_HCLK_Div4);
|
||||
RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7);
|
||||
|
||||
RCC_PLLCmd(ENABLE);
|
||||
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
|
||||
|
||||
FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
|
||||
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
|
||||
|
||||
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
|
||||
}
|
||||
SystemCoreClockUpdate();
|
||||
}
|
||||
|
||||
void NVIC_Configuration(void)
|
||||
{
|
||||
#ifdef VECT_TAB_RAM
|
||||
NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
|
||||
#else
|
||||
NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
|
||||
#endif
|
||||
|
||||
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
|
||||
}
|
||||
|
||||
void SysTickConfiguration(void)
|
||||
{
|
||||
RCC_ClocksTypeDef rcc_clocks;
|
||||
uint32 cnts;
|
||||
|
||||
RCC_GetClocksFreq(&rcc_clocks);
|
||||
|
||||
cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND;
|
||||
cnts = cnts / 8;
|
||||
|
||||
SysTick_Config(cnts);
|
||||
SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
|
||||
}
|
||||
|
||||
void SysTick_Handler(int irqn, void *arg)
|
||||
{
|
||||
|
||||
TickAndTaskTimesliceUpdate();
|
||||
|
||||
}
|
||||
DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE);
|
||||
|
||||
|
||||
void InitBoardHardware()
|
||||
{
|
||||
int i = 0;
|
||||
int ret = 0;
|
||||
ClockConfiguration();
|
||||
|
||||
NVIC_Configuration();
|
||||
|
||||
SysTickConfiguration();
|
||||
#ifdef BSP_USING_UART
|
||||
Stm32HwUsartInit();
|
||||
#endif
|
||||
#ifdef KERNEL_CONSOLE
|
||||
InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
|
||||
|
||||
RCC_ClocksTypeDef rcc_clocks;
|
||||
RCC_GetClocksFreq(&rcc_clocks);
|
||||
KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency);
|
||||
|
||||
KPrintf("\nconsole init completed.\n");
|
||||
KPrintf("board initialization......\n");
|
||||
#endif
|
||||
|
||||
InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
export CROSS_COMPILE ?=/usr/bin/arm-none-eabi-
|
||||
|
||||
export CFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb -Werror
|
||||
export AFLAGS := -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb -gdwarf-2
|
||||
export LFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_stm32f407-st-discovery.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds
|
||||
export CXXFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -Werror
|
||||
|
||||
export APPLFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
|
||||
|
||||
|
||||
export DEFINES := -DHAVE_CCONFIG_H -DSTM32F407xx -DUSE_HAL_DRIVER -DHAVE_SIGINFO
|
||||
|
||||
export USING_NEWLIB =1
|
||||
export USING_VFS = 1
|
||||
export USING_SPI = 1
|
||||
export ARCH = arm
|
||||
export USING_LORA = 1
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
export CROSS_COMPILE ?=/usr/bin/arm-none-eabi-
|
||||
|
||||
export CFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb -Werror
|
||||
export AFLAGS := -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb -gdwarf-2
|
||||
export LFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_stm32f407-st-discovery.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds
|
||||
export CXXFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -Werror
|
||||
|
||||
export APPLFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
|
||||
|
||||
|
||||
export DEFINES := -DHAVE_CCONFIG_H -DSTM32F407xx -DUSE_HAL_DRIVER -DHAVE_SIGINFO
|
||||
|
||||
export ARCH = arm
|
||||
export USING_LORA = 1
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
export CROSS_COMPILE ?=/usr/bin/arm-none-eabi-
|
||||
|
||||
export CFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb -Werror
|
||||
export AFLAGS := -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb -gdwarf-2
|
||||
export LFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_stm32f407-st-discovery.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds
|
||||
export CXXFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -Werror
|
||||
|
||||
export APPLFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
|
||||
|
||||
|
||||
export DEFINES := -DHAVE_CCONFIG_H -DSTM32F407xx -DUSE_HAL_DRIVER -DHAVE_SIGINFO
|
||||
|
||||
export ARCH = arm
|
||||
export USING_LORA = 1
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
export CROSS_COMPILE ?=/usr/bin/arm-none-eabi-
|
||||
|
||||
export CFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb -Werror
|
||||
export AFLAGS := -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb -gdwarf-2
|
||||
export LFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_stm32f407-st-discovery.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds
|
||||
export CXXFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -Werror
|
||||
|
||||
export APPLFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
|
||||
|
||||
|
||||
export DEFINES := -DHAVE_CCONFIG_H
|
||||
|
||||
export ARCH = arm
|
||||
export USING_LORA = 1
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
export CROSS_COMPILE ?=/usr/bin/arm-none-eabi-
|
||||
|
||||
export CFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb -Werror
|
||||
export AFLAGS := -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb -gdwarf-2
|
||||
export LFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_stm32f407-st-discovery.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds
|
||||
export CXXFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -Werror
|
||||
|
||||
export APPLFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
|
||||
|
||||
|
||||
export DEFINES := -DHAVE_CCONFIG_H
|
||||
|
||||
export ARCH = arm
|
||||
export USING_LORA = 1
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file connect_usart.h
|
||||
* @brief define stm32f407-st-discovery-board usart function and struct
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-04-25
|
||||
*/
|
||||
|
||||
#ifndef CONNECT_USART_H
|
||||
#define CONNECT_USART_H
|
||||
|
||||
#include <device.h>
|
||||
#include "hardware_usart.h"
|
||||
#include "hardware_dma.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define KERNEL_CONSOLE_BUS_NAME SERIAL_BUS_NAME_1
|
||||
#define KERNEL_CONSOLE_DRV_NAME SERIAL_DRV_NAME_1
|
||||
#define KERNEL_CONSOLE_DEVICE_NAME SERIAL_1_DEVICE_NAME_0
|
||||
|
||||
struct UsartHwCfg
|
||||
{
|
||||
USART_TypeDef *uart_device;
|
||||
IRQn_Type irq;
|
||||
};
|
||||
|
||||
struct Stm32Usart
|
||||
{
|
||||
struct Stm32UsartDma
|
||||
{
|
||||
DMA_Stream_TypeDef *RxStream;
|
||||
uint32 RxCh;
|
||||
uint32 RxFlag;
|
||||
uint8 RxIrqCh;
|
||||
x_size_t SettingRecvLen;
|
||||
x_size_t LastRecvIndex;
|
||||
} dma;
|
||||
|
||||
struct SerialBus serial_bus;
|
||||
};
|
||||
|
||||
int Stm32HwUsartInit(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file connect_usart.h
|
||||
* @brief define stm32f407-st-discovery-board usart function and struct
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-04-25
|
||||
*/
|
||||
|
||||
#ifndef CONNECT_USART_H
|
||||
#define CONNECT_USART_H
|
||||
|
||||
#include <device.h>
|
||||
#include "hardware_usart.h"
|
||||
#include "hardware_dma.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define KERNEL_CONSOLE_BUS_NAME SERIAL_BUS_NAME_1
|
||||
#define KERNEL_CONSOLE_DRV_NAME SERIAL_DRV_NAME_1
|
||||
#define KERNEL_CONSOLE_DEVICE_NAME SERIAL_1_DEVICE_NAME_0
|
||||
|
||||
struct UsartHwCfg
|
||||
{
|
||||
USART_TypeDef *uart_device;
|
||||
IRQn_Type irq;
|
||||
};
|
||||
|
||||
struct Stm32Usart
|
||||
{
|
||||
struct Stm32UsartDma
|
||||
{
|
||||
DMA_Stream_TypeDef *RxStream;
|
||||
uint32 RxCh;
|
||||
uint32 RxFlag;
|
||||
uint8 RxIrqCh;
|
||||
x_size_t SettingRecvLen;
|
||||
x_size_t LastRecvIndex;
|
||||
} dma;
|
||||
|
||||
struct SerialBus serial_bus;
|
||||
};
|
||||
|
||||
int InitHwUsart(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,858 @@
|
|||
/*
|
||||
* Copyright (c) 2020 RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file connect_usart.c
|
||||
* @brief support stm32f407-st-discovery-board usart function and register to bus framework
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-04-25
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: connect_uart.c
|
||||
Description: support stm32f407-st-discovery-board usart configure and uart bus register function
|
||||
Others: take RT-Thread v4.0.2/bsp/stm32/libraries/HAL_Drivers/drv_usart.c for references
|
||||
https://github.com/RT-Thread/rt-thread/tree/v4.0.2
|
||||
History:
|
||||
1. Date: 2021-04-25
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. support stm32f407-st-discovery-board usart configure, write and read
|
||||
2. support stm32f407-st-discovery-board usart bus device and driver register
|
||||
*************************************************/
|
||||
|
||||
#include "stm32f4xx.h"
|
||||
#include "board.h"
|
||||
#include "misc.h"
|
||||
#include "connect_usart.h"
|
||||
#include "hardware_gpio.h"
|
||||
#include "hardware_rcc.h"
|
||||
|
||||
/* UART GPIO define. */
|
||||
#define UART1_GPIO_TX GPIO_Pin_6
|
||||
#define UART1_TX_PIN_SOURCE GPIO_PinSource6
|
||||
#define UART1_GPIO_RX GPIO_Pin_7
|
||||
#define UART1_RX_PIN_SOURCE GPIO_PinSource7
|
||||
#define UART1_GPIO GPIOB
|
||||
#define UART1_GPIO_RCC RCC_AHB1Periph_GPIOB
|
||||
#define RCC_APBPeriph_UART1 RCC_APB2Periph_USART1
|
||||
|
||||
#define UART2_GPIO_TX GPIO_Pin_2
|
||||
#define UART2_TX_PIN_SOURCE GPIO_PinSource2
|
||||
#define UART2_GPIO_RX GPIO_Pin_3
|
||||
#define UART2_RX_PIN_SOURCE GPIO_PinSource3
|
||||
#define UART2_GPIO GPIOA
|
||||
#define UART2_GPIO_RCC RCC_AHB1Periph_GPIOA
|
||||
#define RCC_APBPeriph_UART2 RCC_APB1Periph_USART2
|
||||
|
||||
#define UART3_GPIO_TX GPIO_Pin_8
|
||||
#define UART3_TX_PIN_SOURCE GPIO_PinSource8
|
||||
#define UART3_GPIO_RX GPIO_Pin_9
|
||||
#define UART3_RX_PIN_SOURCE GPIO_PinSource9
|
||||
#define UART3_GPIO GPIOD
|
||||
#define UART3_GPIO_RCC RCC_AHB1Periph_GPIOD
|
||||
#define RCC_APBPeriph_UART3 RCC_APB1Periph_USART3
|
||||
|
||||
#define UART4_GPIO_TX GPIO_Pin_10
|
||||
#define UART4_TX_PIN_SOURCE GPIO_PinSource10
|
||||
#define UART4_GPIO_RX GPIO_Pin_11
|
||||
#define UART4_RX_PIN_SOURCE GPIO_PinSource11
|
||||
#define UART4_GPIO GPIOC
|
||||
#define UART4_GPIO_RCC RCC_AHB1Periph_GPIOC
|
||||
#define RCC_APBPeriph_UART4 RCC_APB1Periph_UART4
|
||||
|
||||
#define UART5_GPIO_TX GPIO_Pin_12
|
||||
#define UART5_TX_PIN_SOURCE GPIO_PinSource12
|
||||
#define UART5_GPIO_RX GPIO_Pin_2
|
||||
#define UART5_RX_PIN_SOURCE GPIO_PinSource2
|
||||
#define UART5_TX GPIOC
|
||||
#define UART5_RX GPIOD
|
||||
#define UART5_GPIO_RCC_TX RCC_AHB1Periph_GPIOC
|
||||
#define UART5_GPIO_RCC_RX RCC_AHB1Periph_GPIOD
|
||||
#define RCC_APBPeriph_UART5 RCC_APB1Periph_UART5
|
||||
|
||||
#define UART_ENABLE_IRQ(n) NVIC_EnableIRQ((n))
|
||||
#define UART_DISABLE_IRQ(n) NVIC_DisableIRQ((n))
|
||||
|
||||
static void RCCConfiguration(void)
|
||||
{
|
||||
#ifdef BSP_USING_USART1
|
||||
RCC_AHB1PeriphClockCmd(UART1_GPIO_RCC, ENABLE);
|
||||
RCC_APB2PeriphClockCmd(RCC_APBPeriph_UART1, ENABLE);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_USART2
|
||||
RCC_AHB1PeriphClockCmd(UART2_GPIO_RCC, ENABLE);
|
||||
RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART2, ENABLE);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_USART3
|
||||
RCC_AHB1PeriphClockCmd(UART3_GPIO_RCC, ENABLE);
|
||||
RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART3, ENABLE);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART4
|
||||
RCC_AHB1PeriphClockCmd(UART4_GPIO_RCC, ENABLE);
|
||||
RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART4, ENABLE);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART5
|
||||
RCC_AHB1PeriphClockCmd(UART5_GPIO_RCC_TX | UART5_GPIO_RCC_RX, ENABLE);
|
||||
RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART5, ENABLE);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void GPIOConfiguration(void)
|
||||
{
|
||||
GPIO_InitTypeDef gpio_initstructure;
|
||||
|
||||
gpio_initstructure.GPIO_Mode = GPIO_Mode_AF;
|
||||
gpio_initstructure.GPIO_OType = GPIO_OType_PP;
|
||||
gpio_initstructure.GPIO_PuPd = GPIO_PuPd_UP;
|
||||
gpio_initstructure.GPIO_Speed = GPIO_Speed_2MHz;
|
||||
|
||||
#ifdef BSP_USING_USART1
|
||||
gpio_initstructure.GPIO_Pin = UART1_GPIO_RX | UART1_GPIO_TX;
|
||||
GPIO_PinAFConfig(UART1_GPIO, UART1_TX_PIN_SOURCE, GPIO_AF_USART1);
|
||||
GPIO_PinAFConfig(UART1_GPIO, UART1_RX_PIN_SOURCE, GPIO_AF_USART1);
|
||||
|
||||
GPIO_Init(UART1_GPIO, &gpio_initstructure);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_USART2
|
||||
gpio_initstructure.GPIO_Pin = UART2_GPIO_RX | UART2_GPIO_TX;
|
||||
GPIO_PinAFConfig(UART2_GPIO, UART2_TX_PIN_SOURCE, GPIO_AF_USART2);
|
||||
GPIO_PinAFConfig(UART2_GPIO, UART2_RX_PIN_SOURCE, GPIO_AF_USART2);
|
||||
|
||||
GPIO_Init(UART2_GPIO, &gpio_initstructure);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_USART3
|
||||
gpio_initstructure.GPIO_Pin = UART3_GPIO_TX | UART3_GPIO_RX;
|
||||
GPIO_PinAFConfig(UART3_GPIO, UART3_TX_PIN_SOURCE, GPIO_AF_USART3);
|
||||
GPIO_PinAFConfig(UART3_GPIO, UART3_RX_PIN_SOURCE, GPIO_AF_USART3);
|
||||
|
||||
GPIO_Init(UART3_GPIO, &gpio_initstructure);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART4
|
||||
gpio_initstructure.GPIO_Pin = UART4_GPIO_TX | UART4_GPIO_RX;
|
||||
GPIO_PinAFConfig(UART4_GPIO, UART4_TX_PIN_SOURCE, GPIO_AF_UART4);
|
||||
GPIO_PinAFConfig(UART4_GPIO, UART4_RX_PIN_SOURCE, GPIO_AF_UART4);
|
||||
|
||||
GPIO_Init(UART4_GPIO, &gpio_initstructure);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART5
|
||||
gpio_initstructure.GPIO_Pin = UART5_GPIO_TX;
|
||||
GPIO_PinAFConfig(UART5_TX, UART5_TX_PIN_SOURCE, GPIO_AF_UART5);
|
||||
GPIO_Init(UART5_TX, &gpio_initstructure);
|
||||
|
||||
gpio_initstructure.GPIO_Pin = UART5_GPIO_RX;
|
||||
GPIO_PinAFConfig(UART5_RX, UART5_RX_PIN_SOURCE, GPIO_AF_UART5);
|
||||
GPIO_Init(UART5_RX, &gpio_initstructure);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void NVIC_Configuration(IRQn_Type irq)
|
||||
{
|
||||
NVIC_InitTypeDef NVIC_InitStructure;
|
||||
|
||||
NVIC_InitStructure.NVIC_IRQChannel = irq;
|
||||
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
|
||||
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
|
||||
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||
NVIC_Init(&NVIC_InitStructure);
|
||||
}
|
||||
|
||||
static void DmaUartConfig(struct Stm32UsartDma *dma, USART_TypeDef *uart_device, uint32_t SettingRecvLen, void *mem_base_addr)
|
||||
{
|
||||
DMA_InitTypeDef DMA_InitStructure;
|
||||
|
||||
dma->SettingRecvLen = SettingRecvLen;
|
||||
DMA_DeInit(dma->RxStream);
|
||||
while (DMA_GetCmdStatus(dma->RxStream) != DISABLE);
|
||||
DMA_InitStructure.DMA_Channel = dma->RxCh;
|
||||
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t) &(uart_device->DR);
|
||||
DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)mem_base_addr;
|
||||
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory;
|
||||
DMA_InitStructure.DMA_BufferSize = dma->SettingRecvLen;
|
||||
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
|
||||
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
|
||||
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
|
||||
DMA_InitStructure.DMA_MemoryDataSize = DMA_PeripheralDataSize_Byte;
|
||||
DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
|
||||
DMA_InitStructure.DMA_Priority = DMA_Priority_High;
|
||||
DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
|
||||
DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
|
||||
DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
|
||||
DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
|
||||
DMA_Init(dma->RxStream, &DMA_InitStructure);
|
||||
}
|
||||
|
||||
static void DMAConfiguration(struct SerialHardwareDevice *serial_dev, USART_TypeDef *uart_device)
|
||||
{
|
||||
struct Stm32Usart *serial = CONTAINER_OF(serial_dev->haldev.owner_bus, struct Stm32Usart, serial_bus);
|
||||
struct Stm32UsartDma *dma = &serial->dma;
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
|
||||
|
||||
NVIC_InitTypeDef NVIC_InitStructure;
|
||||
|
||||
USART_ITConfig(uart_device, USART_IT_IDLE , ENABLE);
|
||||
|
||||
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);
|
||||
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE);
|
||||
|
||||
DmaUartConfig(dma, uart_device, serial_cfg->data_cfg.serial_buffer_size, serial_dev->serial_fifo.serial_rx->serial_rx_buffer);
|
||||
|
||||
DMA_ClearFlag(dma->RxStream, dma->RxFlag);
|
||||
DMA_ITConfig(dma->RxStream, DMA_IT_TC, ENABLE);
|
||||
USART_DMACmd(uart_device, USART_DMAReq_Rx, ENABLE);
|
||||
DMA_Cmd(dma->RxStream, ENABLE);
|
||||
|
||||
NVIC_InitStructure.NVIC_IRQChannel = dma->RxIrqCh;
|
||||
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
|
||||
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
|
||||
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||
NVIC_Init(&NVIC_InitStructure);
|
||||
}
|
||||
|
||||
static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struct SerialCfgParam *serial_cfg_new)
|
||||
{
|
||||
struct SerialDataCfg *data_cfg_default = &serial_cfg_default->data_cfg;
|
||||
struct SerialDataCfg *data_cfg_new = &serial_cfg_new->data_cfg;
|
||||
|
||||
if((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) {
|
||||
data_cfg_default->serial_baud_rate = data_cfg_new->serial_baud_rate;
|
||||
}
|
||||
|
||||
if((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order)) {
|
||||
data_cfg_default->serial_bit_order = data_cfg_new->serial_bit_order;
|
||||
}
|
||||
|
||||
if((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)) {
|
||||
data_cfg_default->serial_buffer_size = data_cfg_new->serial_buffer_size;
|
||||
}
|
||||
|
||||
if((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits)) {
|
||||
data_cfg_default->serial_data_bits = data_cfg_new->serial_data_bits;
|
||||
}
|
||||
|
||||
if((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode)) {
|
||||
data_cfg_default->serial_invert_mode = data_cfg_new->serial_invert_mode;
|
||||
}
|
||||
|
||||
if((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)) {
|
||||
data_cfg_default->serial_parity_mode = data_cfg_new->serial_parity_mode;
|
||||
}
|
||||
|
||||
if((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
|
||||
data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
|
||||
}
|
||||
}
|
||||
|
||||
static uint32 Stm32SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info)
|
||||
{
|
||||
NULL_PARAM_CHECK(serial_drv);
|
||||
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
|
||||
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
|
||||
|
||||
if (configure_info->private_data) {
|
||||
struct SerialCfgParam *serial_cfg_new = (struct SerialCfgParam *)configure_info->private_data;
|
||||
SerialCfgParamCheck(serial_cfg, serial_cfg_new);
|
||||
}
|
||||
|
||||
USART_InitTypeDef USART_InitStructure;
|
||||
|
||||
USART_InitStructure.USART_BaudRate = serial_cfg->data_cfg.serial_baud_rate;
|
||||
|
||||
if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_8) {
|
||||
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
|
||||
} else if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_9) {
|
||||
USART_InitStructure.USART_WordLength = USART_WordLength_9b;
|
||||
}
|
||||
|
||||
if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_1){
|
||||
USART_InitStructure.USART_StopBits = USART_StopBits_1;
|
||||
} else if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_2) {
|
||||
USART_InitStructure.USART_StopBits = USART_StopBits_2;
|
||||
}
|
||||
|
||||
if (serial_cfg->data_cfg.serial_parity_mode == PARITY_NONE) {
|
||||
USART_InitStructure.USART_Parity = USART_Parity_No;
|
||||
} else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_ODD) {
|
||||
USART_InitStructure.USART_Parity = USART_Parity_Odd;
|
||||
} else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_EVEN) {
|
||||
USART_InitStructure.USART_Parity = USART_Parity_Even;
|
||||
}
|
||||
|
||||
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
||||
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
|
||||
USART_Init(serial_hw_cfg->uart_device, &USART_InitStructure);
|
||||
|
||||
USART_Cmd(serial_hw_cfg->uart_device, ENABLE);
|
||||
|
||||
return EOK;
|
||||
}
|
||||
|
||||
static uint32 Stm32SerialConfigure(struct SerialDriver *serial_drv, int serial_operation_cmd)
|
||||
{
|
||||
NULL_PARAM_CHECK(serial_drv);
|
||||
|
||||
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
|
||||
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
|
||||
struct SerialDevParam *serial_dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
|
||||
|
||||
switch (serial_operation_cmd)
|
||||
{
|
||||
case OPER_CLR_INT:
|
||||
UART_DISABLE_IRQ(serial_hw_cfg->irq);
|
||||
USART_ITConfig(serial_hw_cfg->uart_device, USART_IT_RXNE, DISABLE);
|
||||
break;
|
||||
case OPER_SET_INT:
|
||||
UART_ENABLE_IRQ(serial_hw_cfg->irq);
|
||||
USART_ITConfig(serial_hw_cfg->uart_device, USART_IT_RXNE, ENABLE);
|
||||
break;
|
||||
case OPER_CONFIG :
|
||||
if (SIGN_OPER_DMA_RX == serial_dev_param->serial_set_mode){
|
||||
DMAConfiguration(serial_dev, serial_hw_cfg->uart_device);
|
||||
}
|
||||
}
|
||||
|
||||
return EOK;
|
||||
}
|
||||
|
||||
static int Stm32SerialPutchar(struct SerialHardwareDevice *serial_dev, char c)
|
||||
{
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
|
||||
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
|
||||
|
||||
while (!(serial_hw_cfg->uart_device->SR & USART_FLAG_TXE));
|
||||
serial_hw_cfg->uart_device->DR = c;
|
||||
|
||||
return EOK;
|
||||
}
|
||||
|
||||
static int Stm32SerialGetchar(struct SerialHardwareDevice *serial_dev)
|
||||
{
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
|
||||
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
|
||||
|
||||
int ch = -1;
|
||||
if (serial_hw_cfg->uart_device->SR & USART_FLAG_RXNE) {
|
||||
ch = serial_hw_cfg->uart_device->DR & 0xff;
|
||||
}
|
||||
|
||||
return ch;
|
||||
}
|
||||
|
||||
static void DmaUartRxIdleIsr(struct SerialHardwareDevice *serial_dev, struct Stm32UsartDma *dma, USART_TypeDef *uart_device)
|
||||
{
|
||||
x_base level = CriticalAreaLock();
|
||||
|
||||
x_size_t recv_total_index = dma->SettingRecvLen - DMA_GetCurrDataCounter(dma->RxStream);
|
||||
x_size_t recv_len = recv_total_index - dma->LastRecvIndex;
|
||||
dma->LastRecvIndex = recv_total_index;
|
||||
CriticalAreaUnLock(level);
|
||||
|
||||
if (recv_len) SerialSetIsr(serial_dev, SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
|
||||
|
||||
USART_ReceiveData(uart_device);
|
||||
}
|
||||
|
||||
static void DmaRxDoneIsr(struct Stm32Usart *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev)
|
||||
{
|
||||
struct Stm32UsartDma *dma = &serial->dma;
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
|
||||
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
|
||||
|
||||
if (DMA_GetFlagStatus(dma->RxStream, dma->RxFlag) != RESET) {
|
||||
x_base level = CriticalAreaLock();
|
||||
|
||||
x_size_t recv_len = dma->SettingRecvLen - dma->LastRecvIndex;
|
||||
dma->LastRecvIndex = 0;
|
||||
CriticalAreaUnLock(level);
|
||||
|
||||
if (recv_len) SerialSetIsr(serial_dev, SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
|
||||
|
||||
DMA_ClearFlag(dma->RxStream, dma->RxFlag);
|
||||
}
|
||||
}
|
||||
|
||||
static void UartIsr(struct Stm32Usart *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev)
|
||||
{
|
||||
struct Stm32UsartDma *dma = &serial->dma;
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
|
||||
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
|
||||
|
||||
if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_RXNE) != RESET) {
|
||||
SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND);
|
||||
USART_ClearITPendingBit(serial_hw_cfg->uart_device, USART_IT_RXNE);
|
||||
}
|
||||
if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_IDLE) != RESET) {
|
||||
DmaUartRxIdleIsr(serial_dev, dma, serial_hw_cfg->uart_device);
|
||||
}
|
||||
if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_TC) != RESET) {
|
||||
USART_ClearITPendingBit(serial_hw_cfg->uart_device, USART_IT_TC);
|
||||
}
|
||||
if (USART_GetFlagStatus(serial_hw_cfg->uart_device, USART_FLAG_ORE) == SET) {
|
||||
USART_ReceiveData(serial_hw_cfg->uart_device);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef BSP_USING_USART1
|
||||
struct Stm32Usart serial_1;
|
||||
struct SerialDriver serial_driver_1;
|
||||
struct SerialHardwareDevice serial_device_1;
|
||||
|
||||
static const struct Stm32UsartDma usart_dma_1 =
|
||||
{
|
||||
DMA2_Stream5,
|
||||
DMA_Channel_4,
|
||||
DMA_FLAG_TCIF5,
|
||||
DMA2_Stream5_IRQn,
|
||||
0,
|
||||
0,
|
||||
};
|
||||
|
||||
void USART1_IRQHandler(int irq_num, void *arg)
|
||||
{
|
||||
UartIsr(&serial_1, &serial_driver_1, &serial_device_1);
|
||||
}
|
||||
DECLARE_HW_IRQ(USART1_IRQn, USART1_IRQHandler, NONE);
|
||||
|
||||
void DMA2_Stream5_IRQHandler(int irq_num, void *arg) {
|
||||
DmaRxDoneIsr(&serial_1, &serial_driver_1, &serial_device_1);
|
||||
}
|
||||
DECLARE_HW_IRQ(DMA2_Stream5_IRQn, DMA2_Stream5_IRQHandler, NONE);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_USART2
|
||||
struct Stm32Usart serial_2;
|
||||
struct SerialDriver serial_driver_2;
|
||||
struct SerialHardwareDevice serial_device_2;
|
||||
|
||||
static const struct Stm32UsartDma usart_dma_2 =
|
||||
{
|
||||
DMA1_Stream5,
|
||||
DMA_Channel_4,
|
||||
DMA_FLAG_TCIF5,
|
||||
DMA1_Stream5_IRQn,
|
||||
0,
|
||||
0,
|
||||
};
|
||||
|
||||
void USART2_IRQHandler(int irq_num, void *arg)
|
||||
{
|
||||
UartIsr(&serial_2, &serial_driver_2, &serial_device_2);
|
||||
}
|
||||
DECLARE_HW_IRQ(USART2_IRQn, USART2_IRQHandler, NONE);
|
||||
|
||||
void DMA1_Stream5_IRQHandler(int irq_num, void *arg) {
|
||||
DmaRxDoneIsr(&serial_2, &serial_driver_2, &serial_device_2);
|
||||
}
|
||||
DECLARE_HW_IRQ(DMA1_Stream5_IRQn, DMA1_Stream5_IRQHandler, NONE);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_USART3
|
||||
struct Stm32Usart serial_3;
|
||||
struct SerialDriver serial_driver_3;
|
||||
struct SerialHardwareDevice serial_device_3;
|
||||
|
||||
static const struct Stm32UsartDma usart_dma_3 =
|
||||
{
|
||||
DMA1_Stream1,
|
||||
DMA_Channel_4,
|
||||
DMA_FLAG_TCIF1,
|
||||
DMA1_Stream1_IRQn,
|
||||
0,
|
||||
0,
|
||||
};
|
||||
|
||||
void USART3_IRQHandler(int irq_num, void *arg)
|
||||
{
|
||||
UartIsr(&serial_3, &serial_driver_3, &serial_device_3);
|
||||
}
|
||||
DECLARE_HW_IRQ(USART3_IRQn, USART3_IRQHandler, NONE);
|
||||
|
||||
void DMA1_Stream1_IRQHandler(int irq_num, void *arg) {
|
||||
DmaRxDoneIsr(&serial_3, &serial_driver_3, &serial_device_3);
|
||||
}
|
||||
DECLARE_HW_IRQ(DMA1_Stream1_IRQn, DMA1_Stream1_IRQHandler, NONE);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART4
|
||||
struct Stm32Usart serial_4;
|
||||
struct SerialDriver serial_driver_4;
|
||||
struct SerialHardwareDevice serial_device_4;
|
||||
|
||||
static const struct Stm32UsartDma uart_dma_4 =
|
||||
{
|
||||
DMA1_Stream2,
|
||||
DMA_Channel_4,
|
||||
DMA_FLAG_TCIF2,
|
||||
DMA1_Stream2_IRQn,
|
||||
0,
|
||||
0,
|
||||
};
|
||||
|
||||
void UART4_IRQHandler(int irq_num, void *arg)
|
||||
{
|
||||
UartIsr(&serial_4, &serial_driver_4, &serial_device_4);
|
||||
}
|
||||
DECLARE_HW_IRQ(UART4_IRQn, UART4_IRQHandler, NONE);
|
||||
|
||||
void DMA1_Stream2_IRQHandler(int irq_num, void *arg) {
|
||||
DmaRxDoneIsr(&serial_4, &serial_driver_4, &serial_device_4);
|
||||
}
|
||||
DECLARE_HW_IRQ(DMA1_Stream2_IRQn, DMA1_Stream2_IRQHandler, NONE);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART5
|
||||
struct Stm32Usart serial_5;
|
||||
struct SerialDriver serial_driver_5;
|
||||
struct SerialHardwareDevice serial_device_5;
|
||||
|
||||
static const struct Stm32UsartDma uart_dma_5 =
|
||||
{
|
||||
DMA1_Stream0,
|
||||
DMA_Channel_4,
|
||||
DMA_FLAG_TCIF0,
|
||||
DMA1_Stream0_IRQn,
|
||||
0,
|
||||
0,
|
||||
};
|
||||
|
||||
void UART5_IRQHandler(int irq_num, void *arg)
|
||||
{
|
||||
UartIsr(&serial_5, &serial_driver_5, &serial_device_5);
|
||||
}
|
||||
DECLARE_HW_IRQ(UART5_IRQn, UART5_IRQHandler, NONE);
|
||||
|
||||
void DMA1_Stream0_IRQHandler(int irq_num, void *arg) {
|
||||
DmaRxDoneIsr(&serial_5, &serial_driver_5, &serial_device_5);
|
||||
}
|
||||
DECLARE_HW_IRQ(DMA1_Stream0_IRQn, DMA1_Stream0_IRQHandler, NONE);
|
||||
#endif
|
||||
|
||||
static uint32 Stm32SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
|
||||
{
|
||||
NULL_PARAM_CHECK(drv);
|
||||
NULL_PARAM_CHECK(configure_info);
|
||||
|
||||
x_err_t ret = EOK;
|
||||
int serial_operation_cmd;
|
||||
struct SerialDriver *serial_drv = (struct SerialDriver *)drv;
|
||||
|
||||
switch (configure_info->configure_cmd)
|
||||
{
|
||||
case OPE_INT:
|
||||
ret = Stm32SerialInit(serial_drv, configure_info);
|
||||
break;
|
||||
case OPE_CFG:
|
||||
serial_operation_cmd = *(int *)configure_info->private_data;
|
||||
ret = Stm32SerialConfigure(serial_drv, serial_operation_cmd);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct SerialDataCfg data_cfg_init =
|
||||
{
|
||||
.serial_baud_rate = BAUD_RATE_115200,
|
||||
.serial_data_bits = DATA_BITS_8,
|
||||
.serial_stop_bits = STOP_BITS_1,
|
||||
.serial_parity_mode = PARITY_NONE,
|
||||
.serial_bit_order = BIT_ORDER_LSB,
|
||||
.serial_invert_mode = NRZ_NORMAL,
|
||||
.serial_buffer_size = SERIAL_RB_BUFSZ,
|
||||
};
|
||||
|
||||
/*manage the serial device operations*/
|
||||
static const struct SerialDrvDone drv_done =
|
||||
{
|
||||
.init = Stm32SerialInit,
|
||||
.configure = Stm32SerialConfigure,
|
||||
};
|
||||
|
||||
/*manage the serial device hal operations*/
|
||||
static struct SerialHwDevDone hwdev_done =
|
||||
{
|
||||
.put_char = Stm32SerialPutchar,
|
||||
.get_char = Stm32SerialGetchar,
|
||||
};
|
||||
|
||||
static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver *serial_driver, const char *bus_name, const char *drv_name)
|
||||
{
|
||||
x_err_t ret = EOK;
|
||||
|
||||
/*Init the serial bus */
|
||||
ret = SerialBusInit(serial_bus, bus_name);
|
||||
if (EOK != ret) {
|
||||
KPrintf("hw_serial_init SerialBusInit error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
/*Init the serial driver*/
|
||||
ret = SerialDriverInit(serial_driver, drv_name);
|
||||
if (EOK != ret) {
|
||||
KPrintf("hw_serial_init SerialDriverInit error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
/*Attach the serial driver to the serial bus*/
|
||||
ret = SerialDriverAttachToBus(drv_name, bus_name);
|
||||
if (EOK != ret) {
|
||||
KPrintf("hw_serial_init SerialDriverAttachToBus error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*Attach the serial device to the serial bus*/
|
||||
static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *serial_param, const char *bus_name, const char *dev_name)
|
||||
{
|
||||
x_err_t ret = EOK;
|
||||
|
||||
ret = SerialDeviceRegister(serial_device, serial_param, dev_name);
|
||||
if (EOK != ret) {
|
||||
KPrintf("hw_serial_init SerialDeviceInit device %s error %d\n", dev_name, ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
ret = SerialDeviceAttachToBus(dev_name, bus_name);
|
||||
if (EOK != ret) {
|
||||
KPrintf("hw_serial_init SerialDeviceAttachToBus device %s error %d\n", dev_name, ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int InitHwUsart(void)
|
||||
{
|
||||
x_err_t ret = EOK;
|
||||
|
||||
RCCConfiguration();
|
||||
GPIOConfiguration();
|
||||
|
||||
#ifdef BSP_USING_USART1
|
||||
static struct SerialCfgParam serial_cfg_1;
|
||||
memset(&serial_cfg_1, 0, sizeof(struct SerialCfgParam));
|
||||
|
||||
static struct UsartHwCfg serial_hw_cfg_1;
|
||||
memset(&serial_hw_cfg_1, 0, sizeof(struct UsartHwCfg));
|
||||
|
||||
static struct SerialDevParam serial_dev_param_1;
|
||||
memset(&serial_dev_param_1, 0, sizeof(struct SerialDevParam));
|
||||
|
||||
serial_1.dma = usart_dma_1;
|
||||
|
||||
serial_driver_1.drv_done = &drv_done;
|
||||
serial_driver_1.configure = &Stm32SerialDrvConfigure;
|
||||
serial_device_1.hwdev_done = &hwdev_done;
|
||||
|
||||
serial_cfg_1.data_cfg = data_cfg_init;
|
||||
|
||||
serial_hw_cfg_1.uart_device = USART1;
|
||||
serial_hw_cfg_1.irq = USART1_IRQn;
|
||||
serial_cfg_1.hw_cfg.private_data = (void *)&serial_hw_cfg_1;
|
||||
serial_driver_1.private_data = (void *)&serial_cfg_1;
|
||||
|
||||
serial_dev_param_1.serial_work_mode = SIGN_OPER_INT_RX;
|
||||
serial_device_1.haldev.private_data = (void *)&serial_dev_param_1;
|
||||
|
||||
NVIC_Configuration(serial_hw_cfg_1.irq);
|
||||
|
||||
ret = BoardSerialBusInit(&serial_1.serial_bus, &serial_driver_1, SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUsart usart1 error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
ret = BoardSerialDevBend(&serial_device_1, (void *)&serial_cfg_1, SERIAL_BUS_NAME_1, SERIAL_1_DEVICE_NAME_0);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUsart usart1 error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_USART2
|
||||
static struct SerialCfgParam serial_cfg_2;
|
||||
memset(&serial_cfg_2, 0, sizeof(struct SerialCfgParam));
|
||||
|
||||
static struct UsartHwCfg serial_hw_cfg_2;
|
||||
memset(&serial_hw_cfg_2, 0, sizeof(struct UsartHwCfg));
|
||||
|
||||
static struct SerialDevParam serial_dev_param_2;
|
||||
memset(&serial_dev_param_2, 0, sizeof(struct SerialDevParam));
|
||||
|
||||
serial_2.dma = usart_dma_2;
|
||||
|
||||
serial_driver_2.drv_done = &drv_done;
|
||||
serial_driver_2.configure = &Stm32SerialDrvConfigure;
|
||||
serial_device_2.hwdev_done = &hwdev_done;
|
||||
|
||||
serial_cfg_2.data_cfg = data_cfg_init;
|
||||
|
||||
serial_hw_cfg_2.uart_device = USART2;
|
||||
serial_hw_cfg_2.irq = USART2_IRQn;
|
||||
serial_cfg_2.hw_cfg.private_data = (void *)&serial_hw_cfg_2;
|
||||
serial_driver_2.private_data = (void *)&serial_cfg_2;
|
||||
|
||||
serial_dev_param_2.serial_work_mode = SIGN_OPER_INT_RX;
|
||||
serial_device_2.haldev.private_data = (void *)&serial_dev_param_2;
|
||||
|
||||
NVIC_Configuration(serial_hw_cfg_2.irq);
|
||||
|
||||
ret = BoardSerialBusInit(&serial_2.serial_bus, &serial_driver_2, SERIAL_BUS_NAME_2, SERIAL_DRV_NAME_2);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUsart usart2 error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
ret = BoardSerialDevBend(&serial_device_2, (void *)&serial_cfg_2, SERIAL_BUS_NAME_2, SERIAL_2_DEVICE_NAME_0);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUsart usart2 error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_USART3
|
||||
static struct SerialCfgParam serial_cfg_3;
|
||||
memset(&serial_cfg_3, 0, sizeof(struct SerialCfgParam));
|
||||
|
||||
static struct UsartHwCfg serial_hw_cfg_3;
|
||||
memset(&serial_hw_cfg_3, 0, sizeof(struct UsartHwCfg));
|
||||
|
||||
static struct SerialDevParam serial_dev_param_3;
|
||||
memset(&serial_dev_param_3, 0, sizeof(struct SerialDevParam));
|
||||
|
||||
serial_3.dma = usart_dma_3;
|
||||
|
||||
serial_driver_3.drv_done = &drv_done;
|
||||
serial_driver_3.configure = &Stm32SerialDrvConfigure;
|
||||
serial_device_3.hwdev_done = &hwdev_done;
|
||||
|
||||
serial_cfg_3.data_cfg = data_cfg_init;
|
||||
|
||||
serial_hw_cfg_3.uart_device = USART3;
|
||||
serial_hw_cfg_3.irq = USART3_IRQn;
|
||||
serial_cfg_3.hw_cfg.private_data = (void *)&serial_hw_cfg_3;
|
||||
serial_driver_3.private_data = (void *)&serial_cfg_3;
|
||||
|
||||
serial_dev_param_3.serial_work_mode = SIGN_OPER_INT_RX;
|
||||
serial_device_3.haldev.private_data = (void *)&serial_dev_param_3;
|
||||
|
||||
NVIC_Configuration(serial_hw_cfg_3.irq);
|
||||
|
||||
ret = BoardSerialBusInit(&serial_3.serial_bus, &serial_driver_3, SERIAL_BUS_NAME_3, SERIAL_DRV_NAME_3);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUsart usart3 error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
ret = BoardSerialDevBend(&serial_device_3, (void *)&serial_cfg_3, SERIAL_BUS_NAME_3, SERIAL_3_DEVICE_NAME_0);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUsart usart3 error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART4
|
||||
static struct SerialCfgParam serial_cfg_4;
|
||||
memset(&serial_cfg_4, 0, sizeof(struct SerialCfgParam));
|
||||
|
||||
static struct UsartHwCfg serial_hw_cfg_4;
|
||||
memset(&serial_hw_cfg_4, 0, sizeof(struct UsartHwCfg));
|
||||
|
||||
static struct SerialDevParam serial_dev_param_4;
|
||||
memset(&serial_dev_param_4, 0, sizeof(struct SerialDevParam));
|
||||
|
||||
serial_4.dma = uart_dma_4;
|
||||
|
||||
serial_driver_4.drv_done = &drv_done;
|
||||
serial_driver_4.configure = &Stm32SerialDrvConfigure;
|
||||
serial_device_4.hwdev_done = &hwdev_done;
|
||||
|
||||
serial_cfg_4.data_cfg = data_cfg_init;
|
||||
|
||||
serial_hw_cfg_4.uart_device = UART4;
|
||||
serial_hw_cfg_4.irq = UART4_IRQn;
|
||||
serial_cfg_4.hw_cfg.private_data = (void *)&serial_hw_cfg_4;
|
||||
serial_driver_4.private_data = (void *)&serial_cfg_4;
|
||||
|
||||
serial_dev_param_4.serial_work_mode = SIGN_OPER_INT_RX;
|
||||
serial_device_4.haldev.private_data = (void *)&serial_dev_param_4;
|
||||
|
||||
NVIC_Configuration(serial_hw_cfg_4.irq);
|
||||
|
||||
ret = BoardSerialBusInit(&serial_4.serial_bus, &serial_driver_4, SERIAL_BUS_NAME_4, SERIAL_DRV_NAME_4);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUsart usart4 error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
ret = BoardSerialDevBend(&serial_device_4, (void *)&serial_cfg_4, SERIAL_BUS_NAME_4, SERIAL_4_DEVICE_NAME_0);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUsart usart4 error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART5
|
||||
static struct SerialCfgParam serial_cfg_5;
|
||||
memset(&serial_cfg_5, 0, sizeof(struct SerialCfgParam));
|
||||
|
||||
static struct UsartHwCfg serial_hw_cfg_5;
|
||||
memset(&serial_hw_cfg_5, 0, sizeof(struct UsartHwCfg));
|
||||
|
||||
static struct SerialDevParam serial_dev_param_5;
|
||||
memset(&serial_dev_param_5, 0, sizeof(struct SerialDevParam));
|
||||
|
||||
serial_5.dma = uart_dma_5;
|
||||
|
||||
serial_driver_5.drv_done = &drv_done;
|
||||
serial_driver_5.configure = &Stm32SerialDrvConfigure;
|
||||
serial_device_5.hwdev_done = &hwdev_done;
|
||||
|
||||
serial_cfg_5.data_cfg = data_cfg_init;
|
||||
|
||||
serial_hw_cfg_5.uart_device = UART5;
|
||||
serial_hw_cfg_5.irq = UART5_IRQn;
|
||||
serial_cfg_5.hw_cfg.private_data = (void *)&serial_hw_cfg_5;
|
||||
serial_driver_5.private_data = (void *)&serial_cfg_5;
|
||||
|
||||
serial_dev_param_5.serial_work_mode = SIGN_OPER_INT_RX;
|
||||
serial_device_5.haldev.private_data = (void *)&serial_dev_param_5;
|
||||
|
||||
NVIC_Configuration(serial_hw_cfg_5.irq);
|
||||
|
||||
ret = BoardSerialBusInit(&serial_5.serial_bus, &serial_driver_5, SERIAL_BUS_NAME_5, SERIAL_DRV_NAME_5);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUsart usart5 error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
ret = BoardSerialDevBend(&serial_device_5, (void *)&serial_cfg_5, SERIAL_BUS_NAME_5, SERIAL_5_DEVICE_NAME_0);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUsart usart5 error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -0,0 +1,858 @@
|
|||
/*
|
||||
* Copyright (c) 2020 RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file connect_usart.c
|
||||
* @brief support stm32f407-st-discovery-board usart function and register to bus framework
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-04-25
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: connect_uart.c
|
||||
Description: support stm32f407-st-discovery-board usart configure and uart bus register function
|
||||
Others: take RT-Thread v4.0.2/bsp/stm32/libraries/HAL_Drivers/drv_usart.c for references
|
||||
https://github.com/RT-Thread/rt-thread/tree/v4.0.2
|
||||
History:
|
||||
1. Date: 2021-04-25
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. support stm32f407-st-discovery-board usart configure, write and read
|
||||
2. support stm32f407-st-discovery-board usart bus device and driver register
|
||||
*************************************************/
|
||||
|
||||
#include "stm32f4xx.h"
|
||||
#include "board.h"
|
||||
#include "misc.h"
|
||||
#include "connect_usart.h"
|
||||
#include "hardware_gpio.h"
|
||||
#include "hardware_rcc.h"
|
||||
|
||||
/* UART GPIO define. */
|
||||
#define UART1_GPIO_TX GPIO_Pin_6
|
||||
#define UART1_TX_PIN_SOURCE GPIO_PinSource6
|
||||
#define UART1_GPIO_RX GPIO_Pin_7
|
||||
#define UART1_RX_PIN_SOURCE GPIO_PinSource7
|
||||
#define UART1_GPIO GPIOB
|
||||
#define UART1_GPIO_RCC RCC_AHB1Periph_GPIOB
|
||||
#define RCC_APBPeriph_UART1 RCC_APB2Periph_USART1
|
||||
|
||||
#define UART2_GPIO_TX GPIO_Pin_2
|
||||
#define UART2_TX_PIN_SOURCE GPIO_PinSource2
|
||||
#define UART2_GPIO_RX GPIO_Pin_3
|
||||
#define UART2_RX_PIN_SOURCE GPIO_PinSource3
|
||||
#define UART2_GPIO GPIOA
|
||||
#define UART2_GPIO_RCC RCC_AHB1Periph_GPIOA
|
||||
#define RCC_APBPeriph_UART2 RCC_APB1Periph_USART2
|
||||
|
||||
#define UART3_GPIO_TX GPIO_Pin_8
|
||||
#define UART3_TX_PIN_SOURCE GPIO_PinSource8
|
||||
#define UART3_GPIO_RX GPIO_Pin_9
|
||||
#define UART3_RX_PIN_SOURCE GPIO_PinSource9
|
||||
#define UART3_GPIO GPIOD
|
||||
#define UART3_GPIO_RCC RCC_AHB1Periph_GPIOD
|
||||
#define RCC_APBPeriph_UART3 RCC_APB1Periph_USART3
|
||||
|
||||
#define UART4_GPIO_TX GPIO_Pin_10
|
||||
#define UART4_TX_PIN_SOURCE GPIO_PinSource10
|
||||
#define UART4_GPIO_RX GPIO_Pin_11
|
||||
#define UART4_RX_PIN_SOURCE GPIO_PinSource11
|
||||
#define UART4_GPIO GPIOC
|
||||
#define UART4_GPIO_RCC RCC_AHB1Periph_GPIOC
|
||||
#define RCC_APBPeriph_UART4 RCC_APB1Periph_UART4
|
||||
|
||||
#define UART5_GPIO_TX GPIO_Pin_12
|
||||
#define UART5_TX_PIN_SOURCE GPIO_PinSource12
|
||||
#define UART5_GPIO_RX GPIO_Pin_2
|
||||
#define UART5_RX_PIN_SOURCE GPIO_PinSource2
|
||||
#define UART5_TX GPIOC
|
||||
#define UART5_RX GPIOD
|
||||
#define UART5_GPIO_RCC_TX RCC_AHB1Periph_GPIOC
|
||||
#define UART5_GPIO_RCC_RX RCC_AHB1Periph_GPIOD
|
||||
#define RCC_APBPeriph_UART5 RCC_APB1Periph_UART5
|
||||
|
||||
#define UART_ENABLE_IRQ(n) NVIC_EnableIRQ((n))
|
||||
#define UART_DISABLE_IRQ(n) NVIC_DisableIRQ((n))
|
||||
|
||||
static void RCCConfiguration(void)
|
||||
{
|
||||
#ifdef BSP_USING_USART1
|
||||
RCC_AHB1PeriphClockCmd(UART1_GPIO_RCC, ENABLE);
|
||||
RCC_APB2PeriphClockCmd(RCC_APBPeriph_UART1, ENABLE);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_USART2
|
||||
RCC_AHB1PeriphClockCmd(UART2_GPIO_RCC, ENABLE);
|
||||
RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART2, ENABLE);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_USART3
|
||||
RCC_AHB1PeriphClockCmd(UART3_GPIO_RCC, ENABLE);
|
||||
RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART3, ENABLE);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART4
|
||||
RCC_AHB1PeriphClockCmd(UART4_GPIO_RCC, ENABLE);
|
||||
RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART4, ENABLE);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART5
|
||||
RCC_AHB1PeriphClockCmd(UART5_GPIO_RCC_TX | UART5_GPIO_RCC_RX, ENABLE);
|
||||
RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART5, ENABLE);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void GPIOConfiguration(void)
|
||||
{
|
||||
GPIO_InitTypeDef gpio_initstructure;
|
||||
|
||||
gpio_initstructure.GPIO_Mode = GPIO_Mode_AF;
|
||||
gpio_initstructure.GPIO_OType = GPIO_OType_PP;
|
||||
gpio_initstructure.GPIO_PuPd = GPIO_PuPd_UP;
|
||||
gpio_initstructure.GPIO_Speed = GPIO_Speed_2MHz;
|
||||
|
||||
#ifdef BSP_USING_USART1
|
||||
gpio_initstructure.GPIO_Pin = UART1_GPIO_RX | UART1_GPIO_TX;
|
||||
GPIO_PinAFConfig(UART1_GPIO, UART1_TX_PIN_SOURCE, GPIO_AF_USART1);
|
||||
GPIO_PinAFConfig(UART1_GPIO, UART1_RX_PIN_SOURCE, GPIO_AF_USART1);
|
||||
|
||||
GPIO_Init(UART1_GPIO, &gpio_initstructure);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_USART2
|
||||
gpio_initstructure.GPIO_Pin = UART2_GPIO_RX | UART2_GPIO_TX;
|
||||
GPIO_PinAFConfig(UART2_GPIO, UART2_TX_PIN_SOURCE, GPIO_AF_USART2);
|
||||
GPIO_PinAFConfig(UART2_GPIO, UART2_RX_PIN_SOURCE, GPIO_AF_USART2);
|
||||
|
||||
GPIO_Init(UART2_GPIO, &gpio_initstructure);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_USART3
|
||||
gpio_initstructure.GPIO_Pin = UART3_GPIO_TX | UART3_GPIO_RX;
|
||||
GPIO_PinAFConfig(UART3_GPIO, UART3_TX_PIN_SOURCE, GPIO_AF_USART3);
|
||||
GPIO_PinAFConfig(UART3_GPIO, UART3_RX_PIN_SOURCE, GPIO_AF_USART3);
|
||||
|
||||
GPIO_Init(UART3_GPIO, &gpio_initstructure);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART4
|
||||
gpio_initstructure.GPIO_Pin = UART4_GPIO_TX | UART4_GPIO_RX;
|
||||
GPIO_PinAFConfig(UART4_GPIO, UART4_TX_PIN_SOURCE, GPIO_AF_UART4);
|
||||
GPIO_PinAFConfig(UART4_GPIO, UART4_RX_PIN_SOURCE, GPIO_AF_UART4);
|
||||
|
||||
GPIO_Init(UART4_GPIO, &gpio_initstructure);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART5
|
||||
gpio_initstructure.GPIO_Pin = UART5_GPIO_TX;
|
||||
GPIO_PinAFConfig(UART5_TX, UART5_TX_PIN_SOURCE, GPIO_AF_UART5);
|
||||
GPIO_Init(UART5_TX, &gpio_initstructure);
|
||||
|
||||
gpio_initstructure.GPIO_Pin = UART5_GPIO_RX;
|
||||
GPIO_PinAFConfig(UART5_RX, UART5_RX_PIN_SOURCE, GPIO_AF_UART5);
|
||||
GPIO_Init(UART5_RX, &gpio_initstructure);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void NVIC_Configuration(IRQn_Type irq)
|
||||
{
|
||||
NVIC_InitTypeDef NVIC_InitStructure;
|
||||
|
||||
NVIC_InitStructure.NVIC_IRQChannel = irq;
|
||||
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
|
||||
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
|
||||
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||
NVIC_Init(&NVIC_InitStructure);
|
||||
}
|
||||
|
||||
static void DmaUartConfig(struct Stm32UsartDma *dma, USART_TypeDef *uart_device, uint32_t SettingRecvLen, void *mem_base_addr)
|
||||
{
|
||||
DMA_InitTypeDef DMA_InitStructure;
|
||||
|
||||
dma->SettingRecvLen = SettingRecvLen;
|
||||
DMA_DeInit(dma->RxStream);
|
||||
while (DMA_GetCmdStatus(dma->RxStream) != DISABLE);
|
||||
DMA_InitStructure.DMA_Channel = dma->RxCh;
|
||||
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t) &(uart_device->DR);
|
||||
DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)mem_base_addr;
|
||||
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory;
|
||||
DMA_InitStructure.DMA_BufferSize = dma->SettingRecvLen;
|
||||
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
|
||||
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
|
||||
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
|
||||
DMA_InitStructure.DMA_MemoryDataSize = DMA_PeripheralDataSize_Byte;
|
||||
DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
|
||||
DMA_InitStructure.DMA_Priority = DMA_Priority_High;
|
||||
DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
|
||||
DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
|
||||
DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
|
||||
DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
|
||||
DMA_Init(dma->RxStream, &DMA_InitStructure);
|
||||
}
|
||||
|
||||
static void DMAConfiguration(struct SerialHardwareDevice *serial_dev, USART_TypeDef *uart_device)
|
||||
{
|
||||
struct Stm32Usart *serial = CONTAINER_OF(serial_dev->haldev.owner_bus, struct Stm32Usart, serial_bus);
|
||||
struct Stm32UsartDma *dma = &serial->dma;
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
|
||||
|
||||
NVIC_InitTypeDef NVIC_InitStructure;
|
||||
|
||||
USART_ITConfig(uart_device, USART_IT_IDLE , ENABLE);
|
||||
|
||||
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);
|
||||
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE);
|
||||
|
||||
DmaUartConfig(dma, uart_device, serial_cfg->data_cfg.serial_buffer_size, serial_dev->serial_fifo.serial_rx->serial_rx_buffer);
|
||||
|
||||
DMA_ClearFlag(dma->RxStream, dma->RxFlag);
|
||||
DMA_ITConfig(dma->RxStream, DMA_IT_TC, ENABLE);
|
||||
USART_DMACmd(uart_device, USART_DMAReq_Rx, ENABLE);
|
||||
DMA_Cmd(dma->RxStream, ENABLE);
|
||||
|
||||
NVIC_InitStructure.NVIC_IRQChannel = dma->RxIrqCh;
|
||||
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
|
||||
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
|
||||
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||
NVIC_Init(&NVIC_InitStructure);
|
||||
}
|
||||
|
||||
static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struct SerialCfgParam *serial_cfg_new)
|
||||
{
|
||||
struct SerialDataCfg *data_cfg_default = &serial_cfg_default->data_cfg;
|
||||
struct SerialDataCfg *data_cfg_new = &serial_cfg_new->data_cfg;
|
||||
|
||||
if((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) {
|
||||
data_cfg_default->serial_baud_rate = data_cfg_new->serial_baud_rate;
|
||||
}
|
||||
|
||||
if((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order)) {
|
||||
data_cfg_default->serial_bit_order = data_cfg_new->serial_bit_order;
|
||||
}
|
||||
|
||||
if((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)) {
|
||||
data_cfg_default->serial_buffer_size = data_cfg_new->serial_buffer_size;
|
||||
}
|
||||
|
||||
if((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits)) {
|
||||
data_cfg_default->serial_data_bits = data_cfg_new->serial_data_bits;
|
||||
}
|
||||
|
||||
if((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode)) {
|
||||
data_cfg_default->serial_invert_mode = data_cfg_new->serial_invert_mode;
|
||||
}
|
||||
|
||||
if((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)) {
|
||||
data_cfg_default->serial_parity_mode = data_cfg_new->serial_parity_mode;
|
||||
}
|
||||
|
||||
if((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
|
||||
data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
|
||||
}
|
||||
}
|
||||
|
||||
static uint32 Stm32SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info)
|
||||
{
|
||||
NULL_PARAM_CHECK(serial_drv);
|
||||
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
|
||||
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
|
||||
|
||||
if (configure_info->private_data) {
|
||||
struct SerialCfgParam *serial_cfg_new = (struct SerialCfgParam *)configure_info->private_data;
|
||||
SerialCfgParamCheck(serial_cfg, serial_cfg_new);
|
||||
}
|
||||
|
||||
USART_InitTypeDef USART_InitStructure;
|
||||
|
||||
USART_InitStructure.USART_BaudRate = serial_cfg->data_cfg.serial_baud_rate;
|
||||
|
||||
if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_8) {
|
||||
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
|
||||
} else if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_9) {
|
||||
USART_InitStructure.USART_WordLength = USART_WordLength_9b;
|
||||
}
|
||||
|
||||
if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_1){
|
||||
USART_InitStructure.USART_StopBits = USART_StopBits_1;
|
||||
} else if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_2) {
|
||||
USART_InitStructure.USART_StopBits = USART_StopBits_2;
|
||||
}
|
||||
|
||||
if (serial_cfg->data_cfg.serial_parity_mode == PARITY_NONE) {
|
||||
USART_InitStructure.USART_Parity = USART_Parity_No;
|
||||
} else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_ODD) {
|
||||
USART_InitStructure.USART_Parity = USART_Parity_Odd;
|
||||
} else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_EVEN) {
|
||||
USART_InitStructure.USART_Parity = USART_Parity_Even;
|
||||
}
|
||||
|
||||
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
||||
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
|
||||
USART_Init(serial_hw_cfg->uart_device, &USART_InitStructure);
|
||||
|
||||
USART_Cmd(serial_hw_cfg->uart_device, ENABLE);
|
||||
|
||||
return EOK;
|
||||
}
|
||||
|
||||
static uint32 Stm32SerialConfigure(struct SerialDriver *serial_drv, int serial_operation_cmd)
|
||||
{
|
||||
NULL_PARAM_CHECK(serial_drv);
|
||||
|
||||
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
|
||||
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
|
||||
struct SerialDevParam *serial_dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
|
||||
|
||||
switch (serial_operation_cmd)
|
||||
{
|
||||
case OPER_CLR_INT:
|
||||
UART_DISABLE_IRQ(serial_hw_cfg->irq);
|
||||
USART_ITConfig(serial_hw_cfg->uart_device, USART_IT_RXNE, DISABLE);
|
||||
break;
|
||||
case OPER_SET_INT:
|
||||
UART_ENABLE_IRQ(serial_hw_cfg->irq);
|
||||
USART_ITConfig(serial_hw_cfg->uart_device, USART_IT_RXNE, ENABLE);
|
||||
break;
|
||||
case OPER_CONFIG :
|
||||
if (SIGN_OPER_DMA_RX == serial_dev_param->serial_set_mode){
|
||||
DMAConfiguration(serial_dev, serial_hw_cfg->uart_device);
|
||||
}
|
||||
}
|
||||
|
||||
return EOK;
|
||||
}
|
||||
|
||||
static int Stm32SerialPutchar(struct SerialHardwareDevice *serial_dev, char c)
|
||||
{
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
|
||||
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
|
||||
|
||||
while (!(serial_hw_cfg->uart_device->SR & USART_FLAG_TXE));
|
||||
serial_hw_cfg->uart_device->DR = c;
|
||||
|
||||
return EOK;
|
||||
}
|
||||
|
||||
static int Stm32SerialGetchar(struct SerialHardwareDevice *serial_dev)
|
||||
{
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
|
||||
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
|
||||
|
||||
int ch = -1;
|
||||
if (serial_hw_cfg->uart_device->SR & USART_FLAG_RXNE) {
|
||||
ch = serial_hw_cfg->uart_device->DR & 0xff;
|
||||
}
|
||||
|
||||
return ch;
|
||||
}
|
||||
|
||||
static void DmaUartRxIdleIsr(struct SerialHardwareDevice *serial_dev, struct Stm32UsartDma *dma, USART_TypeDef *uart_device)
|
||||
{
|
||||
x_base level = CriticalAreaLock();
|
||||
|
||||
x_size_t recv_total_index = dma->SettingRecvLen - DMA_GetCurrDataCounter(dma->RxStream);
|
||||
x_size_t recv_len = recv_total_index - dma->LastRecvIndex;
|
||||
dma->LastRecvIndex = recv_total_index;
|
||||
CriticalAreaUnLock(level);
|
||||
|
||||
if (recv_len) SerialSetIsr(serial_dev, SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
|
||||
|
||||
USART_ReceiveData(uart_device);
|
||||
}
|
||||
|
||||
static void DmaRxDoneIsr(struct Stm32Usart *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev)
|
||||
{
|
||||
struct Stm32UsartDma *dma = &serial->dma;
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
|
||||
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
|
||||
|
||||
if (DMA_GetFlagStatus(dma->RxStream, dma->RxFlag) != RESET) {
|
||||
x_base level = CriticalAreaLock();
|
||||
|
||||
x_size_t recv_len = dma->SettingRecvLen - dma->LastRecvIndex;
|
||||
dma->LastRecvIndex = 0;
|
||||
CriticalAreaUnLock(level);
|
||||
|
||||
if (recv_len) SerialSetIsr(serial_dev, SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
|
||||
|
||||
DMA_ClearFlag(dma->RxStream, dma->RxFlag);
|
||||
}
|
||||
}
|
||||
|
||||
static void UartIsr(struct Stm32Usart *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev)
|
||||
{
|
||||
struct Stm32UsartDma *dma = &serial->dma;
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
|
||||
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
|
||||
|
||||
if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_RXNE) != RESET) {
|
||||
SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND);
|
||||
USART_ClearITPendingBit(serial_hw_cfg->uart_device, USART_IT_RXNE);
|
||||
}
|
||||
if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_IDLE) != RESET) {
|
||||
DmaUartRxIdleIsr(serial_dev, dma, serial_hw_cfg->uart_device);
|
||||
}
|
||||
if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_TC) != RESET) {
|
||||
USART_ClearITPendingBit(serial_hw_cfg->uart_device, USART_IT_TC);
|
||||
}
|
||||
if (USART_GetFlagStatus(serial_hw_cfg->uart_device, USART_FLAG_ORE) == SET) {
|
||||
USART_ReceiveData(serial_hw_cfg->uart_device);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef BSP_USING_USART1
|
||||
struct Stm32Usart serial_1;
|
||||
struct SerialDriver serial_driver_1;
|
||||
struct SerialHardwareDevice serial_device_1;
|
||||
|
||||
static const struct Stm32UsartDma usart_dma_1 =
|
||||
{
|
||||
DMA2_Stream5,
|
||||
DMA_Channel_4,
|
||||
DMA_FLAG_TCIF5,
|
||||
DMA2_Stream5_IRQn,
|
||||
0,
|
||||
0,
|
||||
};
|
||||
|
||||
void USART1_IRQHandler(int irq_num, void *arg)
|
||||
{
|
||||
UartIsr(&serial_1, &serial_driver_1, &serial_device_1);
|
||||
}
|
||||
DECLARE_HW_IRQ(USART1_IRQn, USART1_IRQHandler, NONE);
|
||||
|
||||
void DMA2_Stream5_IRQHandler(int irq_num, void *arg) {
|
||||
DmaRxDoneIsr(&serial_1, &serial_driver_1, &serial_device_1);
|
||||
}
|
||||
DECLARE_HW_IRQ(DMA2_Stream5_IRQn, DMA2_Stream5_IRQHandler, NONE);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_USART2
|
||||
struct Stm32Usart serial_2;
|
||||
struct SerialDriver serial_driver_2;
|
||||
struct SerialHardwareDevice serial_device_2;
|
||||
|
||||
static const struct Stm32UsartDma usart_dma_2 =
|
||||
{
|
||||
DMA1_Stream5,
|
||||
DMA_Channel_4,
|
||||
DMA_FLAG_TCIF5,
|
||||
DMA1_Stream5_IRQn,
|
||||
0,
|
||||
0,
|
||||
};
|
||||
|
||||
void USART2_IRQHandler(int irq_num, void *arg)
|
||||
{
|
||||
UartIsr(&serial_2, &serial_driver_2, &serial_device_2);
|
||||
}
|
||||
DECLARE_HW_IRQ(USART2_IRQn, USART2_IRQHandler, NONE);
|
||||
|
||||
void DMA1_Stream5_IRQHandler(int irq_num, void *arg) {
|
||||
DmaRxDoneIsr(&serial_2, &serial_driver_2, &serial_device_2);
|
||||
}
|
||||
DECLARE_HW_IRQ(DMA1_Stream5_IRQn, DMA1_Stream5_IRQHandler, NONE);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_USART3
|
||||
struct Stm32Usart serial_3;
|
||||
struct SerialDriver serial_driver_3;
|
||||
struct SerialHardwareDevice serial_device_3;
|
||||
|
||||
static const struct Stm32UsartDma usart_dma_3 =
|
||||
{
|
||||
DMA1_Stream1,
|
||||
DMA_Channel_4,
|
||||
DMA_FLAG_TCIF1,
|
||||
DMA1_Stream1_IRQn,
|
||||
0,
|
||||
0,
|
||||
};
|
||||
|
||||
void USART3_IRQHandler(int irq_num, void *arg)
|
||||
{
|
||||
UartIsr(&serial_3, &serial_driver_3, &serial_device_3);
|
||||
}
|
||||
DECLARE_HW_IRQ(USART3_IRQn, USART3_IRQHandler, NONE);
|
||||
|
||||
void DMA1_Stream1_IRQHandler(int irq_num, void *arg) {
|
||||
DmaRxDoneIsr(&serial_3, &serial_driver_3, &serial_device_3);
|
||||
}
|
||||
DECLARE_HW_IRQ(DMA1_Stream1_IRQn, DMA1_Stream1_IRQHandler, NONE);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART4
|
||||
struct Stm32Usart serial_4;
|
||||
struct SerialDriver serial_driver_4;
|
||||
struct SerialHardwareDevice serial_device_4;
|
||||
|
||||
static const struct Stm32UsartDma uart_dma_4 =
|
||||
{
|
||||
DMA1_Stream2,
|
||||
DMA_Channel_4,
|
||||
DMA_FLAG_TCIF2,
|
||||
DMA1_Stream2_IRQn,
|
||||
0,
|
||||
0,
|
||||
};
|
||||
|
||||
void UART4_IRQHandler(int irq_num, void *arg)
|
||||
{
|
||||
UartIsr(&serial_4, &serial_driver_4, &serial_device_4);
|
||||
}
|
||||
DECLARE_HW_IRQ(UART4_IRQn, UART4_IRQHandler, NONE);
|
||||
|
||||
void DMA1_Stream2_IRQHandler(int irq_num, void *arg) {
|
||||
DmaRxDoneIsr(&serial_4, &serial_driver_4, &serial_device_4);
|
||||
}
|
||||
DECLARE_HW_IRQ(DMA1_Stream2_IRQn, DMA1_Stream2_IRQHandler, NONE);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART5
|
||||
struct Stm32Usart serial_5;
|
||||
struct SerialDriver serial_driver_5;
|
||||
struct SerialHardwareDevice serial_device_5;
|
||||
|
||||
static const struct Stm32UsartDma uart_dma_5 =
|
||||
{
|
||||
DMA1_Stream0,
|
||||
DMA_Channel_4,
|
||||
DMA_FLAG_TCIF0,
|
||||
DMA1_Stream0_IRQn,
|
||||
0,
|
||||
0,
|
||||
};
|
||||
|
||||
void UART5_IRQHandler(int irq_num, void *arg)
|
||||
{
|
||||
UartIsr(&serial_5, &serial_driver_5, &serial_device_5);
|
||||
}
|
||||
DECLARE_HW_IRQ(UART5_IRQn, UART5_IRQHandler, NONE);
|
||||
|
||||
void DMA1_Stream0_IRQHandler(int irq_num, void *arg) {
|
||||
DmaRxDoneIsr(&serial_5, &serial_driver_5, &serial_device_5);
|
||||
}
|
||||
DECLARE_HW_IRQ(DMA1_Stream0_IRQn, DMA1_Stream0_IRQHandler, NONE);
|
||||
#endif
|
||||
|
||||
static uint32 Stm32SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
|
||||
{
|
||||
NULL_PARAM_CHECK(drv);
|
||||
NULL_PARAM_CHECK(configure_info);
|
||||
|
||||
x_err_t ret = EOK;
|
||||
int serial_operation_cmd;
|
||||
struct SerialDriver *serial_drv = (struct SerialDriver *)drv;
|
||||
|
||||
switch (configure_info->configure_cmd)
|
||||
{
|
||||
case OPE_INT:
|
||||
ret = Stm32SerialInit(serial_drv, configure_info);
|
||||
break;
|
||||
case OPE_CFG:
|
||||
serial_operation_cmd = *(int *)configure_info->private_data;
|
||||
ret = Stm32SerialConfigure(serial_drv, serial_operation_cmd);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct SerialDataCfg data_cfg_init =
|
||||
{
|
||||
.serial_baud_rate = BAUD_RATE_115200,
|
||||
.serial_data_bits = DATA_BITS_8,
|
||||
.serial_stop_bits = STOP_BITS_1,
|
||||
.serial_parity_mode = PARITY_NONE,
|
||||
.serial_bit_order = BIT_ORDER_LSB,
|
||||
.serial_invert_mode = NRZ_NORMAL,
|
||||
.serial_buffer_size = SERIAL_RB_BUFSZ,
|
||||
};
|
||||
|
||||
/*manage the serial device operations*/
|
||||
static const struct SerialDrvDone drv_done =
|
||||
{
|
||||
.init = Stm32SerialInit,
|
||||
.configure = Stm32SerialConfigure,
|
||||
};
|
||||
|
||||
/*manage the serial device hal operations*/
|
||||
static struct SerialHwDevDone hwdev_done =
|
||||
{
|
||||
.put_char = Stm32SerialPutchar,
|
||||
.get_char = Stm32SerialGetchar,
|
||||
};
|
||||
|
||||
static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver *serial_driver, const char *bus_name, const char *drv_name)
|
||||
{
|
||||
x_err_t ret = EOK;
|
||||
|
||||
/*Init the serial bus */
|
||||
ret = SerialBusInit(serial_bus, bus_name);
|
||||
if (EOK != ret) {
|
||||
KPrintf("hw_serial_init SerialBusInit error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
/*Init the serial driver*/
|
||||
ret = SerialDriverInit(serial_driver, drv_name);
|
||||
if (EOK != ret) {
|
||||
KPrintf("hw_serial_init SerialDriverInit error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
/*Attach the serial driver to the serial bus*/
|
||||
ret = SerialDriverAttachToBus(drv_name, bus_name);
|
||||
if (EOK != ret) {
|
||||
KPrintf("hw_serial_init SerialDriverAttachToBus error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*Attach the serial device to the serial bus*/
|
||||
static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *serial_param, const char *bus_name, const char *dev_name)
|
||||
{
|
||||
x_err_t ret = EOK;
|
||||
|
||||
ret = SerialDeviceRegister(serial_device, serial_param, dev_name);
|
||||
if (EOK != ret) {
|
||||
KPrintf("hw_serial_init SerialDeviceInit device %s error %d\n", dev_name, ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
ret = SerialDeviceAttachToBus(dev_name, bus_name);
|
||||
if (EOK != ret) {
|
||||
KPrintf("hw_serial_init SerialDeviceAttachToBus device %s error %d\n", dev_name, ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int InitHwUsart(void)
|
||||
{
|
||||
x_err_t ret = EOK;
|
||||
|
||||
RCCConfiguration();
|
||||
GPIOConfiguration();
|
||||
|
||||
#ifdef BSP_USING_USART1
|
||||
static struct SerialCfgParam serial_cfg_1;
|
||||
memset(&serial_cfg_1, 0, sizeof(struct SerialCfgParam));
|
||||
|
||||
static struct UsartHwCfg serial_hw_cfg_1;
|
||||
memset(&serial_hw_cfg_1, 0, sizeof(struct UsartHwCfg));
|
||||
|
||||
static struct SerialDevParam serial_dev_param_1;
|
||||
memset(&serial_dev_param_1, 0, sizeof(struct SerialDevParam));
|
||||
|
||||
serial_1.dma = usart_dma_1;
|
||||
|
||||
serial_driver_1.drv_done = &drv_done;
|
||||
serial_driver_1.configure = &Stm32SerialDrvConfigure;
|
||||
serial_device_1.hwdev_done = &hwdev_done;
|
||||
|
||||
serial_cfg_1.data_cfg = data_cfg_init;
|
||||
|
||||
serial_hw_cfg_1.uart_device = USART1;
|
||||
serial_hw_cfg_1.irq = USART1_IRQn;
|
||||
serial_cfg_1.hw_cfg.private_data = (void *)&serial_hw_cfg_1;
|
||||
serial_driver_1.private_data = (void *)&serial_cfg_1;
|
||||
|
||||
serial_dev_param_1.serial_work_mode = SIGN_OPER_INT_RX;
|
||||
serial_device_1.haldev.private_data = (void *)&serial_dev_param_1;
|
||||
|
||||
NVIC_Configuration(serial_hw_cfg_1.irq);
|
||||
|
||||
ret = BoardSerialBusInit(&serial_1.serial_bus, &serial_driver_1, SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUsart usart1 error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
ret = BoardSerialDevBend(&serial_device_1, (void *)&serial_cfg_1, SERIAL_BUS_NAME_1, SERIAL_1_DEVICE_NAME_0);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUsart usart1 error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_USART2
|
||||
static struct SerialCfgParam serial_cfg_2;
|
||||
memset(&serial_cfg_2, 0, sizeof(struct SerialCfgParam));
|
||||
|
||||
static struct UsartHwCfg serial_hw_cfg_2;
|
||||
memset(&serial_hw_cfg_2, 0, sizeof(struct UsartHwCfg));
|
||||
|
||||
static struct SerialDevParam serial_dev_param_2;
|
||||
memset(&serial_dev_param_2, 0, sizeof(struct SerialDevParam));
|
||||
|
||||
serial_2.dma = usart_dma_2;
|
||||
|
||||
serial_driver_2.drv_done = &drv_done;
|
||||
serial_driver_2.configure = &Stm32SerialDrvConfigure;
|
||||
serial_device_2.hwdev_done = &hwdev_done;
|
||||
|
||||
serial_cfg_2.data_cfg = data_cfg_init;
|
||||
|
||||
serial_hw_cfg_2.uart_device = USART2;
|
||||
serial_hw_cfg_2.irq = USART2_IRQn;
|
||||
serial_cfg_2.hw_cfg.private_data = (void *)&serial_hw_cfg_2;
|
||||
serial_driver_2.private_data = (void *)&serial_cfg_2;
|
||||
|
||||
serial_dev_param_2.serial_work_mode = SIGN_OPER_INT_RX;
|
||||
serial_device_2.haldev.private_data = (void *)&serial_dev_param_2;
|
||||
|
||||
NVIC_Configuration(serial_hw_cfg_2.irq);
|
||||
|
||||
ret = BoardSerialBusInit(&serial_2.serial_bus, &serial_driver_2, SERIAL_BUS_NAME_2, SERIAL_DRV_NAME_2);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUsart usart2 error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
ret = BoardSerialDevBend(&serial_device_2, (void *)&serial_cfg_2, SERIAL_BUS_NAME_2, SERIAL_2_DEVICE_NAME_0);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUsart usart2 error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_USART3
|
||||
static struct SerialCfgParam serial_cfg_3;
|
||||
memset(&serial_cfg_3, 0, sizeof(struct SerialCfgParam));
|
||||
|
||||
static struct UsartHwCfg serial_hw_cfg_3;
|
||||
memset(&serial_hw_cfg_3, 0, sizeof(struct UsartHwCfg));
|
||||
|
||||
static struct SerialDevParam serial_dev_param_3;
|
||||
memset(&serial_dev_param_3, 0, sizeof(struct SerialDevParam));
|
||||
|
||||
serial_3.dma = usart_dma_3;
|
||||
|
||||
serial_driver_3.drv_done = &drv_done;
|
||||
serial_driver_3.configure = &Stm32SerialDrvConfigure;
|
||||
serial_device_3.hwdev_done = &hwdev_done;
|
||||
|
||||
serial_cfg_3.data_cfg = data_cfg_init;
|
||||
|
||||
serial_hw_cfg_3.uart_device = USART3;
|
||||
serial_hw_cfg_3.irq = USART3_IRQn;
|
||||
serial_cfg_3.hw_cfg.private_data = (void *)&serial_hw_cfg_3;
|
||||
serial_driver_3.private_data = (void *)&serial_cfg_3;
|
||||
|
||||
serial_dev_param_3.serial_work_mode = SIGN_OPER_INT_RX;
|
||||
serial_device_3.haldev.private_data = (void *)&serial_dev_param_3;
|
||||
|
||||
NVIC_Configuration(serial_hw_cfg_3.irq);
|
||||
|
||||
ret = BoardSerialBusInit(&serial_3.serial_bus, &serial_driver_3, SERIAL_BUS_NAME_3, SERIAL_DRV_NAME_3);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUsart usart3 error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
ret = BoardSerialDevBend(&serial_device_3, (void *)&serial_cfg_3, SERIAL_BUS_NAME_3, SERIAL_3_DEVICE_NAME_0);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUsart usart3 error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART4
|
||||
static struct SerialCfgParam serial_cfg_4;
|
||||
memset(&serial_cfg_4, 0, sizeof(struct SerialCfgParam));
|
||||
|
||||
static struct UsartHwCfg serial_hw_cfg_4;
|
||||
memset(&serial_hw_cfg_4, 0, sizeof(struct UsartHwCfg));
|
||||
|
||||
static struct SerialDevParam serial_dev_param_4;
|
||||
memset(&serial_dev_param_4, 0, sizeof(struct SerialDevParam));
|
||||
|
||||
serial_4.dma = uart_dma_4;
|
||||
|
||||
serial_driver_4.drv_done = &drv_done;
|
||||
serial_driver_4.configure = &Stm32SerialDrvConfigure;
|
||||
serial_device_4.hwdev_done = &hwdev_done;
|
||||
|
||||
serial_cfg_4.data_cfg = data_cfg_init;
|
||||
|
||||
serial_hw_cfg_4.uart_device = UART4;
|
||||
serial_hw_cfg_4.irq = UART4_IRQn;
|
||||
serial_cfg_4.hw_cfg.private_data = (void *)&serial_hw_cfg_4;
|
||||
serial_driver_4.private_data = (void *)&serial_cfg_4;
|
||||
|
||||
serial_dev_param_4.serial_work_mode = SIGN_OPER_INT_RX;
|
||||
serial_device_4.haldev.private_data = (void *)&serial_dev_param_4;
|
||||
|
||||
NVIC_Configuration(serial_hw_cfg_4.irq);
|
||||
|
||||
ret = BoardSerialBusInit(&serial_4.serial_bus, &serial_driver_4, SERIAL_BUS_NAME_4, SERIAL_DRV_NAME_4);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUsart usart4 error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
ret = BoardSerialDevBend(&serial_device_4, (void *)&serial_cfg_4, SERIAL_BUS_NAME_4, SERIAL_4_DEVICE_NAME_0);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUsart usart4 error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART5
|
||||
static struct SerialCfgParam serial_cfg_5;
|
||||
memset(&serial_cfg_5, 0, sizeof(struct SerialCfgParam));
|
||||
|
||||
static struct UsartHwCfg serial_hw_cfg_5;
|
||||
memset(&serial_hw_cfg_5, 0, sizeof(struct UsartHwCfg));
|
||||
|
||||
static struct SerialDevParam serial_dev_param_5;
|
||||
memset(&serial_dev_param_5, 0, sizeof(struct SerialDevParam));
|
||||
|
||||
serial_5.dma = uart_dma_5;
|
||||
|
||||
serial_driver_5.drv_done = &drv_done;
|
||||
serial_driver_5.configure = &Stm32SerialDrvConfigure;
|
||||
serial_device_5.hwdev_done = &hwdev_done;
|
||||
|
||||
serial_cfg_5.data_cfg = data_cfg_init;
|
||||
|
||||
serial_hw_cfg_5.uart_device = UART5;
|
||||
serial_hw_cfg_5.irq = UART5_IRQn;
|
||||
serial_cfg_5.hw_cfg.private_data = (void *)&serial_hw_cfg_5;
|
||||
serial_driver_5.private_data = (void *)&serial_cfg_5;
|
||||
|
||||
serial_dev_param_5.serial_work_mode = SIGN_OPER_INT_RX;
|
||||
serial_device_5.haldev.private_data = (void *)&serial_dev_param_5;
|
||||
|
||||
NVIC_Configuration(serial_hw_cfg_5.irq);
|
||||
|
||||
ret = BoardSerialBusInit(&serial_5.serial_bus, &serial_driver_5, SERIAL_BUS_NAME_5, SERIAL_DRV_NAME_5);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUsart usart5 error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
ret = BoardSerialDevBend(&serial_device_5, (void *)&serial_cfg_5, SERIAL_BUS_NAME_5, SERIAL_5_DEVICE_NAME_0);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUsart usart5 error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -0,0 +1,858 @@
|
|||
/*
|
||||
* Copyright (c) 2020 RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file connect_usart.c
|
||||
* @brief support stm32f407-st-discovery-board usart function and register to bus framework
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-04-25
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: connect_uart.c
|
||||
Description: support stm32f407-st-discovery-board usart configure and uart bus register function
|
||||
Others: take RT-Thread v4.0.2/bsp/stm32/libraries/HAL_Drivers/drv_usart.c for references
|
||||
https://github.com/RT-Thread/rt-thread/tree/v4.0.2
|
||||
History:
|
||||
1. Date: 2021-04-25
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. support stm32f407-st-discovery-board usart configure, write and read
|
||||
2. support stm32f407-st-discovery-board usart bus device and driver register
|
||||
*************************************************/
|
||||
|
||||
#include "stm32f4xx.h"
|
||||
#include "board.h"
|
||||
#include "misc.h"
|
||||
#include "connect_usart.h"
|
||||
#include "hardware_gpio.h"
|
||||
#include "hardware_rcc.h"
|
||||
|
||||
/* UART GPIO define. */
|
||||
#define UART1_GPIO_TX GPIO_Pin_6
|
||||
#define UART1_TX_PIN_SOURCE GPIO_PinSource6
|
||||
#define UART1_GPIO_RX GPIO_Pin_7
|
||||
#define UART1_RX_PIN_SOURCE GPIO_PinSource7
|
||||
#define UART1_GPIO GPIOB
|
||||
#define UART1_GPIO_RCC RCC_AHB1Periph_GPIOB
|
||||
#define RCC_APBPeriph_UART1 RCC_APB2Periph_USART1
|
||||
|
||||
#define UART2_GPIO_TX GPIO_Pin_2
|
||||
#define UART2_TX_PIN_SOURCE GPIO_PinSource2
|
||||
#define UART2_GPIO_RX GPIO_Pin_3
|
||||
#define UART2_RX_PIN_SOURCE GPIO_PinSource3
|
||||
#define UART2_GPIO GPIOA
|
||||
#define UART2_GPIO_RCC RCC_AHB1Periph_GPIOA
|
||||
#define RCC_APBPeriph_UART2 RCC_APB1Periph_USART2
|
||||
|
||||
#define UART3_GPIO_TX GPIO_Pin_8
|
||||
#define UART3_TX_PIN_SOURCE GPIO_PinSource8
|
||||
#define UART3_GPIO_RX GPIO_Pin_9
|
||||
#define UART3_RX_PIN_SOURCE GPIO_PinSource9
|
||||
#define UART3_GPIO GPIOD
|
||||
#define UART3_GPIO_RCC RCC_AHB1Periph_GPIOD
|
||||
#define RCC_APBPeriph_UART3 RCC_APB1Periph_USART3
|
||||
|
||||
#define UART4_GPIO_TX GPIO_Pin_10
|
||||
#define UART4_TX_PIN_SOURCE GPIO_PinSource10
|
||||
#define UART4_GPIO_RX GPIO_Pin_11
|
||||
#define UART4_RX_PIN_SOURCE GPIO_PinSource11
|
||||
#define UART4_GPIO GPIOC
|
||||
#define UART4_GPIO_RCC RCC_AHB1Periph_GPIOC
|
||||
#define RCC_APBPeriph_UART4 RCC_APB1Periph_UART4
|
||||
|
||||
#define UART5_GPIO_TX GPIO_Pin_12
|
||||
#define UART5_TX_PIN_SOURCE GPIO_PinSource12
|
||||
#define UART5_GPIO_RX GPIO_Pin_2
|
||||
#define UART5_RX_PIN_SOURCE GPIO_PinSource2
|
||||
#define UART5_TX GPIOC
|
||||
#define UART5_RX GPIOD
|
||||
#define UART5_GPIO_RCC_TX RCC_AHB1Periph_GPIOC
|
||||
#define UART5_GPIO_RCC_RX RCC_AHB1Periph_GPIOD
|
||||
#define RCC_APBPeriph_UART5 RCC_APB1Periph_UART5
|
||||
|
||||
#define UART_ENABLE_IRQ(n) NVIC_EnableIRQ((n))
|
||||
#define UART_DISABLE_IRQ(n) NVIC_DisableIRQ((n))
|
||||
|
||||
static void RCCConfiguration(void)
|
||||
{
|
||||
#ifdef BSP_USING_USART1
|
||||
RCC_AHB1PeriphClockCmd(UART1_GPIO_RCC, ENABLE);
|
||||
RCC_APB2PeriphClockCmd(RCC_APBPeriph_UART1, ENABLE);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_USART2
|
||||
RCC_AHB1PeriphClockCmd(UART2_GPIO_RCC, ENABLE);
|
||||
RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART2, ENABLE);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_USART3
|
||||
RCC_AHB1PeriphClockCmd(UART3_GPIO_RCC, ENABLE);
|
||||
RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART3, ENABLE);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART4
|
||||
RCC_AHB1PeriphClockCmd(UART4_GPIO_RCC, ENABLE);
|
||||
RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART4, ENABLE);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART5
|
||||
RCC_AHB1PeriphClockCmd(UART5_GPIO_RCC_TX | UART5_GPIO_RCC_RX, ENABLE);
|
||||
RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART5, ENABLE);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void GPIOConfiguration(void)
|
||||
{
|
||||
GPIO_InitTypeDef gpio_initstructure;
|
||||
|
||||
gpio_initstructure.GPIO_Mode = GPIO_Mode_AF;
|
||||
gpio_initstructure.GPIO_OType = GPIO_OType_PP;
|
||||
gpio_initstructure.GPIO_PuPd = GPIO_PuPd_UP;
|
||||
gpio_initstructure.GPIO_Speed = GPIO_Speed_2MHz;
|
||||
|
||||
#ifdef BSP_USING_USART1
|
||||
gpio_initstructure.GPIO_Pin = UART1_GPIO_RX | UART1_GPIO_TX;
|
||||
GPIO_PinAFConfig(UART1_GPIO, UART1_TX_PIN_SOURCE, GPIO_AF_USART1);
|
||||
GPIO_PinAFConfig(UART1_GPIO, UART1_RX_PIN_SOURCE, GPIO_AF_USART1);
|
||||
|
||||
GPIO_Init(UART1_GPIO, &gpio_initstructure);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_USART2
|
||||
gpio_initstructure.GPIO_Pin = UART2_GPIO_RX | UART2_GPIO_TX;
|
||||
GPIO_PinAFConfig(UART2_GPIO, UART2_TX_PIN_SOURCE, GPIO_AF_USART2);
|
||||
GPIO_PinAFConfig(UART2_GPIO, UART2_RX_PIN_SOURCE, GPIO_AF_USART2);
|
||||
|
||||
GPIO_Init(UART2_GPIO, &gpio_initstructure);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_USART3
|
||||
gpio_initstructure.GPIO_Pin = UART3_GPIO_TX | UART3_GPIO_RX;
|
||||
GPIO_PinAFConfig(UART3_GPIO, UART3_TX_PIN_SOURCE, GPIO_AF_USART3);
|
||||
GPIO_PinAFConfig(UART3_GPIO, UART3_RX_PIN_SOURCE, GPIO_AF_USART3);
|
||||
|
||||
GPIO_Init(UART3_GPIO, &gpio_initstructure);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART4
|
||||
gpio_initstructure.GPIO_Pin = UART4_GPIO_TX | UART4_GPIO_RX;
|
||||
GPIO_PinAFConfig(UART4_GPIO, UART4_TX_PIN_SOURCE, GPIO_AF_UART4);
|
||||
GPIO_PinAFConfig(UART4_GPIO, UART4_RX_PIN_SOURCE, GPIO_AF_UART4);
|
||||
|
||||
GPIO_Init(UART4_GPIO, &gpio_initstructure);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART5
|
||||
gpio_initstructure.GPIO_Pin = UART5_GPIO_TX;
|
||||
GPIO_PinAFConfig(UART5_TX, UART5_TX_PIN_SOURCE, GPIO_AF_UART5);
|
||||
GPIO_Init(UART5_TX, &gpio_initstructure);
|
||||
|
||||
gpio_initstructure.GPIO_Pin = UART5_GPIO_RX;
|
||||
GPIO_PinAFConfig(UART5_RX, UART5_RX_PIN_SOURCE, GPIO_AF_UART5);
|
||||
GPIO_Init(UART5_RX, &gpio_initstructure);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void NVIC_Configuration(IRQn_Type irq)
|
||||
{
|
||||
NVIC_InitTypeDef NVIC_InitStructure;
|
||||
|
||||
NVIC_InitStructure.NVIC_IRQChannel = irq;
|
||||
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
|
||||
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
|
||||
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||
NVIC_Init(&NVIC_InitStructure);
|
||||
}
|
||||
|
||||
static void DmaUartConfig(struct Stm32UsartDma *dma, USART_TypeDef *uart_device, uint32_t SettingRecvLen, void *mem_base_addr)
|
||||
{
|
||||
DMA_InitTypeDef DMA_InitStructure;
|
||||
|
||||
dma->SettingRecvLen = SettingRecvLen;
|
||||
DMA_DeInit(dma->RxStream);
|
||||
while (DMA_GetCmdStatus(dma->RxStream) != DISABLE);
|
||||
DMA_InitStructure.DMA_Channel = dma->RxCh;
|
||||
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t) &(uart_device->DR);
|
||||
DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)mem_base_addr;
|
||||
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory;
|
||||
DMA_InitStructure.DMA_BufferSize = dma->SettingRecvLen;
|
||||
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
|
||||
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
|
||||
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
|
||||
DMA_InitStructure.DMA_MemoryDataSize = DMA_PeripheralDataSize_Byte;
|
||||
DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
|
||||
DMA_InitStructure.DMA_Priority = DMA_Priority_High;
|
||||
DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
|
||||
DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
|
||||
DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
|
||||
DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
|
||||
DMA_Init(dma->RxStream, &DMA_InitStructure);
|
||||
}
|
||||
|
||||
static void DMAConfiguration(struct SerialHardwareDevice *serial_dev, USART_TypeDef *uart_device)
|
||||
{
|
||||
struct Stm32Usart *serial = CONTAINER_OF(serial_dev->haldev.owner_bus, struct Stm32Usart, serial_bus);
|
||||
struct Stm32UsartDma *dma = &serial->dma;
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
|
||||
|
||||
NVIC_InitTypeDef NVIC_InitStructure;
|
||||
|
||||
USART_ITConfig(uart_device, USART_IT_IDLE , ENABLE);
|
||||
|
||||
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);
|
||||
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE);
|
||||
|
||||
DmaUartConfig(dma, uart_device, serial_cfg->data_cfg.serial_buffer_size, serial_dev->serial_fifo.serial_rx->serial_rx_buffer);
|
||||
|
||||
DMA_ClearFlag(dma->RxStream, dma->RxFlag);
|
||||
DMA_ITConfig(dma->RxStream, DMA_IT_TC, ENABLE);
|
||||
USART_DMACmd(uart_device, USART_DMAReq_Rx, ENABLE);
|
||||
DMA_Cmd(dma->RxStream, ENABLE);
|
||||
|
||||
NVIC_InitStructure.NVIC_IRQChannel = dma->RxIrqCh;
|
||||
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
|
||||
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
|
||||
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||
NVIC_Init(&NVIC_InitStructure);
|
||||
}
|
||||
|
||||
static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struct SerialCfgParam *serial_cfg_new)
|
||||
{
|
||||
struct SerialDataCfg *data_cfg_default = &serial_cfg_default->data_cfg;
|
||||
struct SerialDataCfg *data_cfg_new = &serial_cfg_new->data_cfg;
|
||||
|
||||
if((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) {
|
||||
data_cfg_default->serial_baud_rate = data_cfg_new->serial_baud_rate;
|
||||
}
|
||||
|
||||
if((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order)) {
|
||||
data_cfg_default->serial_bit_order = data_cfg_new->serial_bit_order;
|
||||
}
|
||||
|
||||
if((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)) {
|
||||
data_cfg_default->serial_buffer_size = data_cfg_new->serial_buffer_size;
|
||||
}
|
||||
|
||||
if((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits)) {
|
||||
data_cfg_default->serial_data_bits = data_cfg_new->serial_data_bits;
|
||||
}
|
||||
|
||||
if((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode)) {
|
||||
data_cfg_default->serial_invert_mode = data_cfg_new->serial_invert_mode;
|
||||
}
|
||||
|
||||
if((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)) {
|
||||
data_cfg_default->serial_parity_mode = data_cfg_new->serial_parity_mode;
|
||||
}
|
||||
|
||||
if((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
|
||||
data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
|
||||
}
|
||||
}
|
||||
|
||||
static uint32 Stm32SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info)
|
||||
{
|
||||
NULL_PARAM_CHECK(serial_drv);
|
||||
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
|
||||
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
|
||||
|
||||
if (configure_info->private_data) {
|
||||
struct SerialCfgParam *serial_cfg_new = (struct SerialCfgParam *)configure_info->private_data;
|
||||
SerialCfgParamCheck(serial_cfg, serial_cfg_new);
|
||||
}
|
||||
|
||||
USART_InitTypeDef USART_InitStructure;
|
||||
|
||||
USART_InitStructure.USART_BaudRate = serial_cfg->data_cfg.serial_baud_rate;
|
||||
|
||||
if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_8) {
|
||||
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
|
||||
} else if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_9) {
|
||||
USART_InitStructure.USART_WordLength = USART_WordLength_9b;
|
||||
}
|
||||
|
||||
if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_1){
|
||||
USART_InitStructure.USART_StopBits = USART_StopBits_1;
|
||||
} else if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_2) {
|
||||
USART_InitStructure.USART_StopBits = USART_StopBits_2;
|
||||
}
|
||||
|
||||
if (serial_cfg->data_cfg.serial_parity_mode == PARITY_NONE) {
|
||||
USART_InitStructure.USART_Parity = USART_Parity_No;
|
||||
} else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_ODD) {
|
||||
USART_InitStructure.USART_Parity = USART_Parity_Odd;
|
||||
} else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_EVEN) {
|
||||
USART_InitStructure.USART_Parity = USART_Parity_Even;
|
||||
}
|
||||
|
||||
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
||||
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
|
||||
USART_Init(serial_hw_cfg->uart_device, &USART_InitStructure);
|
||||
|
||||
USART_Cmd(serial_hw_cfg->uart_device, ENABLE);
|
||||
|
||||
return EOK;
|
||||
}
|
||||
|
||||
static uint32 Stm32SerialConfigure(struct SerialDriver *serial_drv, int serial_operation_cmd)
|
||||
{
|
||||
NULL_PARAM_CHECK(serial_drv);
|
||||
|
||||
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
|
||||
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
|
||||
struct SerialDevParam *serial_dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
|
||||
|
||||
switch (serial_operation_cmd)
|
||||
{
|
||||
case OPER_CLR_INT:
|
||||
UART_DISABLE_IRQ(serial_hw_cfg->irq);
|
||||
USART_ITConfig(serial_hw_cfg->uart_device, USART_IT_RXNE, DISABLE);
|
||||
break;
|
||||
case OPER_SET_INT:
|
||||
UART_ENABLE_IRQ(serial_hw_cfg->irq);
|
||||
USART_ITConfig(serial_hw_cfg->uart_device, USART_IT_RXNE, ENABLE);
|
||||
break;
|
||||
case OPER_CONFIG :
|
||||
if (SIGN_OPER_DMA_RX == serial_dev_param->serial_set_mode){
|
||||
DMAConfiguration(serial_dev, serial_hw_cfg->uart_device);
|
||||
}
|
||||
}
|
||||
|
||||
return EOK;
|
||||
}
|
||||
|
||||
static int Stm32SerialPutchar(struct SerialHardwareDevice *serial_dev, char c)
|
||||
{
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
|
||||
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
|
||||
|
||||
while (!(serial_hw_cfg->uart_device->SR & USART_FLAG_TXE));
|
||||
serial_hw_cfg->uart_device->DR = c;
|
||||
|
||||
return EOK;
|
||||
}
|
||||
|
||||
static int Stm32SerialGetchar(struct SerialHardwareDevice *serial_dev)
|
||||
{
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
|
||||
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
|
||||
|
||||
int ch = -1;
|
||||
if (serial_hw_cfg->uart_device->SR & USART_FLAG_RXNE) {
|
||||
ch = serial_hw_cfg->uart_device->DR & 0xff;
|
||||
}
|
||||
|
||||
return ch;
|
||||
}
|
||||
|
||||
static void DmaUartRxIdleIsr(struct SerialHardwareDevice *serial_dev, struct Stm32UsartDma *dma, USART_TypeDef *uart_device)
|
||||
{
|
||||
x_base level = CriticalAreaLock();
|
||||
|
||||
x_size_t recv_total_index = dma->SettingRecvLen - DMA_GetCurrDataCounter(dma->RxStream);
|
||||
x_size_t recv_len = recv_total_index - dma->LastRecvIndex;
|
||||
dma->LastRecvIndex = recv_total_index;
|
||||
CriticalAreaUnLock(level);
|
||||
|
||||
if (recv_len) SerialSetIsr(serial_dev, SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
|
||||
|
||||
USART_ReceiveData(uart_device);
|
||||
}
|
||||
|
||||
static void DmaRxDoneIsr(struct Stm32Usart *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev)
|
||||
{
|
||||
struct Stm32UsartDma *dma = &serial->dma;
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
|
||||
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
|
||||
|
||||
if (DMA_GetFlagStatus(dma->RxStream, dma->RxFlag) != RESET) {
|
||||
x_base level = CriticalAreaLock();
|
||||
|
||||
x_size_t recv_len = dma->SettingRecvLen - dma->LastRecvIndex;
|
||||
dma->LastRecvIndex = 0;
|
||||
CriticalAreaUnLock(level);
|
||||
|
||||
if (recv_len) SerialSetIsr(serial_dev, SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
|
||||
|
||||
DMA_ClearFlag(dma->RxStream, dma->RxFlag);
|
||||
}
|
||||
}
|
||||
|
||||
static void UartIsr(struct Stm32Usart *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev)
|
||||
{
|
||||
struct Stm32UsartDma *dma = &serial->dma;
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
|
||||
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
|
||||
|
||||
if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_RXNE) != RESET) {
|
||||
SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND);
|
||||
USART_ClearITPendingBit(serial_hw_cfg->uart_device, USART_IT_RXNE);
|
||||
}
|
||||
if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_IDLE) != RESET) {
|
||||
DmaUartRxIdleIsr(serial_dev, dma, serial_hw_cfg->uart_device);
|
||||
}
|
||||
if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_TC) != RESET) {
|
||||
USART_ClearITPendingBit(serial_hw_cfg->uart_device, USART_IT_TC);
|
||||
}
|
||||
if (USART_GetFlagStatus(serial_hw_cfg->uart_device, USART_FLAG_ORE) == SET) {
|
||||
USART_ReceiveData(serial_hw_cfg->uart_device);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef BSP_USING_USART1
|
||||
struct Stm32Usart serial_1;
|
||||
struct SerialDriver serial_driver_1;
|
||||
struct SerialHardwareDevice serial_device_1;
|
||||
|
||||
static const struct Stm32UsartDma usart_dma_1 =
|
||||
{
|
||||
DMA2_Stream5,
|
||||
DMA_Channel_4,
|
||||
DMA_FLAG_TCIF5,
|
||||
DMA2_Stream5_IRQn,
|
||||
0,
|
||||
0,
|
||||
};
|
||||
|
||||
void USART1_IRQHandler(int irq_num, void *arg)
|
||||
{
|
||||
UartIsr(&serial_1, &serial_driver_1, &serial_device_1);
|
||||
}
|
||||
DECLARE_HW_IRQ(USART1_IRQn, USART1_IRQHandler, NONE);
|
||||
|
||||
void DMA2_Stream5_IRQHandler(int irq_num, void *arg) {
|
||||
DmaRxDoneIsr(&serial_1, &serial_driver_1, &serial_device_1);
|
||||
}
|
||||
DECLARE_HW_IRQ(DMA2_Stream5_IRQn, DMA2_Stream5_IRQHandler, NONE);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_USART2
|
||||
struct Stm32Usart serial_2;
|
||||
struct SerialDriver serial_driver_2;
|
||||
struct SerialHardwareDevice serial_device_2;
|
||||
|
||||
static const struct Stm32UsartDma usart_dma_2 =
|
||||
{
|
||||
DMA1_Stream5,
|
||||
DMA_Channel_4,
|
||||
DMA_FLAG_TCIF5,
|
||||
DMA1_Stream5_IRQn,
|
||||
0,
|
||||
0,
|
||||
};
|
||||
|
||||
void USART2_IRQHandler(int irq_num, void *arg)
|
||||
{
|
||||
UartIsr(&serial_2, &serial_driver_2, &serial_device_2);
|
||||
}
|
||||
DECLARE_HW_IRQ(USART2_IRQn, USART2_IRQHandler, NONE);
|
||||
|
||||
void DMA1_Stream5_IRQHandler(int irq_num, void *arg) {
|
||||
DmaRxDoneIsr(&serial_2, &serial_driver_2, &serial_device_2);
|
||||
}
|
||||
DECLARE_HW_IRQ(DMA1_Stream5_IRQn, DMA1_Stream5_IRQHandler, NONE);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_USART3
|
||||
struct Stm32Usart serial_3;
|
||||
struct SerialDriver serial_driver_3;
|
||||
struct SerialHardwareDevice serial_device_3;
|
||||
|
||||
static const struct Stm32UsartDma usart_dma_3 =
|
||||
{
|
||||
DMA1_Stream1,
|
||||
DMA_Channel_4,
|
||||
DMA_FLAG_TCIF1,
|
||||
DMA1_Stream1_IRQn,
|
||||
0,
|
||||
0,
|
||||
};
|
||||
|
||||
void USART3_IRQHandler(int irq_num, void *arg)
|
||||
{
|
||||
UartIsr(&serial_3, &serial_driver_3, &serial_device_3);
|
||||
}
|
||||
DECLARE_HW_IRQ(USART3_IRQn, USART3_IRQHandler, NONE);
|
||||
|
||||
void DMA1_Stream1_IRQHandler(int irq_num, void *arg) {
|
||||
DmaRxDoneIsr(&serial_3, &serial_driver_3, &serial_device_3);
|
||||
}
|
||||
DECLARE_HW_IRQ(DMA1_Stream1_IRQn, DMA1_Stream1_IRQHandler, NONE);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART4
|
||||
struct Stm32Usart serial_4;
|
||||
struct SerialDriver serial_driver_4;
|
||||
struct SerialHardwareDevice serial_device_4;
|
||||
|
||||
static const struct Stm32UsartDma uart_dma_4 =
|
||||
{
|
||||
DMA1_Stream2,
|
||||
DMA_Channel_4,
|
||||
DMA_FLAG_TCIF2,
|
||||
DMA1_Stream2_IRQn,
|
||||
0,
|
||||
0,
|
||||
};
|
||||
|
||||
void UART4_IRQHandler(int irq_num, void *arg)
|
||||
{
|
||||
UartIsr(&serial_4, &serial_driver_4, &serial_device_4);
|
||||
}
|
||||
DECLARE_HW_IRQ(UART4_IRQn, UART4_IRQHandler, NONE);
|
||||
|
||||
void DMA1_Stream2_IRQHandler(int irq_num, void *arg) {
|
||||
DmaRxDoneIsr(&serial_4, &serial_driver_4, &serial_device_4);
|
||||
}
|
||||
DECLARE_HW_IRQ(DMA1_Stream2_IRQn, DMA1_Stream2_IRQHandler, NONE);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART5
|
||||
struct Stm32Usart serial_5;
|
||||
struct SerialDriver serial_driver_5;
|
||||
struct SerialHardwareDevice serial_device_5;
|
||||
|
||||
static const struct Stm32UsartDma uart_dma_5 =
|
||||
{
|
||||
DMA1_Stream0,
|
||||
DMA_Channel_4,
|
||||
DMA_FLAG_TCIF0,
|
||||
DMA1_Stream0_IRQn,
|
||||
0,
|
||||
0,
|
||||
};
|
||||
|
||||
void UART5_IRQHandler(int irq_num, void *arg)
|
||||
{
|
||||
UartIsr(&serial_5, &serial_driver_5, &serial_device_5);
|
||||
}
|
||||
DECLARE_HW_IRQ(UART5_IRQn, UART5_IRQHandler, NONE);
|
||||
|
||||
void DMA1_Stream0_IRQHandler(int irq_num, void *arg) {
|
||||
DmaRxDoneIsr(&serial_5, &serial_driver_5, &serial_device_5);
|
||||
}
|
||||
DECLARE_HW_IRQ(DMA1_Stream0_IRQn, DMA1_Stream0_IRQHandler, NONE);
|
||||
#endif
|
||||
|
||||
static uint32 Stm32SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
|
||||
{
|
||||
NULL_PARAM_CHECK(drv);
|
||||
NULL_PARAM_CHECK(configure_info);
|
||||
|
||||
x_err_t ret = EOK;
|
||||
int serial_operation_cmd;
|
||||
struct SerialDriver *serial_drv = (struct SerialDriver *)drv;
|
||||
|
||||
switch (configure_info->configure_cmd)
|
||||
{
|
||||
case OPE_INT:
|
||||
ret = Stm32SerialInit(serial_drv, configure_info);
|
||||
break;
|
||||
case OPE_CFG:
|
||||
serial_operation_cmd = *(int *)configure_info->private_data;
|
||||
ret = Stm32SerialConfigure(serial_drv, serial_operation_cmd);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct SerialDataCfg data_cfg_init =
|
||||
{
|
||||
.serial_baud_rate = BAUD_RATE_115200,
|
||||
.serial_data_bits = DATA_BITS_8,
|
||||
.serial_stop_bits = STOP_BITS_1,
|
||||
.serial_parity_mode = PARITY_NONE,
|
||||
.serial_bit_order = BIT_ORDER_LSB,
|
||||
.serial_invert_mode = NRZ_NORMAL,
|
||||
.serial_buffer_size = SERIAL_RB_BUFSZ,
|
||||
};
|
||||
|
||||
/*manage the serial device operations*/
|
||||
static const struct SerialDrvDone drv_done =
|
||||
{
|
||||
.init = Stm32SerialInit,
|
||||
.configure = Stm32SerialConfigure,
|
||||
};
|
||||
|
||||
/*manage the serial device hal operations*/
|
||||
static struct SerialHwDevDone hwdev_done =
|
||||
{
|
||||
.put_char = Stm32SerialPutchar,
|
||||
.get_char = Stm32SerialGetchar,
|
||||
};
|
||||
|
||||
static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver *serial_driver, const char *bus_name, const char *drv_name)
|
||||
{
|
||||
x_err_t ret = EOK;
|
||||
|
||||
/*Init the serial bus */
|
||||
ret = SerialBusInit(serial_bus, bus_name);
|
||||
if (EOK != ret) {
|
||||
KPrintf("hw_serial_init SerialBusInit error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
/*Init the serial driver*/
|
||||
ret = SerialDriverInit(serial_driver, drv_name);
|
||||
if (EOK != ret) {
|
||||
KPrintf("hw_serial_init SerialDriverInit error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
/*Attach the serial driver to the serial bus*/
|
||||
ret = SerialDriverAttachToBus(drv_name, bus_name);
|
||||
if (EOK != ret) {
|
||||
KPrintf("hw_serial_init SerialDriverAttachToBus error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*Attach the serial device to the serial bus*/
|
||||
static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *serial_param, const char *bus_name, const char *dev_name)
|
||||
{
|
||||
x_err_t ret = EOK;
|
||||
|
||||
ret = SerialDeviceRegister(serial_device, serial_param, dev_name);
|
||||
if (EOK != ret) {
|
||||
KPrintf("hw_serial_init SerialDeviceInit device %s error %d\n", dev_name, ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
ret = SerialDeviceAttachToBus(dev_name, bus_name);
|
||||
if (EOK != ret) {
|
||||
KPrintf("hw_serial_init SerialDeviceAttachToBus device %s error %d\n", dev_name, ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int InitHwUsart(void)
|
||||
{
|
||||
x_err_t ret = EOK;
|
||||
|
||||
RCCConfiguration();
|
||||
GPIOConfiguration();
|
||||
|
||||
#ifdef BSP_USING_USART1
|
||||
static struct SerialCfgParam serial_cfg_1;
|
||||
memset(&serial_cfg_1, 0, sizeof(struct SerialCfgParam));
|
||||
|
||||
static struct UsartHwCfg serial_hw_cfg_1;
|
||||
memset(&serial_hw_cfg_1, 0, sizeof(struct UsartHwCfg));
|
||||
|
||||
static struct SerialDevParam serial_dev_param_1;
|
||||
memset(&serial_dev_param_1, 0, sizeof(struct SerialDevParam));
|
||||
|
||||
serial_1.dma = usart_dma_1;
|
||||
|
||||
serial_driver_1.drv_done = &drv_done;
|
||||
serial_driver_1.configure = &Stm32SerialDrvConfigure;
|
||||
serial_device_1.hwdev_done = &hwdev_done;
|
||||
|
||||
serial_cfg_1.data_cfg = data_cfg_init;
|
||||
|
||||
serial_hw_cfg_1.uart_device = USART1;
|
||||
serial_hw_cfg_1.irq = USART1_IRQn;
|
||||
serial_cfg_1.hw_cfg.private_data = (void *)&serial_hw_cfg_1;
|
||||
serial_driver_1.private_data = (void *)&serial_cfg_1;
|
||||
|
||||
serial_dev_param_1.serial_work_mode = SIGN_OPER_INT_RX;
|
||||
serial_device_1.haldev.private_data = (void *)&serial_dev_param_1;
|
||||
|
||||
NVIC_Configuration(serial_hw_cfg_1.irq);
|
||||
|
||||
ret = BoardSerialBusInit(&serial_1.serial_bus, &serial_driver_1, SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUsart usart1 error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
ret = BoardSerialDevBend(&serial_device_1, (void *)&serial_cfg_1, SERIAL_BUS_NAME_1, SERIAL_1_DEVICE_NAME_0);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUsart usart1 error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_USART2
|
||||
static struct SerialCfgParam serial_cfg_2;
|
||||
memset(&serial_cfg_2, 0, sizeof(struct SerialCfgParam));
|
||||
|
||||
static struct UsartHwCfg serial_hw_cfg_2;
|
||||
memset(&serial_hw_cfg_2, 0, sizeof(struct UsartHwCfg));
|
||||
|
||||
static struct SerialDevParam serial_dev_param_2;
|
||||
memset(&serial_dev_param_2, 0, sizeof(struct SerialDevParam));
|
||||
|
||||
serial_2.dma = usart_dma_2;
|
||||
|
||||
serial_driver_2.drv_done = &drv_done;
|
||||
serial_driver_2.configure = &Stm32SerialDrvConfigure;
|
||||
serial_device_2.hwdev_done = &hwdev_done;
|
||||
|
||||
serial_cfg_2.data_cfg = data_cfg_init;
|
||||
|
||||
serial_hw_cfg_2.uart_device = USART2;
|
||||
serial_hw_cfg_2.irq = USART2_IRQn;
|
||||
serial_cfg_2.hw_cfg.private_data = (void *)&serial_hw_cfg_2;
|
||||
serial_driver_2.private_data = (void *)&serial_cfg_2;
|
||||
|
||||
serial_dev_param_2.serial_work_mode = SIGN_OPER_INT_RX;
|
||||
serial_device_2.haldev.private_data = (void *)&serial_dev_param_2;
|
||||
|
||||
NVIC_Configuration(serial_hw_cfg_2.irq);
|
||||
|
||||
ret = BoardSerialBusInit(&serial_2.serial_bus, &serial_driver_2, SERIAL_BUS_NAME_2, SERIAL_DRV_NAME_2);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUsart usart2 error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
ret = BoardSerialDevBend(&serial_device_2, (void *)&serial_cfg_2, SERIAL_BUS_NAME_2, SERIAL_2_DEVICE_NAME_0);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUsart usart2 error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_USART3
|
||||
static struct SerialCfgParam serial_cfg_3;
|
||||
memset(&serial_cfg_3, 0, sizeof(struct SerialCfgParam));
|
||||
|
||||
static struct UsartHwCfg serial_hw_cfg_3;
|
||||
memset(&serial_hw_cfg_3, 0, sizeof(struct UsartHwCfg));
|
||||
|
||||
static struct SerialDevParam serial_dev_param_3;
|
||||
memset(&serial_dev_param_3, 0, sizeof(struct SerialDevParam));
|
||||
|
||||
serial_3.dma = usart_dma_3;
|
||||
|
||||
serial_driver_3.drv_done = &drv_done;
|
||||
serial_driver_3.configure = &Stm32SerialDrvConfigure;
|
||||
serial_device_3.hwdev_done = &hwdev_done;
|
||||
|
||||
serial_cfg_3.data_cfg = data_cfg_init;
|
||||
|
||||
serial_hw_cfg_3.uart_device = USART3;
|
||||
serial_hw_cfg_3.irq = USART3_IRQn;
|
||||
serial_cfg_3.hw_cfg.private_data = (void *)&serial_hw_cfg_3;
|
||||
serial_driver_3.private_data = (void *)&serial_cfg_3;
|
||||
|
||||
serial_dev_param_3.serial_work_mode = SIGN_OPER_INT_RX;
|
||||
serial_device_3.haldev.private_data = (void *)&serial_dev_param_3;
|
||||
|
||||
NVIC_Configuration(serial_hw_cfg_3.irq);
|
||||
|
||||
ret = BoardSerialBusInit(&serial_3.serial_bus, &serial_driver_3, SERIAL_BUS_NAME_3, SERIAL_DRV_NAME_3);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUsart usart3 error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
ret = BoardSerialDevBend(&serial_device_3, (void *)&serial_cfg_3, SERIAL_BUS_NAME_3, SERIAL_3_DEVICE_NAME_0);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUsart usart3 error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART4
|
||||
static struct SerialCfgParam serial_cfg_4;
|
||||
memset(&serial_cfg_4, 0, sizeof(struct SerialCfgParam));
|
||||
|
||||
static struct UsartHwCfg serial_hw_cfg_4;
|
||||
memset(&serial_hw_cfg_4, 0, sizeof(struct UsartHwCfg));
|
||||
|
||||
static struct SerialDevParam serial_dev_param_4;
|
||||
memset(&serial_dev_param_4, 0, sizeof(struct SerialDevParam));
|
||||
|
||||
serial_4.dma = uart_dma_4;
|
||||
|
||||
serial_driver_4.drv_done = &drv_done;
|
||||
serial_driver_4.configure = &Stm32SerialDrvConfigure;
|
||||
serial_device_4.hwdev_done = &hwdev_done;
|
||||
|
||||
serial_cfg_4.data_cfg = data_cfg_init;
|
||||
|
||||
serial_hw_cfg_4.uart_device = UART4;
|
||||
serial_hw_cfg_4.irq = UART4_IRQn;
|
||||
serial_cfg_4.hw_cfg.private_data = (void *)&serial_hw_cfg_4;
|
||||
serial_driver_4.private_data = (void *)&serial_cfg_4;
|
||||
|
||||
serial_dev_param_4.serial_work_mode = SIGN_OPER_INT_RX;
|
||||
serial_device_4.haldev.private_data = (void *)&serial_dev_param_4;
|
||||
|
||||
NVIC_Configuration(serial_hw_cfg_4.irq);
|
||||
|
||||
ret = BoardSerialBusInit(&serial_4.serial_bus, &serial_driver_4, SERIAL_BUS_NAME_4, SERIAL_DRV_NAME_4);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUsart usart4 error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
ret = BoardSerialDevBend(&serial_device_4, (void *)&serial_cfg_4, SERIAL_BUS_NAME_4, SERIAL_4_DEVICE_NAME_0);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUsart usart4 error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART5
|
||||
static struct SerialCfgParam serial_cfg_5;
|
||||
memset(&serial_cfg_5, 0, sizeof(struct SerialCfgParam));
|
||||
|
||||
static struct UsartHwCfg serial_hw_cfg_5;
|
||||
memset(&serial_hw_cfg_5, 0, sizeof(struct UsartHwCfg));
|
||||
|
||||
static struct SerialDevParam serial_dev_param_5;
|
||||
memset(&serial_dev_param_5, 0, sizeof(struct SerialDevParam));
|
||||
|
||||
serial_5.dma = uart_dma_5;
|
||||
|
||||
serial_driver_5.drv_done = &drv_done;
|
||||
serial_driver_5.configure = &Stm32SerialDrvConfigure;
|
||||
serial_device_5.hwdev_done = &hwdev_done;
|
||||
|
||||
serial_cfg_5.data_cfg = data_cfg_init;
|
||||
|
||||
serial_hw_cfg_5.uart_device = UART5;
|
||||
serial_hw_cfg_5.irq = UART5_IRQn;
|
||||
serial_cfg_5.hw_cfg.private_data = (void *)&serial_hw_cfg_5;
|
||||
serial_driver_5.private_data = (void *)&serial_cfg_5;
|
||||
|
||||
serial_dev_param_5.serial_work_mode = SIGN_OPER_INT_RX;
|
||||
serial_device_5.haldev.private_data = (void *)&serial_dev_param_5;
|
||||
|
||||
NVIC_Configuration(serial_hw_cfg_5.irq);
|
||||
|
||||
ret = BoardSerialBusInit(&serial_5.serial_bus, &serial_driver_5, SERIAL_BUS_NAME_5, SERIAL_DRV_NAME_5);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUsart usart5 error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
ret = BoardSerialDevBend(&serial_device_5, (void *)&serial_cfg_5, SERIAL_BUS_NAME_5, SERIAL_5_DEVICE_NAME_0);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUsart usart5 error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -0,0 +1,185 @@
|
|||
#ifndef XS_CONFIG_H__
|
||||
#define XS_CONFIG_H__
|
||||
|
||||
/* Automatically generated file; DO NOT EDIT. */
|
||||
/* XiUOS Project Configuration */
|
||||
|
||||
#define BOARD_STM32F407_EVB
|
||||
#define ARCH_ARM
|
||||
|
||||
/* stm32f407-st-discovery feature */
|
||||
|
||||
#define BSP_USING_DMA
|
||||
#define BSP_USING_GPIO
|
||||
#define PIN_BUS_NAME "pin"
|
||||
#define PIN_DRIVER_NAME "pin_drv"
|
||||
#define PIN_DEVICE_NAME "pin_dev"
|
||||
#define BSP_USING_UART
|
||||
#define BSP_USING_USART1
|
||||
#define SERIAL_BUS_NAME_1 "usart1"
|
||||
#define SERIAL_DRV_NAME_1 "usart1_drv"
|
||||
#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
|
||||
#define BSP_USING_USART2
|
||||
#define SERIAL_BUS_NAME_2 "usart2"
|
||||
#define SERIAL_DRV_NAME_2 "usart2_drv"
|
||||
#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
|
||||
#define BSP_USING_USART3
|
||||
#define SERIAL_BUS_NAME_3 "usart3"
|
||||
#define SERIAL_DRV_NAME_3 "usart3_drv"
|
||||
#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
|
||||
#define BSP_USING_WDT
|
||||
#define WDT_BUS_NAME "wdt"
|
||||
#define WDT_DRIVER_NAME "wdt_drv"
|
||||
#define WDT_DEVICE_NAME "wdt_dev"
|
||||
|
||||
/* config default board resources */
|
||||
|
||||
/* config board app name */
|
||||
|
||||
#define BOARD_APP_NAME "/XiUOS_stm32f407-st-discovery_app.bin"
|
||||
|
||||
/* config board service table */
|
||||
|
||||
#define SERVICE_TABLE_ADDRESS 0x20000000
|
||||
|
||||
/* config hardware resources for connection */
|
||||
|
||||
/* Hardware feature */
|
||||
|
||||
#define RESOURCES_SERIAL
|
||||
#define SERIAL_USING_DMA
|
||||
#define SERIAL_RB_BUFSZ 128
|
||||
#define RESOURCES_PIN
|
||||
#define RESOURCES_WDT
|
||||
|
||||
/* Kernel feature */
|
||||
|
||||
/* separate compile(choose none for compile once) */
|
||||
|
||||
#define APP_STARTUP_FROM_FLASH
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
#define MEM_ALIGN_SIZE 8
|
||||
#define MM_PAGE_SIZE 4096
|
||||
|
||||
/* Using small memory allocator */
|
||||
|
||||
#define KERNEL_SMALL_MEM_ALLOC
|
||||
#define SMALL_NUMBER_32B 64
|
||||
#define SMALL_NUMBER_64B 32
|
||||
|
||||
/* Task feature */
|
||||
|
||||
#define USER_APPLICATION
|
||||
|
||||
/* Inter-Task communication */
|
||||
|
||||
#define KERNEL_SEMAPHORE
|
||||
#define KERNEL_MUTEX
|
||||
#define KERNEL_EVENT
|
||||
#define KERNEL_MESSAGEQUEUE
|
||||
#define KERNEL_SOFTTIMER
|
||||
#define SCHED_POLICY_RR_REMAINSLICE
|
||||
#define KTASK_PRIORITY_32
|
||||
#define KTASK_PRIORITY_MAX 32
|
||||
#define TICK_PER_SECOND 1000
|
||||
#define KERNEL_STACK_OVERFLOW_CHECK
|
||||
#define IDLE_KTASK_STACKSIZE 256
|
||||
#define ZOMBIE_KTASK_STACKSIZE 2048
|
||||
|
||||
/* Kernel Console */
|
||||
|
||||
#define KERNEL_CONSOLE
|
||||
#define KERNEL_BANNER
|
||||
#define KERNEL_CONSOLEBUF_SIZE 128
|
||||
|
||||
/* Kernel Hook */
|
||||
|
||||
|
||||
/* Command shell */
|
||||
|
||||
#define TOOL_SHELL
|
||||
#define SHELL_ENTER_CR
|
||||
#define SHELL_ENTER_LF
|
||||
#define SHELL_ENTER_CR_AND_LF
|
||||
|
||||
/* Set shell user control */
|
||||
|
||||
#define SHELL_DEFAULT_USER "letter"
|
||||
#define SHELL_DEFAULT_USER_PASSWORD ""
|
||||
#define SHELL_LOCK_TIMEOUT 10000
|
||||
|
||||
/* Set shell config param */
|
||||
|
||||
#define SHELL_TASK_STACK_SIZE 4096
|
||||
#define SHELL_TASK_PRIORITY 20
|
||||
#define SHELL_MAX_NUMBER 5
|
||||
#define SHELL_PARAMETER_MAX_NUMBER 8
|
||||
#define SHELL_HISTORY_MAX_NUMBER 5
|
||||
#define SHELL_PRINT_BUFFER 128
|
||||
#define SHELL_HELP_SHOW_PERMISSION
|
||||
|
||||
/* Kernel data structure Manage */
|
||||
|
||||
#define KERNEL_QUEUEMANAGE
|
||||
#define KERNEL_WORKQUEUE
|
||||
#define WORKQUEUE_KTASK_STACKSIZE 512
|
||||
#define WORKQUEUE_KTASK_PRIORITY 23
|
||||
#define QUEUE_MAX 16
|
||||
#define KERNEL_WAITQUEUE
|
||||
#define KERNEL_DATAQUEUE
|
||||
|
||||
/* Kernel components init */
|
||||
|
||||
#define KERNEL_COMPONENTS_INIT
|
||||
#define ENV_INIT_KTASK_STACK_SIZE 8192
|
||||
#define KERNEL_USER_MAIN
|
||||
#define NAME_NUM_MAX 32
|
||||
|
||||
/* hash table config */
|
||||
|
||||
#define ID_HTABLE_SIZE 16
|
||||
#define ID_NUM_MAX 128
|
||||
|
||||
/* File system */
|
||||
|
||||
#define FS_VFS
|
||||
#define VFS_USING_WORKDIR
|
||||
#define FS_VFS_DEVFS
|
||||
#define FS_VFS_FATFS
|
||||
|
||||
/* APP Framework */
|
||||
|
||||
/* Perception */
|
||||
|
||||
|
||||
/* connection */
|
||||
|
||||
|
||||
/* Intelligence */
|
||||
|
||||
|
||||
/* Control */
|
||||
|
||||
/* Lib */
|
||||
|
||||
#define LIB
|
||||
#define LIB_POSIX
|
||||
|
||||
/* C++ features */
|
||||
|
||||
#define LIB_NEWLIB
|
||||
|
||||
/* Security */
|
||||
|
||||
|
||||
/* Applications */
|
||||
|
||||
|
||||
/* config stack size and priority of main task */
|
||||
|
||||
#define MAIN_KTASK_STACK_SIZE 2048
|
||||
#define MAIN_KTASK_PRIORITY 10
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,185 @@
|
|||
#ifndef XS_CONFIG_H__
|
||||
#define XS_CONFIG_H__
|
||||
|
||||
/* Automatically generated file; DO NOT EDIT. */
|
||||
/* XiUOS Project Configuration */
|
||||
|
||||
#define BOARD_CORTEX_M4_EVB
|
||||
#define ARCH_ARM
|
||||
|
||||
/* stm32f407-st-discovery feature */
|
||||
|
||||
#define BSP_USING_DMA
|
||||
#define BSP_USING_GPIO
|
||||
#define PIN_BUS_NAME "pin"
|
||||
#define PIN_DRIVER_NAME "pin_drv"
|
||||
#define PIN_DEVICE_NAME "pin_dev"
|
||||
#define BSP_USING_UART
|
||||
#define BSP_USING_USART1
|
||||
#define SERIAL_BUS_NAME_1 "usart1"
|
||||
#define SERIAL_DRV_NAME_1 "usart1_drv"
|
||||
#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
|
||||
#define BSP_USING_USART2
|
||||
#define SERIAL_BUS_NAME_2 "usart2"
|
||||
#define SERIAL_DRV_NAME_2 "usart2_drv"
|
||||
#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
|
||||
#define BSP_USING_USART3
|
||||
#define SERIAL_BUS_NAME_3 "usart3"
|
||||
#define SERIAL_DRV_NAME_3 "usart3_drv"
|
||||
#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
|
||||
#define BSP_USING_WDT
|
||||
#define WDT_BUS_NAME "wdt"
|
||||
#define WDT_DRIVER_NAME "wdt_drv"
|
||||
#define WDT_DEVICE_NAME "wdt_dev"
|
||||
|
||||
/* config default board resources */
|
||||
|
||||
/* config board app name */
|
||||
|
||||
#define BOARD_APP_NAME "/XiUOS_stm32f407-st-discovery_app.bin"
|
||||
|
||||
/* config board service table */
|
||||
|
||||
#define SERVICE_TABLE_ADDRESS 0x20000000
|
||||
|
||||
/* config hardware resources for connection */
|
||||
|
||||
/* Hardware feature */
|
||||
|
||||
#define RESOURCES_SERIAL
|
||||
#define SERIAL_USING_DMA
|
||||
#define SERIAL_RB_BUFSZ 128
|
||||
#define RESOURCES_PIN
|
||||
#define RESOURCES_WDT
|
||||
|
||||
/* Kernel feature */
|
||||
|
||||
/* separate compile(choose none for compile once) */
|
||||
|
||||
#define APP_STARTUP_FROM_FLASH
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
#define MEM_ALIGN_SIZE 8
|
||||
#define MM_PAGE_SIZE 4096
|
||||
|
||||
/* Using small memory allocator */
|
||||
|
||||
#define KERNEL_SMALL_MEM_ALLOC
|
||||
#define SMALL_NUMBER_32B 64
|
||||
#define SMALL_NUMBER_64B 32
|
||||
|
||||
/* Task feature */
|
||||
|
||||
#define USER_APPLICATION
|
||||
|
||||
/* Inter-Task communication */
|
||||
|
||||
#define KERNEL_SEMAPHORE
|
||||
#define KERNEL_MUTEX
|
||||
#define KERNEL_EVENT
|
||||
#define KERNEL_MESSAGEQUEUE
|
||||
#define KERNEL_SOFTTIMER
|
||||
#define SCHED_POLICY_RR_REMAINSLICE
|
||||
#define KTASK_PRIORITY_32
|
||||
#define KTASK_PRIORITY_MAX 32
|
||||
#define TICK_PER_SECOND 1000
|
||||
#define KERNEL_STACK_OVERFLOW_CHECK
|
||||
#define IDLE_KTASK_STACKSIZE 256
|
||||
#define ZOMBIE_KTASK_STACKSIZE 2048
|
||||
|
||||
/* Kernel Console */
|
||||
|
||||
#define KERNEL_CONSOLE
|
||||
#define KERNEL_BANNER
|
||||
#define KERNEL_CONSOLEBUF_SIZE 128
|
||||
|
||||
/* Kernel Hook */
|
||||
|
||||
|
||||
/* Command shell */
|
||||
|
||||
#define TOOL_SHELL
|
||||
#define SHELL_ENTER_CR
|
||||
#define SHELL_ENTER_LF
|
||||
#define SHELL_ENTER_CR_AND_LF
|
||||
|
||||
/* Set shell user control */
|
||||
|
||||
#define SHELL_DEFAULT_USER "letter"
|
||||
#define SHELL_DEFAULT_USER_PASSWORD ""
|
||||
#define SHELL_LOCK_TIMEOUT 10000
|
||||
|
||||
/* Set shell config param */
|
||||
|
||||
#define SHELL_TASK_STACK_SIZE 4096
|
||||
#define SHELL_TASK_PRIORITY 20
|
||||
#define SHELL_MAX_NUMBER 5
|
||||
#define SHELL_PARAMETER_MAX_NUMBER 8
|
||||
#define SHELL_HISTORY_MAX_NUMBER 5
|
||||
#define SHELL_PRINT_BUFFER 128
|
||||
#define SHELL_HELP_SHOW_PERMISSION
|
||||
|
||||
/* Kernel data structure Manage */
|
||||
|
||||
#define KERNEL_QUEUEMANAGE
|
||||
#define KERNEL_WORKQUEUE
|
||||
#define WORKQUEUE_KTASK_STACKSIZE 512
|
||||
#define WORKQUEUE_KTASK_PRIORITY 23
|
||||
#define QUEUE_MAX 16
|
||||
#define KERNEL_WAITQUEUE
|
||||
#define KERNEL_DATAQUEUE
|
||||
|
||||
/* Kernel components init */
|
||||
|
||||
#define KERNEL_COMPONENTS_INIT
|
||||
#define ENV_INIT_KTASK_STACK_SIZE 8192
|
||||
#define KERNEL_USER_MAIN
|
||||
#define NAME_NUM_MAX 32
|
||||
|
||||
/* hash table config */
|
||||
|
||||
#define ID_HTABLE_SIZE 16
|
||||
#define ID_NUM_MAX 128
|
||||
|
||||
/* File system */
|
||||
|
||||
#define FS_VFS
|
||||
#define VFS_USING_WORKDIR
|
||||
#define FS_VFS_DEVFS
|
||||
#define FS_VFS_FATFS
|
||||
|
||||
/* APP Framework */
|
||||
|
||||
/* Perception */
|
||||
|
||||
|
||||
/* connection */
|
||||
|
||||
|
||||
/* Intelligence */
|
||||
|
||||
|
||||
/* Control */
|
||||
|
||||
/* Lib */
|
||||
|
||||
#define LIB
|
||||
#define LIB_POSIX
|
||||
|
||||
/* C++ features */
|
||||
|
||||
#define LIB_NEWLIB
|
||||
|
||||
/* Security */
|
||||
|
||||
|
||||
/* Applications */
|
||||
|
||||
|
||||
/* config stack size and priority of main task */
|
||||
|
||||
#define MAIN_KTASK_STACK_SIZE 2048
|
||||
#define MAIN_KTASK_PRIORITY 10
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,185 @@
|
|||
#ifndef XS_CONFIG_H__
|
||||
#define XS_CONFIG_H__
|
||||
|
||||
/* Automatically generated file; DO NOT EDIT. */
|
||||
/* XiUOS Project Configuration */
|
||||
|
||||
#define BOARD_CORTEX_M4_EVB
|
||||
#define ARCH_ARM
|
||||
|
||||
/* stm32f407-st-discovery feature */
|
||||
|
||||
#define BSP_USING_DMA
|
||||
#define BSP_USING_GPIO
|
||||
#define PIN_BUS_NAME "pin"
|
||||
#define PIN_DRIVER_NAME "pin_drv"
|
||||
#define PIN_DEVICE_NAME "pin_dev"
|
||||
#define BSP_USING_UART
|
||||
#define BSP_USING_USART1
|
||||
#define SERIAL_BUS_NAME_1 "usart1"
|
||||
#define SERIAL_DRV_NAME_1 "usart1_drv"
|
||||
#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
|
||||
#define BSP_USING_USART2
|
||||
#define SERIAL_BUS_NAME_2 "usart2"
|
||||
#define SERIAL_DRV_NAME_2 "usart2_drv"
|
||||
#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
|
||||
#define BSP_USING_USART3
|
||||
#define SERIAL_BUS_NAME_3 "usart3"
|
||||
#define SERIAL_DRV_NAME_3 "usart3_drv"
|
||||
#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
|
||||
#define BSP_USING_WDT
|
||||
#define WDT_BUS_NAME "wdt"
|
||||
#define WDT_DRIVER_NAME "wdt_drv"
|
||||
#define WDT_DEVICE_NAME "wdt_dev"
|
||||
|
||||
/* config default board resources */
|
||||
|
||||
/* config board app name */
|
||||
|
||||
#define BOARD_APP_NAME "/XiUOS_stm32f407-st-discovery_app.bin"
|
||||
|
||||
/* config board service table */
|
||||
|
||||
#define SERVICE_TABLE_ADDRESS 0x20000000
|
||||
|
||||
/* config hardware resources for connection */
|
||||
|
||||
/* Hardware feature */
|
||||
|
||||
#define RESOURCES_SERIAL
|
||||
#define SERIAL_USING_DMA
|
||||
#define SERIAL_RB_BUFSZ 128
|
||||
#define RESOURCES_PIN
|
||||
#define RESOURCES_WDT
|
||||
|
||||
/* Kernel feature */
|
||||
|
||||
/* separate compile(choose none for compile once) */
|
||||
|
||||
#define APP_STARTUP_FROM_FLASH
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
#define MEM_ALIGN_SIZE 8
|
||||
#define MM_PAGE_SIZE 4096
|
||||
|
||||
/* Using small memory allocator */
|
||||
|
||||
#define KERNEL_SMALL_MEM_ALLOC
|
||||
#define SMALL_NUMBER_32B 64
|
||||
#define SMALL_NUMBER_64B 32
|
||||
|
||||
/* Task feature */
|
||||
|
||||
#define USER_APPLICATION
|
||||
|
||||
/* Inter-Task communication */
|
||||
|
||||
#define KERNEL_SEMAPHORE
|
||||
#define KERNEL_MUTEX
|
||||
#define KERNEL_EVENT
|
||||
#define KERNEL_MESSAGEQUEUE
|
||||
#define KERNEL_SOFTTIMER
|
||||
#define SCHED_POLICY_RR_REMAINSLICE
|
||||
#define KTASK_PRIORITY_32
|
||||
#define KTASK_PRIORITY_MAX 32
|
||||
#define TICK_PER_SECOND 1000
|
||||
#define KERNEL_STACK_OVERFLOW_CHECK
|
||||
#define IDLE_KTASK_STACKSIZE 256
|
||||
#define ZOMBIE_KTASK_STACKSIZE 2048
|
||||
|
||||
/* Kernel Console */
|
||||
|
||||
#define KERNEL_CONSOLE
|
||||
#define KERNEL_BANNER
|
||||
#define KERNEL_CONSOLEBUF_SIZE 128
|
||||
|
||||
/* Kernel Hook */
|
||||
|
||||
|
||||
/* Command shell */
|
||||
|
||||
#define TOOL_SHELL
|
||||
#define SHELL_ENTER_CR
|
||||
#define SHELL_ENTER_LF
|
||||
#define SHELL_ENTER_CR_AND_LF
|
||||
|
||||
/* Set shell user control */
|
||||
|
||||
#define SHELL_DEFAULT_USER "letter"
|
||||
#define SHELL_DEFAULT_USER_PASSWORD ""
|
||||
#define SHELL_LOCK_TIMEOUT 10000
|
||||
|
||||
/* Set shell config param */
|
||||
|
||||
#define SHELL_TASK_STACK_SIZE 4096
|
||||
#define SHELL_TASK_PRIORITY 20
|
||||
#define SHELL_MAX_NUMBER 5
|
||||
#define SHELL_PARAMETER_MAX_NUMBER 8
|
||||
#define SHELL_HISTORY_MAX_NUMBER 5
|
||||
#define SHELL_PRINT_BUFFER 128
|
||||
#define SHELL_HELP_SHOW_PERMISSION
|
||||
|
||||
/* Kernel data structure Manage */
|
||||
|
||||
#define KERNEL_QUEUEMANAGE
|
||||
#define KERNEL_WORKQUEUE
|
||||
#define WORKQUEUE_KTASK_STACKSIZE 512
|
||||
#define WORKQUEUE_KTASK_PRIORITY 23
|
||||
#define QUEUE_MAX 16
|
||||
#define KERNEL_WAITQUEUE
|
||||
#define KERNEL_DATAQUEUE
|
||||
|
||||
/* Kernel components init */
|
||||
|
||||
#define KERNEL_COMPONENTS_INIT
|
||||
#define ENV_INIT_KTASK_STACK_SIZE 8192
|
||||
#define KERNEL_USER_MAIN
|
||||
#define NAME_NUM_MAX 32
|
||||
|
||||
/* hash table config */
|
||||
|
||||
#define ID_HTABLE_SIZE 16
|
||||
#define ID_NUM_MAX 128
|
||||
|
||||
/* File system */
|
||||
|
||||
#define FS_VFS
|
||||
#define VFS_USING_WORKDIR
|
||||
#define FS_VFS_DEVFS
|
||||
#define FS_VFS_FATFS
|
||||
|
||||
/* APP Framework */
|
||||
|
||||
/* Perception */
|
||||
|
||||
|
||||
/* connection */
|
||||
|
||||
|
||||
/* Intelligence */
|
||||
|
||||
|
||||
/* Control */
|
||||
|
||||
/* Lib */
|
||||
|
||||
#define LIB
|
||||
#define LIB_POSIX
|
||||
|
||||
/* C++ features */
|
||||
|
||||
#define LIB_NEWLIB
|
||||
|
||||
/* Security */
|
||||
|
||||
|
||||
/* Applications */
|
||||
|
||||
|
||||
/* config stack size and priority of main task */
|
||||
|
||||
#define MAIN_KTASK_STACK_SIZE 2048
|
||||
#define MAIN_KTASK_PRIORITY 10
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,185 @@
|
|||
#ifndef XS_CONFIG_H__
|
||||
#define XS_CONFIG_H__
|
||||
|
||||
/* Automatically generated file; DO NOT EDIT. */
|
||||
/* XiUOS Project Configuration */
|
||||
|
||||
#define BOARD_CORTEX_M4_EVB
|
||||
#define ARCH_ARM
|
||||
|
||||
/* stm32f407-st-discovery feature */
|
||||
|
||||
#define BSP_USING_DMA
|
||||
#define BSP_USING_GPIO
|
||||
#define PIN_BUS_NAME "pin"
|
||||
#define PIN_DRIVER_NAME "pin_drv"
|
||||
#define PIN_DEVICE_NAME "pin_dev"
|
||||
#define BSP_USING_UART
|
||||
#define BSP_USING_USART1
|
||||
#define SERIAL_BUS_NAME_1 "usart1"
|
||||
#define SERIAL_DRV_NAME_1 "usart1_drv"
|
||||
#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
|
||||
#define BSP_USING_USART2
|
||||
#define SERIAL_BUS_NAME_2 "usart2"
|
||||
#define SERIAL_DRV_NAME_2 "usart2_drv"
|
||||
#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
|
||||
#define BSP_USING_USART3
|
||||
#define SERIAL_BUS_NAME_3 "usart3"
|
||||
#define SERIAL_DRV_NAME_3 "usart3_drv"
|
||||
#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
|
||||
#define BSP_USING_WDT
|
||||
#define WDT_BUS_NAME "wdt"
|
||||
#define WDT_DRIVER_NAME "wdt_drv"
|
||||
#define WDT_DEVICE_NAME "wdt_dev"
|
||||
|
||||
/* config default board resources */
|
||||
|
||||
/* config board app name */
|
||||
|
||||
#define BOARD_APP_NAME "/XiUOS_cortex-m4-emulator_app.bin"
|
||||
|
||||
/* config board service table */
|
||||
|
||||
#define SERVICE_TABLE_ADDRESS 0x20000000
|
||||
|
||||
/* config hardware resources for connection */
|
||||
|
||||
/* Hardware feature */
|
||||
|
||||
#define RESOURCES_SERIAL
|
||||
#define SERIAL_USING_DMA
|
||||
#define SERIAL_RB_BUFSZ 128
|
||||
#define RESOURCES_PIN
|
||||
#define RESOURCES_WDT
|
||||
|
||||
/* Kernel feature */
|
||||
|
||||
/* separate compile(choose none for compile once) */
|
||||
|
||||
#define APP_STARTUP_FROM_FLASH
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
#define MEM_ALIGN_SIZE 8
|
||||
#define MM_PAGE_SIZE 4096
|
||||
|
||||
/* Using small memory allocator */
|
||||
|
||||
#define KERNEL_SMALL_MEM_ALLOC
|
||||
#define SMALL_NUMBER_32B 64
|
||||
#define SMALL_NUMBER_64B 32
|
||||
|
||||
/* Task feature */
|
||||
|
||||
#define USER_APPLICATION
|
||||
|
||||
/* Inter-Task communication */
|
||||
|
||||
#define KERNEL_SEMAPHORE
|
||||
#define KERNEL_MUTEX
|
||||
#define KERNEL_EVENT
|
||||
#define KERNEL_MESSAGEQUEUE
|
||||
#define KERNEL_SOFTTIMER
|
||||
#define SCHED_POLICY_RR_REMAINSLICE
|
||||
#define KTASK_PRIORITY_32
|
||||
#define KTASK_PRIORITY_MAX 32
|
||||
#define TICK_PER_SECOND 1000
|
||||
#define KERNEL_STACK_OVERFLOW_CHECK
|
||||
#define IDLE_KTASK_STACKSIZE 256
|
||||
#define ZOMBIE_KTASK_STACKSIZE 2048
|
||||
|
||||
/* Kernel Console */
|
||||
|
||||
#define KERNEL_CONSOLE
|
||||
#define KERNEL_BANNER
|
||||
#define KERNEL_CONSOLEBUF_SIZE 128
|
||||
|
||||
/* Kernel Hook */
|
||||
|
||||
|
||||
/* Command shell */
|
||||
|
||||
#define TOOL_SHELL
|
||||
#define SHELL_ENTER_CR
|
||||
#define SHELL_ENTER_LF
|
||||
#define SHELL_ENTER_CR_AND_LF
|
||||
|
||||
/* Set shell user control */
|
||||
|
||||
#define SHELL_DEFAULT_USER "letter"
|
||||
#define SHELL_DEFAULT_USER_PASSWORD ""
|
||||
#define SHELL_LOCK_TIMEOUT 10000
|
||||
|
||||
/* Set shell config param */
|
||||
|
||||
#define SHELL_TASK_STACK_SIZE 4096
|
||||
#define SHELL_TASK_PRIORITY 20
|
||||
#define SHELL_MAX_NUMBER 5
|
||||
#define SHELL_PARAMETER_MAX_NUMBER 8
|
||||
#define SHELL_HISTORY_MAX_NUMBER 5
|
||||
#define SHELL_PRINT_BUFFER 128
|
||||
#define SHELL_HELP_SHOW_PERMISSION
|
||||
|
||||
/* Kernel data structure Manage */
|
||||
|
||||
#define KERNEL_QUEUEMANAGE
|
||||
#define KERNEL_WORKQUEUE
|
||||
#define WORKQUEUE_KTASK_STACKSIZE 512
|
||||
#define WORKQUEUE_KTASK_PRIORITY 23
|
||||
#define QUEUE_MAX 16
|
||||
#define KERNEL_WAITQUEUE
|
||||
#define KERNEL_DATAQUEUE
|
||||
|
||||
/* Kernel components init */
|
||||
|
||||
#define KERNEL_COMPONENTS_INIT
|
||||
#define ENV_INIT_KTASK_STACK_SIZE 8192
|
||||
#define KERNEL_USER_MAIN
|
||||
#define NAME_NUM_MAX 32
|
||||
|
||||
/* hash table config */
|
||||
|
||||
#define ID_HTABLE_SIZE 16
|
||||
#define ID_NUM_MAX 128
|
||||
|
||||
/* File system */
|
||||
|
||||
#define FS_VFS
|
||||
#define VFS_USING_WORKDIR
|
||||
#define FS_VFS_DEVFS
|
||||
#define FS_VFS_FATFS
|
||||
|
||||
/* APP Framework */
|
||||
|
||||
/* Perception */
|
||||
|
||||
|
||||
/* connection */
|
||||
|
||||
|
||||
/* Intelligence */
|
||||
|
||||
|
||||
/* Control */
|
||||
|
||||
/* Lib */
|
||||
|
||||
#define LIB
|
||||
#define LIB_POSIX
|
||||
|
||||
/* C++ features */
|
||||
|
||||
#define LIB_NEWLIB
|
||||
|
||||
/* Security */
|
||||
|
||||
|
||||
/* Applications */
|
||||
|
||||
|
||||
/* config stack size and priority of main task */
|
||||
|
||||
#define MAIN_KTASK_STACK_SIZE 2048
|
||||
#define MAIN_KTASK_PRIORITY 10
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,185 @@
|
|||
#ifndef XS_CONFIG_H__
|
||||
#define XS_CONFIG_H__
|
||||
|
||||
/* Automatically generated file; DO NOT EDIT. */
|
||||
/* XiUOS Project Configuration */
|
||||
|
||||
#define BOARD_CORTEX_M4_EVB
|
||||
#define ARCH_ARM
|
||||
|
||||
/* stm32f407-st-discovery feature */
|
||||
|
||||
#define BSP_USING_DMA
|
||||
#define BSP_USING_GPIO
|
||||
#define PIN_BUS_NAME "pin"
|
||||
#define PIN_DRIVER_NAME "pin_drv"
|
||||
#define PIN_DEVICE_NAME "pin_dev"
|
||||
#define BSP_USING_UART
|
||||
#define BSP_USING_USART1
|
||||
#define SERIAL_BUS_NAME_1 "usart1"
|
||||
#define SERIAL_DRV_NAME_1 "usart1_drv"
|
||||
#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
|
||||
#define BSP_USING_USART2
|
||||
#define SERIAL_BUS_NAME_2 "usart2"
|
||||
#define SERIAL_DRV_NAME_2 "usart2_drv"
|
||||
#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
|
||||
#define BSP_USING_USART3
|
||||
#define SERIAL_BUS_NAME_3 "usart3"
|
||||
#define SERIAL_DRV_NAME_3 "usart3_drv"
|
||||
#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
|
||||
#define BSP_USING_WDT
|
||||
#define WDT_BUS_NAME "wdt"
|
||||
#define WDT_DRIVER_NAME "wdt_drv"
|
||||
#define WDT_DEVICE_NAME "wdt_dev"
|
||||
|
||||
/* config default board resources */
|
||||
|
||||
/* config board app name */
|
||||
|
||||
#define BOARD_APP_NAME "/XiUOS_cortex-m4-emulator_app.bin"
|
||||
|
||||
/* config board service table */
|
||||
|
||||
#define SERVICE_TABLE_ADDRESS 0x20000000
|
||||
|
||||
/* config hardware resources for connection */
|
||||
|
||||
/* Hardware feature */
|
||||
|
||||
#define RESOURCES_SERIAL
|
||||
#define SERIAL_USING_DMA
|
||||
#define SERIAL_RB_BUFSZ 128
|
||||
#define RESOURCES_PIN
|
||||
#define RESOURCES_WDT
|
||||
|
||||
/* Kernel feature */
|
||||
|
||||
/* separate compile(choose none for compile once) */
|
||||
|
||||
#define APP_STARTUP_FROM_FLASH
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
#define MEM_ALIGN_SIZE 8
|
||||
#define MM_PAGE_SIZE 4096
|
||||
|
||||
/* Using small memory allocator */
|
||||
|
||||
#define KERNEL_SMALL_MEM_ALLOC
|
||||
#define SMALL_NUMBER_32B 64
|
||||
#define SMALL_NUMBER_64B 32
|
||||
|
||||
/* Task feature */
|
||||
|
||||
#define USER_APPLICATION
|
||||
|
||||
/* Inter-Task communication */
|
||||
|
||||
#define KERNEL_SEMAPHORE
|
||||
#define KERNEL_MUTEX
|
||||
#define KERNEL_EVENT
|
||||
#define KERNEL_MESSAGEQUEUE
|
||||
#define KERNEL_SOFTTIMER
|
||||
#define SCHED_POLICY_RR_REMAINSLICE
|
||||
#define KTASK_PRIORITY_32
|
||||
#define KTASK_PRIORITY_MAX 32
|
||||
#define TICK_PER_SECOND 1000
|
||||
#define KERNEL_STACK_OVERFLOW_CHECK
|
||||
#define IDLE_KTASK_STACKSIZE 256
|
||||
#define ZOMBIE_KTASK_STACKSIZE 2048
|
||||
|
||||
/* Kernel Console */
|
||||
|
||||
#define KERNEL_CONSOLE
|
||||
#define KERNEL_BANNER
|
||||
#define KERNEL_CONSOLEBUF_SIZE 128
|
||||
|
||||
/* Kernel Hook */
|
||||
|
||||
|
||||
/* Command shell */
|
||||
|
||||
#define TOOL_SHELL
|
||||
#define SHELL_ENTER_CR
|
||||
#define SHELL_ENTER_LF
|
||||
#define SHELL_ENTER_CR_AND_LF
|
||||
|
||||
/* Set shell user control */
|
||||
|
||||
#define SHELL_DEFAULT_USER "letter"
|
||||
#define SHELL_DEFAULT_USER_PASSWORD ""
|
||||
#define SHELL_LOCK_TIMEOUT 10000
|
||||
|
||||
/* Set shell config param */
|
||||
|
||||
#define SHELL_TASK_STACK_SIZE 4096
|
||||
#define SHELL_TASK_PRIORITY 20
|
||||
#define SHELL_MAX_NUMBER 5
|
||||
#define SHELL_PARAMETER_MAX_NUMBER 8
|
||||
#define SHELL_HISTORY_MAX_NUMBER 5
|
||||
#define SHELL_PRINT_BUFFER 128
|
||||
#define SHELL_HELP_SHOW_PERMISSION
|
||||
|
||||
/* Kernel data structure Manage */
|
||||
|
||||
#define KERNEL_QUEUEMANAGE
|
||||
#define KERNEL_WORKQUEUE
|
||||
#define WORKQUEUE_KTASK_STACKSIZE 512
|
||||
#define WORKQUEUE_KTASK_PRIORITY 23
|
||||
#define QUEUE_MAX 16
|
||||
#define KERNEL_WAITQUEUE
|
||||
#define KERNEL_DATAQUEUE
|
||||
|
||||
/* Kernel components init */
|
||||
|
||||
#define KERNEL_COMPONENTS_INIT
|
||||
#define ENV_INIT_KTASK_STACK_SIZE 8192
|
||||
#define KERNEL_USER_MAIN
|
||||
#define NAME_NUM_MAX 32
|
||||
|
||||
/* hash table config */
|
||||
|
||||
#define ID_HTABLE_SIZE 16
|
||||
#define ID_NUM_MAX 128
|
||||
|
||||
/* File system */
|
||||
|
||||
#define FS_VFS
|
||||
#define VFS_USING_WORKDIR
|
||||
#define FS_VFS_DEVFS
|
||||
#define FS_VFS_FATFS
|
||||
|
||||
/* APP Framework */
|
||||
|
||||
/* Perception */
|
||||
|
||||
|
||||
/* connection */
|
||||
|
||||
|
||||
/* Intelligence */
|
||||
|
||||
|
||||
/* Control */
|
||||
|
||||
/* Lib */
|
||||
|
||||
#define LIB
|
||||
#define LIB_POSIX
|
||||
|
||||
/* C++ features */
|
||||
|
||||
#define LIB_NEWLIB
|
||||
|
||||
/* Security */
|
||||
|
||||
|
||||
/* Applications */
|
||||
|
||||
|
||||
/* config stack size and priority of main task */
|
||||
|
||||
#define MAIN_KTASK_STACK_SIZE 2048
|
||||
#define MAIN_KTASK_PRIORITY 10
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,185 @@
|
|||
#ifndef XS_CONFIG_H__
|
||||
#define XS_CONFIG_H__
|
||||
|
||||
/* Automatically generated file; DO NOT EDIT. */
|
||||
/* XiUOS Project Configuration */
|
||||
|
||||
#define BOARD_CORTEX_M4_EVB
|
||||
#define ARCH_ARM
|
||||
|
||||
/* BOARD_CORTEX_M4_EVB feature */
|
||||
|
||||
#define BSP_USING_DMA
|
||||
#define BSP_USING_GPIO
|
||||
#define PIN_BUS_NAME "pin"
|
||||
#define PIN_DRIVER_NAME "pin_drv"
|
||||
#define PIN_DEVICE_NAME "pin_dev"
|
||||
#define BSP_USING_UART
|
||||
#define BSP_USING_USART1
|
||||
#define SERIAL_BUS_NAME_1 "usart1"
|
||||
#define SERIAL_DRV_NAME_1 "usart1_drv"
|
||||
#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
|
||||
#define BSP_USING_USART2
|
||||
#define SERIAL_BUS_NAME_2 "usart2"
|
||||
#define SERIAL_DRV_NAME_2 "usart2_drv"
|
||||
#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
|
||||
#define BSP_USING_USART3
|
||||
#define SERIAL_BUS_NAME_3 "usart3"
|
||||
#define SERIAL_DRV_NAME_3 "usart3_drv"
|
||||
#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
|
||||
#define BSP_USING_WDT
|
||||
#define WDT_BUS_NAME "wdt"
|
||||
#define WDT_DRIVER_NAME "wdt_drv"
|
||||
#define WDT_DEVICE_NAME "wdt_dev"
|
||||
|
||||
/* config default board resources */
|
||||
|
||||
/* config board app name */
|
||||
|
||||
#define BOARD_APP_NAME "/XiUOS_cortex-m4-emulator_app.bin"
|
||||
|
||||
/* config board service table */
|
||||
|
||||
#define SERVICE_TABLE_ADDRESS 0x20000000
|
||||
|
||||
/* config hardware resources for connection */
|
||||
|
||||
/* Hardware feature */
|
||||
|
||||
#define RESOURCES_SERIAL
|
||||
#define SERIAL_USING_DMA
|
||||
#define SERIAL_RB_BUFSZ 128
|
||||
#define RESOURCES_PIN
|
||||
#define RESOURCES_WDT
|
||||
|
||||
/* Kernel feature */
|
||||
|
||||
/* separate compile(choose none for compile once) */
|
||||
|
||||
#define APP_STARTUP_FROM_FLASH
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
#define MEM_ALIGN_SIZE 8
|
||||
#define MM_PAGE_SIZE 4096
|
||||
|
||||
/* Using small memory allocator */
|
||||
|
||||
#define KERNEL_SMALL_MEM_ALLOC
|
||||
#define SMALL_NUMBER_32B 64
|
||||
#define SMALL_NUMBER_64B 32
|
||||
|
||||
/* Task feature */
|
||||
|
||||
#define USER_APPLICATION
|
||||
|
||||
/* Inter-Task communication */
|
||||
|
||||
#define KERNEL_SEMAPHORE
|
||||
#define KERNEL_MUTEX
|
||||
#define KERNEL_EVENT
|
||||
#define KERNEL_MESSAGEQUEUE
|
||||
#define KERNEL_SOFTTIMER
|
||||
#define SCHED_POLICY_RR_REMAINSLICE
|
||||
#define KTASK_PRIORITY_32
|
||||
#define KTASK_PRIORITY_MAX 32
|
||||
#define TICK_PER_SECOND 1000
|
||||
#define KERNEL_STACK_OVERFLOW_CHECK
|
||||
#define IDLE_KTASK_STACKSIZE 256
|
||||
#define ZOMBIE_KTASK_STACKSIZE 2048
|
||||
|
||||
/* Kernel Console */
|
||||
|
||||
#define KERNEL_CONSOLE
|
||||
#define KERNEL_BANNER
|
||||
#define KERNEL_CONSOLEBUF_SIZE 128
|
||||
|
||||
/* Kernel Hook */
|
||||
|
||||
|
||||
/* Command shell */
|
||||
|
||||
#define TOOL_SHELL
|
||||
#define SHELL_ENTER_CR
|
||||
#define SHELL_ENTER_LF
|
||||
#define SHELL_ENTER_CR_AND_LF
|
||||
|
||||
/* Set shell user control */
|
||||
|
||||
#define SHELL_DEFAULT_USER "letter"
|
||||
#define SHELL_DEFAULT_USER_PASSWORD ""
|
||||
#define SHELL_LOCK_TIMEOUT 10000
|
||||
|
||||
/* Set shell config param */
|
||||
|
||||
#define SHELL_TASK_STACK_SIZE 4096
|
||||
#define SHELL_TASK_PRIORITY 20
|
||||
#define SHELL_MAX_NUMBER 5
|
||||
#define SHELL_PARAMETER_MAX_NUMBER 8
|
||||
#define SHELL_HISTORY_MAX_NUMBER 5
|
||||
#define SHELL_PRINT_BUFFER 128
|
||||
#define SHELL_HELP_SHOW_PERMISSION
|
||||
|
||||
/* Kernel data structure Manage */
|
||||
|
||||
#define KERNEL_QUEUEMANAGE
|
||||
#define KERNEL_WORKQUEUE
|
||||
#define WORKQUEUE_KTASK_STACKSIZE 512
|
||||
#define WORKQUEUE_KTASK_PRIORITY 23
|
||||
#define QUEUE_MAX 16
|
||||
#define KERNEL_WAITQUEUE
|
||||
#define KERNEL_DATAQUEUE
|
||||
|
||||
/* Kernel components init */
|
||||
|
||||
#define KERNEL_COMPONENTS_INIT
|
||||
#define ENV_INIT_KTASK_STACK_SIZE 8192
|
||||
#define KERNEL_USER_MAIN
|
||||
#define NAME_NUM_MAX 32
|
||||
|
||||
/* hash table config */
|
||||
|
||||
#define ID_HTABLE_SIZE 16
|
||||
#define ID_NUM_MAX 128
|
||||
|
||||
/* File system */
|
||||
|
||||
#define FS_VFS
|
||||
#define VFS_USING_WORKDIR
|
||||
#define FS_VFS_DEVFS
|
||||
#define FS_VFS_FATFS
|
||||
|
||||
/* APP Framework */
|
||||
|
||||
/* Perception */
|
||||
|
||||
|
||||
/* connection */
|
||||
|
||||
|
||||
/* Intelligence */
|
||||
|
||||
|
||||
/* Control */
|
||||
|
||||
/* Lib */
|
||||
|
||||
#define LIB
|
||||
#define LIB_POSIX
|
||||
|
||||
/* C++ features */
|
||||
|
||||
#define LIB_NEWLIB
|
||||
|
||||
/* Security */
|
||||
|
||||
|
||||
/* Applications */
|
||||
|
||||
|
||||
/* config stack size and priority of main task */
|
||||
|
||||
#define MAIN_KTASK_STACK_SIZE 2048
|
||||
#define MAIN_KTASK_PRIORITY 10
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,185 @@
|
|||
#ifndef XS_CONFIG_H__
|
||||
#define XS_CONFIG_H__
|
||||
|
||||
/* Automatically generated file; DO NOT EDIT. */
|
||||
/* XiUOS Project Configuration */
|
||||
|
||||
#define BOARD_CORTEX_M4_EVB
|
||||
#define ARCH_ARM
|
||||
|
||||
/* BOARD_CORTEX_M4_EVB feature */
|
||||
|
||||
#define BSP_USING_DMA
|
||||
#define BSP_USING_GPIO
|
||||
#define PIN_BUS_NAME "pin"
|
||||
#define PIN_DRIVER_NAME "pin_drv"
|
||||
#define PIN_DEVICE_NAME "pin_dev"
|
||||
#define BSP_USING_UART
|
||||
#define BSP_USING_USART1
|
||||
#define SERIAL_BUS_NAME_1 "usart1"
|
||||
#define SERIAL_DRV_NAME_1 "usart1_drv"
|
||||
#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
|
||||
#define BSP_USING_USART2
|
||||
#define SERIAL_BUS_NAME_2 "usart2"
|
||||
#define SERIAL_DRV_NAME_2 "usart2_drv"
|
||||
#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
|
||||
#define BSP_USING_USART3
|
||||
#define SERIAL_BUS_NAME_3 "usart3"
|
||||
#define SERIAL_DRV_NAME_3 "usart3_drv"
|
||||
#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
|
||||
#define BSP_USING_WDT
|
||||
#define WDT_BUS_NAME "wdt"
|
||||
#define WDT_DRIVER_NAME "wdt_drv"
|
||||
#define WDT_DEVICE_NAME "wdt_dev"
|
||||
|
||||
/* config default board resources */
|
||||
|
||||
/* config board app name */
|
||||
|
||||
#define BOARD_APP_NAME "/XiUOS_cortex-m4-emulator_app.bin"
|
||||
|
||||
/* config board service table */
|
||||
|
||||
#define SERVICE_TABLE_ADDRESS 0x20000000
|
||||
|
||||
/* config hardware resources for connection */
|
||||
|
||||
/* Hardware feature */
|
||||
|
||||
#define RESOURCES_SERIAL
|
||||
#define SERIAL_USING_DMA
|
||||
#define SERIAL_RB_BUFSZ 128
|
||||
#define RESOURCES_PIN
|
||||
#define RESOURCES_WDT
|
||||
|
||||
/* Kernel feature */
|
||||
|
||||
/* separate compile(choose none for compile once) */
|
||||
|
||||
#define APP_STARTUP_FROM_FLASH
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
#define MEM_ALIGN_SIZE 8
|
||||
#define MM_PAGE_SIZE 4096
|
||||
|
||||
/* Using small memory allocator */
|
||||
|
||||
#define KERNEL_SMALL_MEM_ALLOC
|
||||
#define SMALL_NUMBER_32B 64
|
||||
#define SMALL_NUMBER_64B 32
|
||||
|
||||
/* Task feature */
|
||||
|
||||
#define USER_APPLICATION
|
||||
|
||||
/* Inter-Task communication */
|
||||
|
||||
#define KERNEL_SEMAPHORE
|
||||
#define KERNEL_MUTEX
|
||||
#define KERNEL_EVENT
|
||||
#define KERNEL_MESSAGEQUEUE
|
||||
#define KERNEL_SOFTTIMER
|
||||
#define SCHED_POLICY_RR_REMAINSLICE
|
||||
#define KTASK_PRIORITY_32
|
||||
#define KTASK_PRIORITY_MAX 32
|
||||
#define TICK_PER_SECOND 1000
|
||||
#define KERNEL_STACK_OVERFLOW_CHECK
|
||||
#define IDLE_KTASK_STACKSIZE 256
|
||||
#define ZOMBIE_KTASK_STACKSIZE 2048
|
||||
|
||||
/* Kernel Console */
|
||||
|
||||
#define KERNEL_CONSOLE
|
||||
#define KERNEL_BANNER
|
||||
#define KERNEL_CONSOLEBUF_SIZE 128
|
||||
|
||||
/* Kernel Hook */
|
||||
|
||||
|
||||
/* Command shell */
|
||||
|
||||
#define TOOL_SHELL
|
||||
#define SHELL_ENTER_CR
|
||||
#define SHELL_ENTER_LF
|
||||
#define SHELL_ENTER_CR_AND_LF
|
||||
|
||||
/* Set shell user control */
|
||||
|
||||
#define SHELL_DEFAULT_USER "letter"
|
||||
#define SHELL_DEFAULT_USER_PASSWORD ""
|
||||
#define SHELL_LOCK_TIMEOUT 10000
|
||||
|
||||
/* Set shell config param */
|
||||
|
||||
#define SHELL_TASK_STACK_SIZE 4096
|
||||
#define SHELL_TASK_PRIORITY 20
|
||||
#define SHELL_MAX_NUMBER 5
|
||||
#define SHELL_PARAMETER_MAX_NUMBER 8
|
||||
#define SHELL_HISTORY_MAX_NUMBER 5
|
||||
#define SHELL_PRINT_BUFFER 128
|
||||
#define SHELL_HELP_SHOW_PERMISSION
|
||||
|
||||
/* Kernel data structure Manage */
|
||||
|
||||
#define KERNEL_QUEUEMANAGE
|
||||
#define KERNEL_WORKQUEUE
|
||||
#define WORKQUEUE_KTASK_STACKSIZE 512
|
||||
#define WORKQUEUE_KTASK_PRIORITY 23
|
||||
#define QUEUE_MAX 16
|
||||
#define KERNEL_WAITQUEUE
|
||||
#define KERNEL_DATAQUEUE
|
||||
|
||||
/* Kernel components init */
|
||||
|
||||
#define KERNEL_COMPONENTS_INIT
|
||||
#define ENV_INIT_KTASK_STACK_SIZE 8192
|
||||
#define KERNEL_USER_MAIN
|
||||
#define NAME_NUM_MAX 32
|
||||
|
||||
/* hash table config */
|
||||
|
||||
#define ID_HTABLE_SIZE 16
|
||||
#define ID_NUM_MAX 128
|
||||
|
||||
/* File system */
|
||||
|
||||
#define FS_VFS
|
||||
#define VFS_USING_WORKDIR
|
||||
#define FS_VFS_DEVFS
|
||||
#define FS_VFS_FATFS
|
||||
|
||||
/* APP Framework */
|
||||
|
||||
/* Perception */
|
||||
|
||||
|
||||
/* connection */
|
||||
|
||||
|
||||
/* Intelligence */
|
||||
|
||||
|
||||
/* Control */
|
||||
|
||||
/* Lib */
|
||||
|
||||
#define LIB
|
||||
#define LIB_POSIX
|
||||
|
||||
/* C++ features */
|
||||
|
||||
#define LIB_NEWLIB
|
||||
|
||||
/* Security */
|
||||
|
||||
|
||||
/* Applications */
|
||||
|
||||
|
||||
/* config stack size and priority of main task */
|
||||
|
||||
#define MAIN_KTASK_STACK_SIZE 2048
|
||||
#define MAIN_KTASK_PRIORITY 10
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,185 @@
|
|||
#ifndef XS_CONFIG_H__
|
||||
#define XS_CONFIG_H__
|
||||
|
||||
/* Automatically generated file; DO NOT EDIT. */
|
||||
/* XiUOS Project Configuration */
|
||||
|
||||
#define BOARD_CORTEX_M4_EVB
|
||||
#define ARCH_ARM
|
||||
|
||||
/* BOARD_CORTEX_M4_EVB feature */
|
||||
|
||||
#define BSP_USING_DMA
|
||||
#define BSP_USING_GPIO
|
||||
#define PIN_BUS_NAME "pin"
|
||||
#define PIN_DRIVER_NAME "pin_drv"
|
||||
#define PIN_DEVICE_NAME "pin_dev"
|
||||
#define BSP_USING_UART
|
||||
#define BSP_USING_USART1
|
||||
#define SERIAL_BUS_NAME_1 "usart1"
|
||||
#define SERIAL_DRV_NAME_1 "usart1_drv"
|
||||
#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
|
||||
#define BSP_USING_USART2
|
||||
#define SERIAL_BUS_NAME_2 "usart2"
|
||||
#define SERIAL_DRV_NAME_2 "usart2_drv"
|
||||
#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
|
||||
#define BSP_USING_USART3
|
||||
#define SERIAL_BUS_NAME_3 "usart3"
|
||||
#define SERIAL_DRV_NAME_3 "usart3_drv"
|
||||
#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
|
||||
#define BSP_USING_WDT
|
||||
#define WDT_BUS_NAME "wdt"
|
||||
#define WDT_DRIVER_NAME "wdt_drv"
|
||||
#define WDT_DEVICE_NAME "wdt_dev"
|
||||
|
||||
/* config default board resources */
|
||||
|
||||
/* config board app name */
|
||||
|
||||
#define BOARD_APP_NAME "/XiUOS_cortex-m4-emulator_app.bin"
|
||||
|
||||
/* config board service table */
|
||||
|
||||
#define SERVICE_TABLE_ADDRESS 0x20000000
|
||||
|
||||
/* config hardware resources for connection */
|
||||
|
||||
/* Hardware feature */
|
||||
|
||||
#define RESOURCES_SERIAL
|
||||
#define SERIAL_USING_DMA
|
||||
#define SERIAL_RB_BUFSZ 128
|
||||
#define RESOURCES_PIN
|
||||
#define RESOURCES_WDT
|
||||
|
||||
/* Kernel feature */
|
||||
|
||||
/* separate compile(choose none for compile once) */
|
||||
|
||||
#define APP_STARTUP_FROM_FLASH
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
#define MEM_ALIGN_SIZE 8
|
||||
#define MM_PAGE_SIZE 4096
|
||||
|
||||
/* Using small memory allocator */
|
||||
|
||||
#define KERNEL_SMALL_MEM_ALLOC
|
||||
#define SMALL_NUMBER_32B 64
|
||||
#define SMALL_NUMBER_64B 32
|
||||
|
||||
/* Task feature */
|
||||
|
||||
#define USER_APPLICATION
|
||||
|
||||
/* Inter-Task communication */
|
||||
|
||||
#define KERNEL_SEMAPHORE
|
||||
#define KERNEL_MUTEX
|
||||
#define KERNEL_EVENT
|
||||
#define KERNEL_MESSAGEQUEUE
|
||||
#define KERNEL_SOFTTIMER
|
||||
#define SCHED_POLICY_RR_REMAINSLICE
|
||||
#define KTASK_PRIORITY_32
|
||||
#define KTASK_PRIORITY_MAX 32
|
||||
#define TICK_PER_SECOND 1000
|
||||
#define KERNEL_STACK_OVERFLOW_CHECK
|
||||
#define IDLE_KTASK_STACKSIZE 256
|
||||
#define ZOMBIE_KTASK_STACKSIZE 2048
|
||||
|
||||
/* Kernel Console */
|
||||
|
||||
#define KERNEL_CONSOLE
|
||||
#define KERNEL_BANNER
|
||||
#define KERNEL_CONSOLEBUF_SIZE 128
|
||||
|
||||
/* Kernel Hook */
|
||||
|
||||
|
||||
/* Command shell */
|
||||
|
||||
#define TOOL_SHELL
|
||||
#define SHELL_ENTER_CR
|
||||
#define SHELL_ENTER_LF
|
||||
#define SHELL_ENTER_CR_AND_LF
|
||||
|
||||
/* Set shell user control */
|
||||
|
||||
#define SHELL_DEFAULT_USER "letter"
|
||||
#define SHELL_DEFAULT_USER_PASSWORD ""
|
||||
#define SHELL_LOCK_TIMEOUT 10000
|
||||
|
||||
/* Set shell config param */
|
||||
|
||||
#define SHELL_TASK_STACK_SIZE 4096
|
||||
#define SHELL_TASK_PRIORITY 20
|
||||
#define SHELL_MAX_NUMBER 5
|
||||
#define SHELL_PARAMETER_MAX_NUMBER 8
|
||||
#define SHELL_HISTORY_MAX_NUMBER 5
|
||||
#define SHELL_PRINT_BUFFER 128
|
||||
#define SHELL_HELP_SHOW_PERMISSION
|
||||
|
||||
/* Kernel data structure Manage */
|
||||
|
||||
#define KERNEL_QUEUEMANAGE
|
||||
#define KERNEL_WORKQUEUE
|
||||
#define WORKQUEUE_KTASK_STACKSIZE 512
|
||||
#define WORKQUEUE_KTASK_PRIORITY 23
|
||||
#define QUEUE_MAX 16
|
||||
#define KERNEL_WAITQUEUE
|
||||
#define KERNEL_DATAQUEUE
|
||||
|
||||
/* Kernel components init */
|
||||
|
||||
#define KERNEL_COMPONENTS_INIT
|
||||
#define ENV_INIT_KTASK_STACK_SIZE 8192
|
||||
#define KERNEL_USER_MAIN
|
||||
#define NAME_NUM_MAX 32
|
||||
|
||||
/* hash table config */
|
||||
|
||||
#define ID_HTABLE_SIZE 16
|
||||
#define ID_NUM_MAX 128
|
||||
|
||||
/* File system */
|
||||
|
||||
#define FS_VFS
|
||||
#define VFS_USING_WORKDIR
|
||||
#define FS_VFS_DEVFS
|
||||
#define FS_VFS_FATFS
|
||||
|
||||
/* APP Framework */
|
||||
|
||||
/* Perception */
|
||||
|
||||
|
||||
/* connection */
|
||||
|
||||
|
||||
/* Intelligence */
|
||||
|
||||
|
||||
/* Control */
|
||||
|
||||
/* Lib */
|
||||
|
||||
#define LIB
|
||||
#define LIB_POSIX
|
||||
|
||||
/* C++ features */
|
||||
|
||||
#define LIB_NEWLIB
|
||||
|
||||
/* Security */
|
||||
|
||||
|
||||
/* Applications */
|
||||
|
||||
|
||||
/* config stack size and priority of main task */
|
||||
|
||||
#define MAIN_KTASK_STACK_SIZE 2048
|
||||
#define MAIN_KTASK_PRIORITY 10
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,185 @@
|
|||
#ifndef XS_CONFIG_H__
|
||||
#define XS_CONFIG_H__
|
||||
|
||||
/* Automatically generated file; DO NOT EDIT. */
|
||||
/* XiUOS Project Configuration */
|
||||
|
||||
#define BOARD_CORTEX_M4_EVB
|
||||
#define ARCH_ARM
|
||||
|
||||
/* BOARD_CORTEX_M4_EVB feature */
|
||||
|
||||
#define BSP_USING_DMA
|
||||
#define BSP_USING_GPIO
|
||||
#define PIN_BUS_NAME "pin"
|
||||
#define PIN_DRIVER_NAME "pin_drv"
|
||||
#define PIN_DEVICE_NAME "pin_dev"
|
||||
#define BSP_USING_UART
|
||||
#define BSP_USING_USART1
|
||||
#define SERIAL_BUS_NAME_1 "usart1"
|
||||
#define SERIAL_DRV_NAME_1 "usart1_drv"
|
||||
#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
|
||||
#define BSP_USING_USART2
|
||||
#define SERIAL_BUS_NAME_2 "usart2"
|
||||
#define SERIAL_DRV_NAME_2 "usart2_drv"
|
||||
#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
|
||||
#define BSP_USING_USART3
|
||||
#define SERIAL_BUS_NAME_3 "usart3"
|
||||
#define SERIAL_DRV_NAME_3 "usart3_drv"
|
||||
#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
|
||||
#define BSP_USING_WDT
|
||||
#define WDT_BUS_NAME "wdt"
|
||||
#define WDT_DRIVER_NAME "wdt_drv"
|
||||
#define WDT_DEVICE_NAME "wdt_dev"
|
||||
|
||||
/* config default board resources */
|
||||
|
||||
/* config board app name */
|
||||
|
||||
#define BOARD_APP_NAME "/XiUOS_cortex-m4-emulator_app.bin"
|
||||
|
||||
/* config board service table */
|
||||
|
||||
#define SERVICE_TABLE_ADDRESS 0x20000000
|
||||
|
||||
/* config hardware resources for connection */
|
||||
|
||||
/* Hardware feature */
|
||||
|
||||
#define RESOURCES_SERIAL
|
||||
#define SERIAL_USING_DMA
|
||||
#define SERIAL_RB_BUFSZ 128
|
||||
#define RESOURCES_PIN
|
||||
#define RESOURCES_WDT
|
||||
|
||||
/* Kernel feature */
|
||||
|
||||
/* separate compile(choose none for compile once) */
|
||||
|
||||
#define APP_STARTUP_FROM_FLASH
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
#define MEM_ALIGN_SIZE 8
|
||||
#define MM_PAGE_SIZE 4096
|
||||
|
||||
/* Using small memory allocator */
|
||||
|
||||
#define KERNEL_SMALL_MEM_ALLOC
|
||||
#define SMALL_NUMBER_32B 64
|
||||
#define SMALL_NUMBER_64B 32
|
||||
|
||||
/* Task feature */
|
||||
|
||||
#define USER_APPLICATION
|
||||
|
||||
/* Inter-Task communication */
|
||||
|
||||
#define KERNEL_SEMAPHORE
|
||||
#define KERNEL_MUTEX
|
||||
#define KERNEL_EVENT
|
||||
#define KERNEL_MESSAGEQUEUE
|
||||
#define KERNEL_SOFTTIMER
|
||||
#define SCHED_POLICY_RR_REMAINSLICE
|
||||
#define KTASK_PRIORITY_32
|
||||
#define KTASK_PRIORITY_MAX 32
|
||||
#define TICK_PER_SECOND 1000
|
||||
#define KERNEL_STACK_OVERFLOW_CHECK
|
||||
#define IDLE_KTASK_STACKSIZE 256
|
||||
#define ZOMBIE_KTASK_STACKSIZE 2048
|
||||
|
||||
/* Kernel Console */
|
||||
|
||||
#define KERNEL_CONSOLE
|
||||
#define KERNEL_BANNER
|
||||
#define KERNEL_CONSOLEBUF_SIZE 128
|
||||
|
||||
/* Kernel Hook */
|
||||
|
||||
|
||||
/* Command shell */
|
||||
|
||||
#define TOOL_SHELL
|
||||
#define SHELL_ENTER_CR
|
||||
#define SHELL_ENTER_LF
|
||||
#define SHELL_ENTER_CR_AND_LF
|
||||
|
||||
/* Set shell user control */
|
||||
|
||||
#define SHELL_DEFAULT_USER "letter"
|
||||
#define SHELL_DEFAULT_USER_PASSWORD ""
|
||||
#define SHELL_LOCK_TIMEOUT 10000
|
||||
|
||||
/* Set shell config param */
|
||||
|
||||
#define SHELL_TASK_STACK_SIZE 4096
|
||||
#define SHELL_TASK_PRIORITY 20
|
||||
#define SHELL_MAX_NUMBER 5
|
||||
#define SHELL_PARAMETER_MAX_NUMBER 8
|
||||
#define SHELL_HISTORY_MAX_NUMBER 5
|
||||
#define SHELL_PRINT_BUFFER 128
|
||||
#define SHELL_HELP_SHOW_PERMISSION
|
||||
|
||||
/* Kernel data structure Manage */
|
||||
|
||||
#define KERNEL_QUEUEMANAGE
|
||||
#define KERNEL_WORKQUEUE
|
||||
#define WORKQUEUE_KTASK_STACKSIZE 512
|
||||
#define WORKQUEUE_KTASK_PRIORITY 23
|
||||
#define QUEUE_MAX 16
|
||||
#define KERNEL_WAITQUEUE
|
||||
#define KERNEL_DATAQUEUE
|
||||
|
||||
/* Kernel components init */
|
||||
|
||||
#define KERNEL_COMPONENTS_INIT
|
||||
#define ENV_INIT_KTASK_STACK_SIZE 8192
|
||||
#define KERNEL_USER_MAIN
|
||||
#define NAME_NUM_MAX 32
|
||||
|
||||
/* hash table config */
|
||||
|
||||
#define ID_HTABLE_SIZE 16
|
||||
#define ID_NUM_MAX 128
|
||||
|
||||
/* File system */
|
||||
|
||||
#define FS_VFS
|
||||
#define VFS_USING_WORKDIR
|
||||
#define FS_VFS_DEVFS
|
||||
#define FS_VFS_FATFS
|
||||
|
||||
/* APP Framework */
|
||||
|
||||
/* Perception */
|
||||
|
||||
|
||||
/* connection */
|
||||
|
||||
|
||||
/* Intelligence */
|
||||
|
||||
|
||||
/* Control */
|
||||
|
||||
/* Lib */
|
||||
|
||||
#define LIB
|
||||
#define LIB_POSIX
|
||||
|
||||
/* C++ features */
|
||||
|
||||
#define LIB_NEWLIB
|
||||
|
||||
/* Security */
|
||||
|
||||
|
||||
/* Applications */
|
||||
|
||||
|
||||
/* config stack size and priority of main task */
|
||||
|
||||
#define MAIN_KTASK_STACK_SIZE 2048
|
||||
#define MAIN_KTASK_PRIORITY 10
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,185 @@
|
|||
#ifndef XS_CONFIG_H__
|
||||
#define XS_CONFIG_H__
|
||||
|
||||
/* Automatically generated file; DO NOT EDIT. */
|
||||
/* XiUOS Project Configuration */
|
||||
|
||||
#define BOARD_CORTEX_M4_EVB
|
||||
#define ARCH_ARM
|
||||
|
||||
/* BOARD_CORTEX_M4_EVB feature */
|
||||
|
||||
#define BSP_USING_DMA
|
||||
#define BSP_USING_GPIO
|
||||
#define PIN_BUS_NAME "pin"
|
||||
#define PIN_DRIVER_NAME "pin_drv"
|
||||
#define PIN_DEVICE_NAME "pin_dev"
|
||||
#define BSP_USING_UART
|
||||
#define BSP_USING_USART1
|
||||
#define SERIAL_BUS_NAME_1 "usart1"
|
||||
#define SERIAL_DRV_NAME_1 "usart1_drv"
|
||||
#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
|
||||
#define BSP_USING_USART2
|
||||
#define SERIAL_BUS_NAME_2 "usart2"
|
||||
#define SERIAL_DRV_NAME_2 "usart2_drv"
|
||||
#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
|
||||
#define BSP_USING_USART3
|
||||
#define SERIAL_BUS_NAME_3 "usart3"
|
||||
#define SERIAL_DRV_NAME_3 "usart3_drv"
|
||||
#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
|
||||
#define BSP_USING_WDT
|
||||
#define WDT_BUS_NAME "wdt"
|
||||
#define WDT_DRIVER_NAME "wdt_drv"
|
||||
#define WDT_DEVICE_NAME "wdt_dev"
|
||||
|
||||
/* config default board resources */
|
||||
|
||||
/* config board app name */
|
||||
|
||||
#define BOARD_APP_NAME "/XiUOS_cortex-m4-emulator_app.bin"
|
||||
|
||||
/* config board service table */
|
||||
|
||||
#define SERVICE_TABLE_ADDRESS 0x20000000
|
||||
|
||||
/* config hardware resources for connection */
|
||||
|
||||
/* Hardware feature */
|
||||
|
||||
#define RESOURCES_SERIAL
|
||||
#define SERIAL_USING_DMA
|
||||
#define SERIAL_RB_BUFSZ 128
|
||||
#define RESOURCES_PIN
|
||||
#define RESOURCES_WDT
|
||||
|
||||
/* Kernel feature */
|
||||
|
||||
/* separate compile(choose none for compile once) */
|
||||
|
||||
#define APP_STARTUP_FROM_FLASH
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
#define MEM_ALIGN_SIZE 8
|
||||
#define MM_PAGE_SIZE 4096
|
||||
|
||||
/* Using small memory allocator */
|
||||
|
||||
#define KERNEL_SMALL_MEM_ALLOC
|
||||
#define SMALL_NUMBER_32B 64
|
||||
#define SMALL_NUMBER_64B 32
|
||||
|
||||
/* Task feature */
|
||||
|
||||
#define USER_APPLICATION
|
||||
|
||||
/* Inter-Task communication */
|
||||
|
||||
#define KERNEL_SEMAPHORE
|
||||
#define KERNEL_MUTEX
|
||||
#define KERNEL_EVENT
|
||||
#define KERNEL_MESSAGEQUEUE
|
||||
#define KERNEL_SOFTTIMER
|
||||
#define SCHED_POLICY_RR_REMAINSLICE
|
||||
#define KTASK_PRIORITY_32
|
||||
#define KTASK_PRIORITY_MAX 32
|
||||
#define TICK_PER_SECOND 1000
|
||||
#define KERNEL_STACK_OVERFLOW_CHECK
|
||||
#define IDLE_KTASK_STACKSIZE 256
|
||||
#define ZOMBIE_KTASK_STACKSIZE 2048
|
||||
|
||||
/* Kernel Console */
|
||||
|
||||
#define KERNEL_CONSOLE
|
||||
#define KERNEL_BANNER
|
||||
#define KERNEL_CONSOLEBUF_SIZE 128
|
||||
|
||||
/* Kernel Hook */
|
||||
|
||||
|
||||
/* Command shell */
|
||||
|
||||
#define TOOL_SHELL
|
||||
#define SHELL_ENTER_CR
|
||||
#define SHELL_ENTER_LF
|
||||
#define SHELL_ENTER_CR_AND_LF
|
||||
|
||||
/* Set shell user control */
|
||||
|
||||
#define SHELL_DEFAULT_USER "letter"
|
||||
#define SHELL_DEFAULT_USER_PASSWORD ""
|
||||
#define SHELL_LOCK_TIMEOUT 10000
|
||||
|
||||
/* Set shell config param */
|
||||
|
||||
#define SHELL_TASK_STACK_SIZE 4096
|
||||
#define SHELL_TASK_PRIORITY 20
|
||||
#define SHELL_MAX_NUMBER 5
|
||||
#define SHELL_PARAMETER_MAX_NUMBER 8
|
||||
#define SHELL_HISTORY_MAX_NUMBER 5
|
||||
#define SHELL_PRINT_BUFFER 128
|
||||
#define SHELL_HELP_SHOW_PERMISSION
|
||||
|
||||
/* Kernel data structure Manage */
|
||||
|
||||
#define KERNEL_QUEUEMANAGE
|
||||
#define KERNEL_WORKQUEUE
|
||||
#define WORKQUEUE_KTASK_STACKSIZE 512
|
||||
#define WORKQUEUE_KTASK_PRIORITY 23
|
||||
#define QUEUE_MAX 16
|
||||
#define KERNEL_WAITQUEUE
|
||||
#define KERNEL_DATAQUEUE
|
||||
|
||||
/* Kernel components init */
|
||||
|
||||
#define KERNEL_COMPONENTS_INIT
|
||||
#define ENV_INIT_KTASK_STACK_SIZE 8192
|
||||
#define KERNEL_USER_MAIN
|
||||
#define NAME_NUM_MAX 32
|
||||
|
||||
/* hash table config */
|
||||
|
||||
#define ID_HTABLE_SIZE 16
|
||||
#define ID_NUM_MAX 128
|
||||
|
||||
/* File system */
|
||||
|
||||
#define FS_VFS
|
||||
#define VFS_USING_WORKDIR
|
||||
#define FS_VFS_DEVFS
|
||||
#define FS_VFS_FATFS
|
||||
|
||||
/* APP Framework */
|
||||
|
||||
/* Perception */
|
||||
|
||||
|
||||
/* connection */
|
||||
|
||||
|
||||
/* Intelligence */
|
||||
|
||||
|
||||
/* Control */
|
||||
|
||||
/* Lib */
|
||||
|
||||
#define LIB
|
||||
#define LIB_POSIX
|
||||
|
||||
/* C++ features */
|
||||
|
||||
#define LIB_NEWLIB
|
||||
|
||||
/* Security */
|
||||
|
||||
|
||||
/* Applications */
|
||||
|
||||
|
||||
/* config stack size and priority of main task */
|
||||
|
||||
#define MAIN_KTASK_STACK_SIZE 2048
|
||||
#define MAIN_KTASK_PRIORITY 10
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,185 @@
|
|||
#ifndef XS_CONFIG_H__
|
||||
#define XS_CONFIG_H__
|
||||
|
||||
/* Automatically generated file; DO NOT EDIT. */
|
||||
/* XiUOS Project Configuration */
|
||||
|
||||
#define BOARD_CORTEX_M4_EVB
|
||||
#define ARCH_ARM
|
||||
|
||||
/* BOARD_CORTEX_M4_EVB feature */
|
||||
|
||||
#define BSP_USING_DMA
|
||||
#define BSP_USING_GPIO
|
||||
#define PIN_BUS_NAME "pin"
|
||||
#define PIN_DRIVER_NAME "pin_drv"
|
||||
#define PIN_DEVICE_NAME "pin_dev"
|
||||
#define BSP_USING_UART
|
||||
#define BSP_USING_USART1
|
||||
#define SERIAL_BUS_NAME_1 "usart1"
|
||||
#define SERIAL_DRV_NAME_1 "usart1_drv"
|
||||
#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
|
||||
#define BSP_USING_USART2
|
||||
#define SERIAL_BUS_NAME_2 "usart2"
|
||||
#define SERIAL_DRV_NAME_2 "usart2_drv"
|
||||
#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
|
||||
#define BSP_USING_USART3
|
||||
#define SERIAL_BUS_NAME_3 "usart3"
|
||||
#define SERIAL_DRV_NAME_3 "usart3_drv"
|
||||
#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
|
||||
#define BSP_USING_WDT
|
||||
#define WDT_BUS_NAME "wdt"
|
||||
#define WDT_DRIVER_NAME "wdt_drv"
|
||||
#define WDT_DEVICE_NAME "wdt_dev"
|
||||
|
||||
/* config default board resources */
|
||||
|
||||
/* config board app name */
|
||||
|
||||
#define BOARD_APP_NAME "/XiUOS_cortex-m4-emulator_app.bin"
|
||||
|
||||
/* config board service table */
|
||||
|
||||
#define SERVICE_TABLE_ADDRESS 0x20000000
|
||||
|
||||
/* config hardware resources for connection */
|
||||
|
||||
/* Hardware feature */
|
||||
|
||||
#define RESOURCES_SERIAL
|
||||
#define SERIAL_USING_DMA
|
||||
#define SERIAL_RB_BUFSZ 128
|
||||
#define RESOURCES_PIN
|
||||
#define RESOURCES_WDT
|
||||
|
||||
/* Kernel feature */
|
||||
|
||||
/* separate compile(choose none for compile once) */
|
||||
|
||||
#define APP_STARTUP_FROM_FLASH
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
#define MEM_ALIGN_SIZE 8
|
||||
#define MM_PAGE_SIZE 4096
|
||||
|
||||
/* Using small memory allocator */
|
||||
|
||||
#define KERNEL_SMALL_MEM_ALLOC
|
||||
#define SMALL_NUMBER_32B 64
|
||||
#define SMALL_NUMBER_64B 32
|
||||
|
||||
/* Task feature */
|
||||
|
||||
#define USER_APPLICATION
|
||||
|
||||
/* Inter-Task communication */
|
||||
|
||||
#define KERNEL_SEMAPHORE
|
||||
#define KERNEL_MUTEX
|
||||
#define KERNEL_EVENT
|
||||
#define KERNEL_MESSAGEQUEUE
|
||||
#define KERNEL_SOFTTIMER
|
||||
#define SCHED_POLICY_RR_REMAINSLICE
|
||||
#define KTASK_PRIORITY_32
|
||||
#define KTASK_PRIORITY_MAX 32
|
||||
#define TICK_PER_SECOND 1000
|
||||
#define KERNEL_STACK_OVERFLOW_CHECK
|
||||
#define IDLE_KTASK_STACKSIZE 256
|
||||
#define ZOMBIE_KTASK_STACKSIZE 2048
|
||||
|
||||
/* Kernel Console */
|
||||
|
||||
#define KERNEL_CONSOLE
|
||||
#define KERNEL_BANNER
|
||||
#define KERNEL_CONSOLEBUF_SIZE 128
|
||||
|
||||
/* Kernel Hook */
|
||||
|
||||
|
||||
/* Command shell */
|
||||
|
||||
#define TOOL_SHELL
|
||||
#define SHELL_ENTER_CR
|
||||
#define SHELL_ENTER_LF
|
||||
#define SHELL_ENTER_CR_AND_LF
|
||||
|
||||
/* Set shell user control */
|
||||
|
||||
#define SHELL_DEFAULT_USER "letter"
|
||||
#define SHELL_DEFAULT_USER_PASSWORD ""
|
||||
#define SHELL_LOCK_TIMEOUT 10000
|
||||
|
||||
/* Set shell config param */
|
||||
|
||||
#define SHELL_TASK_STACK_SIZE 4096
|
||||
#define SHELL_TASK_PRIORITY 20
|
||||
#define SHELL_MAX_NUMBER 5
|
||||
#define SHELL_PARAMETER_MAX_NUMBER 8
|
||||
#define SHELL_HISTORY_MAX_NUMBER 5
|
||||
#define SHELL_PRINT_BUFFER 128
|
||||
#define SHELL_HELP_SHOW_PERMISSION
|
||||
|
||||
/* Kernel data structure Manage */
|
||||
|
||||
#define KERNEL_QUEUEMANAGE
|
||||
#define KERNEL_WORKQUEUE
|
||||
#define WORKQUEUE_KTASK_STACKSIZE 512
|
||||
#define WORKQUEUE_KTASK_PRIORITY 23
|
||||
#define QUEUE_MAX 16
|
||||
#define KERNEL_WAITQUEUE
|
||||
#define KERNEL_DATAQUEUE
|
||||
|
||||
/* Kernel components init */
|
||||
|
||||
#define KERNEL_COMPONENTS_INIT
|
||||
#define ENV_INIT_KTASK_STACK_SIZE 8192
|
||||
#define KERNEL_USER_MAIN
|
||||
#define NAME_NUM_MAX 32
|
||||
|
||||
/* hash table config */
|
||||
|
||||
#define ID_HTABLE_SIZE 16
|
||||
#define ID_NUM_MAX 128
|
||||
|
||||
/* File system */
|
||||
|
||||
#define FS_VFS
|
||||
#define VFS_USING_WORKDIR
|
||||
#define FS_VFS_DEVFS
|
||||
#define FS_VFS_FATFS
|
||||
|
||||
/* APP Framework */
|
||||
|
||||
/* Perception */
|
||||
|
||||
|
||||
/* connection */
|
||||
|
||||
|
||||
/* Intelligence */
|
||||
|
||||
|
||||
/* Control */
|
||||
|
||||
/* Lib */
|
||||
|
||||
#define LIB
|
||||
#define LIB_POSIX
|
||||
|
||||
/* C++ features */
|
||||
|
||||
#define LIB_NEWLIB
|
||||
|
||||
/* Security */
|
||||
|
||||
|
||||
/* Applications */
|
||||
|
||||
|
||||
/* config stack size and priority of main task */
|
||||
|
||||
#define MAIN_KTASK_STACK_SIZE 2048
|
||||
#define MAIN_KTASK_PRIORITY 10
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
mainmenu "XiUOS Project Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config KERNEL_DIR
|
||||
string
|
||||
option env="KERNEL_ROOT"
|
||||
default "../.."
|
||||
|
||||
config BOARD_CORTEX_M4_EVB
|
||||
bool
|
||||
select ARCH_ARM
|
||||
default y
|
||||
|
||||
source "$KERNEL_DIR/arch/Kconfig"
|
||||
|
||||
menu "cortex-m4-emulator feature"
|
||||
source "$BSP_DIR/third_party_driver/Kconfig"
|
||||
|
||||
menu "config default board resources"
|
||||
menu "config board app name"
|
||||
config BOARD_APP_NAME
|
||||
string "config board app name"
|
||||
default "/XiUOS_cortex-m4-emulator_app.bin"
|
||||
endmenu
|
||||
|
||||
menu "config board service table"
|
||||
config SERVICE_TABLE_ADDRESS
|
||||
hex "board service table address"
|
||||
default 0x20000000
|
||||
endmenu
|
||||
|
||||
menu "config hardware resources for connection"
|
||||
if CONNECTION_COMMUNICATION_ETHERNET
|
||||
config ETHERNET_UART_NAME
|
||||
string "ethernet uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
if CONNECTION_COMMUNICATION_WIFI
|
||||
config WIFI_UART_NAME
|
||||
string "wifi uart name"
|
||||
default "/dev/usart3_dev3"
|
||||
endif
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
|
||||
menu "Hardware feature"
|
||||
source "$KERNEL_DIR/resources/Kconfig"
|
||||
endmenu
|
||||
|
||||
source "$KERNEL_DIR/Kconfig"
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
SRC_FILES := board.c
|
||||
|
||||
SRC_DIR := third_party_driver
|
||||
|
||||
|
||||
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,201 @@
|
|||
# 从零开始构建矽璓工业物联操作系统：使用ARM架构的cortex-m4 emulator
|
||||
|
||||
[XiUOS](http://xuos.io/) (X Industrial Ubiquitous Operating System) 矽璓XiUOS是一款面向智慧车间的工业物联网操作系统，主要由一个极简的微型实时操作系统内核和其上的工业物联框架构成，通过高效管理工业物联网设备、支撑工业物联应用，在生产车间内实现智能化的“感知环境、联网传输、知悉识别、控制调整”，促进以工业设备和工业控制系统为核心的人、机、物深度互联，帮助提升生产线的数字化和智能化水平。
|
||||
|
||||
|
||||
|
||||
## 1. 简介
|
||||
|
||||
QEMU 是一个通用的开源模拟器和虚拟化工具。目前QEMU已经可以较完整的支持ARM cortex-m4架构。XiUOS同样支持运行在QEMU上
|
||||
|
||||
| 硬件 | 描述 |
|
||||
| -------- | ------------- |
|
||||
| 芯片型号 | netduinoplus2 |
|
||||
| 架构 | cortex-m4 |
|
||||
| 主频 | 168MHz |
|
||||
| 片内SRAM | 100+KB |
|
||||
| 外设支持 | UART、GPIO |
|
||||
|
||||
|
||||
|
||||
## 2. 开发环境搭建
|
||||
|
||||
### 推荐使用：
|
||||
|
||||
**操作系统：** ubuntu18.04 [https://ubuntu.com/download/desktop](https://ubuntu.com/download/desktop)
|
||||
|
||||
更新`ubuntu 18.04`源的方法:（根据自身情况而定，可以不更改）
|
||||
|
||||
第一步:打开sources.list文件
|
||||
|
||||
```c
|
||||
sudo vim /etc/apt/sources.list
|
||||
```
|
||||
|
||||
第二步:将以下内容复制到sources.list文件
|
||||
|
||||
```c
|
||||
deb http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse
|
||||
deb http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse
|
||||
deb http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse
|
||||
deb http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse
|
||||
deb http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse
|
||||
deb-src http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse
|
||||
deb-src http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse
|
||||
deb-src http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse
|
||||
deb-src http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse
|
||||
deb-src http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse
|
||||
```
|
||||
|
||||
第三步:更新源和系统软件
|
||||
|
||||
```c
|
||||
sudo apt-get update
|
||||
sudo apt-get upgrade
|
||||
```
|
||||
|
||||
**开发工具推荐使用 VSCode ，VScode下载地址为：** VSCode [https://code.visualstudio.com/](https://code.visualstudio.com/)，推荐下载地址为 [http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb](http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb)
|
||||
|
||||
### 依赖包安装：
|
||||
|
||||
```
|
||||
$ sudo apt install build-essential pkg-config git
|
||||
$ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev
|
||||
```
|
||||
|
||||
**XiUOS操作系统源码下载：** XiUOS [https://forgeplus.trustie.net/projects/xuos/xiuos](https://forgeplus.trustie.net/projects/xuos/xiuos)
|
||||
|
||||
新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下：
|
||||
|
||||
```c
|
||||
mkdir test && cd test
|
||||
git clone https://git.trustie.net/xuos/xiuos.git
|
||||
```
|
||||
|
||||
打开源码文件包可以看到以下目录：
|
||||
|
||||
| 名称 | 说明 |
|
||||
| ----------- | ---------- |
|
||||
| application | 应用代码 |
|
||||
| board | 板级支持包 |
|
||||
| framework | 应用框架 |
|
||||
| fs | 文件系统 |
|
||||
| kernel | 内核源码 |
|
||||
| resources | 驱动文件 |
|
||||
| tool | 系统工具 |
|
||||
|
||||
使用VScode打开代码，具体操作步骤为：在源码文件夹下打开系统终端，输入`code .`即可打开VScode开发环境，如下图所示：
|
||||
|
||||
<div align= "center">
|
||||
<img src = img/vscode.jpg width =1000>
|
||||
</div>
|
||||
|
||||
|
||||
### 裁减配置工具的下载
|
||||
|
||||
裁减配置工具：
|
||||
|
||||
**工具地址：** kconfig-frontends [https://forgeplus.trustie.net/projects/xuos/kconfig-frontends](https://forgeplus.trustie.net/projects/xuos/kconfig-frontends)，下载与安装的具体命令如下：
|
||||
|
||||
```c
|
||||
mkdir kfrontends && cd kfrontends
|
||||
git clone https://git.trustie.net/xuos/kconfig-frontends.git
|
||||
```
|
||||
|
||||
下载源码后按以下步骤执行软件安装：
|
||||
|
||||
```c
|
||||
cd kconfig-frontends
|
||||
./xs_build.sh
|
||||
```
|
||||
|
||||
### 编译工具链：
|
||||
|
||||
ARM： arm-none-eabi(`gcc version 6.3.1`)，默认安装到Ubuntu的/usr/bin/arm-none-eabi-，使用如下命令行下载和安装。
|
||||
|
||||
```shell
|
||||
$ sudo apt install gcc-arm-none-eabi
|
||||
```
|
||||
|
||||
|
||||
|
||||
## 3. 编译说明
|
||||
|
||||
### 编辑环境：`Ubuntu18.04`
|
||||
|
||||
### 编译工具链：`arm-none-eabi-gcc`
|
||||
|
||||
使用`VScode`打开工程的方法有多种，本文介绍一种快捷键，在项目目录下将`code .`输入linux系统命令终端即可打开目标项目
|
||||
|
||||
|
||||
编译步骤：
|
||||
|
||||
1.在VScode命令终端中执行以下命令，生成配置文件
|
||||
|
||||
```c
|
||||
make BOARD=cortex-m4-emulator menuconfig
|
||||
```
|
||||
|
||||
2.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后保存并退出（本例旨在演示简单的输出例程，所以没有需要配置的选项，双击快捷键ESC退出配置）
|
||||
|
||||
<div align= "center">
|
||||
<img src = img/menuconfig.png width =1000>
|
||||
</div>
|
||||
|
||||
退出时选择`yes`保存上面所配置的内容，如下图所示：
|
||||
|
||||
<div align= "center">
|
||||
<img src = img/menuconfig1.png width =1000>
|
||||
</div>
|
||||
|
||||
3.继续执行以下命令，进行编译
|
||||
|
||||
```
|
||||
make BOARD=cortex-m4-emulator
|
||||
```
|
||||
|
||||
4.如果编译正确无误，会产生XiUOS_cortex-m4-emulator.elf、XiUOS_cortex-m4-emulator.bin文件。
|
||||
|
||||
|
||||
|
||||
## 4. 运行
|
||||
|
||||
### 4.1 安装QEMU
|
||||
|
||||
```
|
||||
sudo apt install qemu-system-arm
|
||||
```
|
||||
|
||||
### 4.2 运行结果
|
||||
|
||||
通过以下命令启动QEMU并加载XiUOS ELF文件
|
||||
|
||||
```
|
||||
qemu-system-arm -machine netduinoplus2 -nographic -kernel build/XiUOS_cortex-m4-emulator.elf
|
||||
```
|
||||
|
||||
QEMU运行起来后将会在终端上看到信息打印输出
|
||||
|
||||
<div align= "center">
|
||||
<img src = img/terminal.png width =1000>
|
||||
</div>
|
||||
|
||||
### 4.3 调试
|
||||
|
||||
通过QEMU可以方便的对XiUOS进行调试，首先安装gdb调试工具
|
||||
|
||||
```
|
||||
sudo apt install gdb-multiarch
|
||||
```
|
||||
|
||||
并通过以下命令启动QEMU
|
||||
|
||||
```
|
||||
qemu-system-arm -machine netduinoplus2 -nographic -kernel build/XiUOS_cortex-m4-emulator.elf -s -S
|
||||
```
|
||||
|
||||
然后要重新开启另一个linux系统终端一个终端，执行`riscv-none-embed-gdb`命令
|
||||
|
||||
```
|
||||
gdb-multiarch build/XiUOS_cortex-m4-emulator.elf -ex "target remote localhost:1234"
|
||||
```
|
||||
|
|
@ -0,0 +1,125 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file board.c
|
||||
* @brief support cortex-m4-emulator-board init configure and start-up
|
||||
* @version 1.0
|
||||
* @author fudan
|
||||
* @date 2021-08-26
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: board.c
|
||||
Description: support cortex-m4-emulator-board init configure and driver/task/... init
|
||||
Others:
|
||||
History:
|
||||
1. Date: 2021-04-25
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. support cortex-m4-emulator-board InitBoardHardware
|
||||
*************************************************/
|
||||
|
||||
#include <xiuos.h>
|
||||
#include "hardware_rcc.h"
|
||||
#include "board.h"
|
||||
#include "connect_usart.h"
|
||||
#include "misc.h"
|
||||
#include <xs_service.h>
|
||||
|
||||
|
||||
|
||||
static void ClockConfiguration()
|
||||
{
|
||||
int cr,cfgr,pllcfgr;
|
||||
int cr1,cfgr1,pllcfgr1;
|
||||
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
|
||||
PWR->CR |= PWR_CR_VOS;
|
||||
RCC_HSEConfig(RCC_HSE_ON);
|
||||
if (RCC_WaitForHSEStartUp() == SUCCESS)
|
||||
{
|
||||
RCC_HCLKConfig(RCC_SYSCLK_Div1);
|
||||
RCC_PCLK2Config(RCC_HCLK_Div2);
|
||||
RCC_PCLK1Config(RCC_HCLK_Div4);
|
||||
RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7);
|
||||
|
||||
RCC_PLLCmd(ENABLE);
|
||||
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
|
||||
|
||||
FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
|
||||
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
|
||||
|
||||
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
|
||||
}
|
||||
SystemCoreClockUpdate();
|
||||
}
|
||||
|
||||
void NVIC_Configuration(void)
|
||||
{
|
||||
#ifdef VECT_TAB_RAM
|
||||
NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
|
||||
#else
|
||||
NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
|
||||
#endif
|
||||
|
||||
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
|
||||
}
|
||||
|
||||
void SysTickConfiguration(void)
|
||||
{
|
||||
RCC_ClocksTypeDef rcc_clocks;
|
||||
uint32 cnts;
|
||||
|
||||
RCC_GetClocksFreq(&rcc_clocks);
|
||||
|
||||
cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND;
|
||||
cnts = cnts / 8;
|
||||
|
||||
SysTick_Config(cnts);
|
||||
SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
|
||||
}
|
||||
|
||||
void SysTick_Handler(int irqn, void *arg)
|
||||
{
|
||||
|
||||
TickAndTaskTimesliceUpdate();
|
||||
|
||||
}
|
||||
DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE);
|
||||
|
||||
|
||||
void InitBoardHardware()
|
||||
{
|
||||
int i = 0;
|
||||
int ret = 0;
|
||||
ClockConfiguration();
|
||||
|
||||
NVIC_Configuration();
|
||||
|
||||
SysTickConfiguration();
|
||||
#ifdef BSP_USING_UART
|
||||
Stm32HwUsartInit();
|
||||
#endif
|
||||
#ifdef KERNEL_CONSOLE
|
||||
InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
|
||||
|
||||
RCC_ClocksTypeDef rcc_clocks;
|
||||
RCC_GetClocksFreq(&rcc_clocks);
|
||||
KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency);
|
||||
|
||||
KPrintf("\nconsole init completed.\n");
|
||||
KPrintf("board initialization......\n");
|
||||
#endif
|
||||
|
||||
InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file board.h
|
||||
* @brief define cortex-m4-emulator-board init configure and start-up function
|
||||
* @version 1.0
|
||||
* @author AIIT fudan Lab
|
||||
* @date 2021-04-25
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: board.h
|
||||
Description: define cortex-m4-emulator-board board init function and struct
|
||||
Others:
|
||||
History:
|
||||
1. Date: 2021-08-25
|
||||
Author: AIIT fudan Lab
|
||||
Modification:
|
||||
1. define cortex-m4-emulator-board InitBoardHardware
|
||||
2. define cortex-m4-emulator-board data and bss struct
|
||||
*************************************************/
|
||||
|
||||
#ifndef BOARD_H
|
||||
#define BOARD_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
extern int __stack_end__;
|
||||
extern unsigned int g_service_table_start;
|
||||
extern unsigned int g_service_table_end;
|
||||
|
||||
#define SURPORT_MPU
|
||||
|
||||
#define MEMORY_START_ADDRESS (&__stack_end__)
|
||||
#define MEM_OFFSET 128
|
||||
#define MEMORY_END_ADDRESS (0x20000000 + MEM_OFFSET * 1024)
|
||||
|
||||
|
||||
#ifdef SEPARATE_COMPILE
|
||||
typedef int (*main_t)(int argc, char *argv[]);
|
||||
typedef void (*exit_t)(void);
|
||||
struct userspace_s
|
||||
{
|
||||
main_t us_entrypoint;
|
||||
exit_t us_taskquit;
|
||||
uintptr_t us_textstart;
|
||||
uintptr_t us_textend;
|
||||
uintptr_t us_datasource;
|
||||
uintptr_t us_datastart;
|
||||
uintptr_t us_dataend;
|
||||
uintptr_t us_bssstart;
|
||||
uintptr_t us_bssend;
|
||||
uintptr_t us_heapend;
|
||||
};
|
||||
#define USERSPACE (( struct userspace_s *)(0x08080000))
|
||||
|
||||
#ifndef SERVICE_TABLE_ADDRESS
|
||||
#define SERVICE_TABLE_ADDRESS (0x20000000)
|
||||
#endif
|
||||
|
||||
#define USER_SRAM_SIZE 64
|
||||
#define USER_MEMORY_START_ADDRESS (USERSPACE->us_bssend)
|
||||
#define USER_MEMORY_END_ADDRESS (0x10000000 + USER_SRAM_SIZE * 1024)
|
||||
#endif
|
||||
|
||||
void InitBoardHardware(void);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
export CROSS_COMPILE ?=/usr/bin/arm-none-eabi-
|
||||
|
||||
export CFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb -Werror
|
||||
export AFLAGS := -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb -gdwarf-2
|
||||
export LFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_cortex-m4-emulator.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds
|
||||
export CXXFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -Werror
|
||||
|
||||
export APPLFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
|
||||
|
||||
|
||||
export DEFINES := -DHAVE_CCONFIG_H -DSTM32F407xx -DUSE_HAL_DRIVER -DHAVE_SIGINFO
|
||||
|
||||
export USING_NEWLIB =1
|
||||
export USING_VFS = 1
|
||||
export USING_SPI = 1
|
||||
export ARCH = arm
|
||||
export USING_LORA = 1
|
||||
Binary file not shown.
|
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|
After Width: | Height: | Size: 35 KiB |
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|
After Width: | Height: | Size: 18 KiB |
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|
After Width: | Height: | Size: 52 KiB |
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|
After Width: | Height: | Size: 56 KiB |
|
|
@ -0,0 +1,136 @@
|
|||
/* ----------------------------------------------------------------------
|
||||
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
|
||||
*
|
||||
* $Date: 19. October 2015
|
||||
* $Revision: V.1.4.5 a
|
||||
*
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_common_tables.h
|
||||
*
|
||||
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
|
||||
*
|
||||
* Target Processor: Cortex-M4/Cortex-M3
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#ifndef _ARM_COMMON_TABLES_H
|
||||
#define _ARM_COMMON_TABLES_H
|
||||
|
||||
#include "arm_math.h"
|
||||
|
||||
extern const uint16_t armBitRevTable[1024];
|
||||
extern const q15_t armRecipTableQ15[64];
|
||||
extern const q31_t armRecipTableQ31[64];
|
||||
/* extern const q31_t realCoefAQ31[1024]; */
|
||||
/* extern const q31_t realCoefBQ31[1024]; */
|
||||
extern const float32_t twiddleCoef_16[32];
|
||||
extern const float32_t twiddleCoef_32[64];
|
||||
extern const float32_t twiddleCoef_64[128];
|
||||
extern const float32_t twiddleCoef_128[256];
|
||||
extern const float32_t twiddleCoef_256[512];
|
||||
extern const float32_t twiddleCoef_512[1024];
|
||||
extern const float32_t twiddleCoef_1024[2048];
|
||||
extern const float32_t twiddleCoef_2048[4096];
|
||||
extern const float32_t twiddleCoef_4096[8192];
|
||||
#define twiddleCoef twiddleCoef_4096
|
||||
extern const q31_t twiddleCoef_16_q31[24];
|
||||
extern const q31_t twiddleCoef_32_q31[48];
|
||||
extern const q31_t twiddleCoef_64_q31[96];
|
||||
extern const q31_t twiddleCoef_128_q31[192];
|
||||
extern const q31_t twiddleCoef_256_q31[384];
|
||||
extern const q31_t twiddleCoef_512_q31[768];
|
||||
extern const q31_t twiddleCoef_1024_q31[1536];
|
||||
extern const q31_t twiddleCoef_2048_q31[3072];
|
||||
extern const q31_t twiddleCoef_4096_q31[6144];
|
||||
extern const q15_t twiddleCoef_16_q15[24];
|
||||
extern const q15_t twiddleCoef_32_q15[48];
|
||||
extern const q15_t twiddleCoef_64_q15[96];
|
||||
extern const q15_t twiddleCoef_128_q15[192];
|
||||
extern const q15_t twiddleCoef_256_q15[384];
|
||||
extern const q15_t twiddleCoef_512_q15[768];
|
||||
extern const q15_t twiddleCoef_1024_q15[1536];
|
||||
extern const q15_t twiddleCoef_2048_q15[3072];
|
||||
extern const q15_t twiddleCoef_4096_q15[6144];
|
||||
extern const float32_t twiddleCoef_rfft_32[32];
|
||||
extern const float32_t twiddleCoef_rfft_64[64];
|
||||
extern const float32_t twiddleCoef_rfft_128[128];
|
||||
extern const float32_t twiddleCoef_rfft_256[256];
|
||||
extern const float32_t twiddleCoef_rfft_512[512];
|
||||
extern const float32_t twiddleCoef_rfft_1024[1024];
|
||||
extern const float32_t twiddleCoef_rfft_2048[2048];
|
||||
extern const float32_t twiddleCoef_rfft_4096[4096];
|
||||
|
||||
|
||||
/* floating-point bit reversal tables */
|
||||
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
|
||||
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
|
||||
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
|
||||
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
|
||||
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
|
||||
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
|
||||
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
|
||||
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
|
||||
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
|
||||
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
|
||||
|
||||
/* fixed-point bit reversal tables */
|
||||
#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
|
||||
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
|
||||
|
||||
/* Tables for Fast Math Sine and Cosine */
|
||||
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
|
||||
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
|
||||
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
|
||||
|
||||
#endif /* ARM_COMMON_TABLES_H */
|
||||
|
|
@ -0,0 +1,79 @@
|
|||
/* ----------------------------------------------------------------------
|
||||
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
|
||||
*
|
||||
* $Date: 19. March 2015
|
||||
* $Revision: V.1.4.5
|
||||
*
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_const_structs.h
|
||||
*
|
||||
* Description: This file has constant structs that are initialized for
|
||||
* user convenience. For example, some can be given as
|
||||
* arguments to the arm_cfft_f32() function.
|
||||
*
|
||||
* Target Processor: Cortex-M4/Cortex-M3
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#ifndef _ARM_CONST_STRUCTS_H
|
||||
#define _ARM_CONST_STRUCTS_H
|
||||
|
||||
#include "arm_math.h"
|
||||
#include "arm_common_tables.h"
|
||||
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,720 @@
|
|||
/**************************************************************************//**
|
||||
* @file cmsis_armcc.h
|
||||
* @brief CMSIS Cortex-M Core Function/Instruction Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#ifndef __CMSIS_ARMCC_H
|
||||
#define __CMSIS_ARMCC_H
|
||||
|
||||
|
||||
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/* intrinsic void __enable_irq(); */
|
||||
/* intrinsic void __disable_irq(); */
|
||||
|
||||
/**
|
||||
\brief Get Control Register
|
||||
\details Returns the content of the Control Register.
|
||||
\return Control Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
return(__regControl);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Control Register
|
||||
\details Writes the given value to the Control Register.
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
__regControl = control;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get IPSR Register
|
||||
\details Returns the content of the IPSR Register.
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
register uint32_t __regIPSR __ASM("ipsr");
|
||||
return(__regIPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get APSR Register
|
||||
\details Returns the content of the APSR Register.
|
||||
\return APSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
register uint32_t __regAPSR __ASM("apsr");
|
||||
return(__regAPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get xPSR Register
|
||||
\details Returns the content of the xPSR Register.
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
register uint32_t __regXPSR __ASM("xpsr");
|
||||
return(__regXPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Process Stack Pointer
|
||||
\details Returns the current value of the Process Stack Pointer (PSP).
|
||||
\return PSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
return(__regProcessStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Process Stack Pointer
|
||||
\details Assigns the given value to the Process Stack Pointer (PSP).
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
__regProcessStackPointer = topOfProcStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Main Stack Pointer
|
||||
\details Returns the current value of the Main Stack Pointer (MSP).
|
||||
\return MSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
return(__regMainStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Main Stack Pointer
|
||||
\details Assigns the given value to the Main Stack Pointer (MSP).
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
__regMainStackPointer = topOfMainStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Priority Mask
|
||||
\details Returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
return(__regPriMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Priority Mask
|
||||
\details Assigns the given value to the Priority Mask Register.
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
__regPriMask = (priMask);
|
||||
}
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
|
||||
|
||||
/**
|
||||
\brief Enable FIQ
|
||||
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable FIQ
|
||||
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Base Priority
|
||||
\details Returns the current value of the Base Priority register.
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
return(__regBasePri);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority
|
||||
\details Assigns the given value to the Base Priority register.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
__regBasePri = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority with condition
|
||||
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
|
||||
or the new value increases the BASEPRI priority level.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePriMax __ASM("basepri_max");
|
||||
__regBasePriMax = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Fault Mask
|
||||
\details Returns the current value of the Fault Mask register.
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
return(__regFaultMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Fault Mask
|
||||
\details Assigns the given value to the Fault Mask register.
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
__regFaultMask = (faultMask & (uint32_t)1);
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
|
||||
|
||||
|
||||
#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
|
||||
|
||||
/**
|
||||
\brief Get FPSCR
|
||||
\details Returns the current value of the Floating Point Status/Control register.
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
return(__regfpscr);
|
||||
#else
|
||||
return(0U);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set FPSCR
|
||||
\details Assigns the given value to the Floating Point Status/Control register.
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
__regfpscr = (fpscr);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
|
||||
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief No Operation
|
||||
\details No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __nop
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Interrupt
|
||||
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __wfi
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Event
|
||||
\details Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __wfe
|
||||
|
||||
|
||||
/**
|
||||
\brief Send Event
|
||||
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV __sev
|
||||
|
||||
|
||||
/**
|
||||
\brief Instruction Synchronization Barrier
|
||||
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or memory,
|
||||
after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() do {\
|
||||
__schedule_barrier();\
|
||||
__isb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
/**
|
||||
\brief Data Synchronization Barrier
|
||||
\details Acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() do {\
|
||||
__schedule_barrier();\
|
||||
__dsb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
/**
|
||||
\brief Data Memory Barrier
|
||||
\details Ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() do {\
|
||||
__schedule_barrier();\
|
||||
__dmb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (32 bit)
|
||||
\details Reverses the byte order in integer value.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV __rev
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order in two unsigned short values.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
\brief Reverse byte order in signed short value
|
||||
\details Reverses the byte order in a signed short value with sign extension to integer.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right in unsigned value (32 bit)
|
||||
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
\param [in] value Value to rotate
|
||||
\param [in] value Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#define __ROR __ror
|
||||
|
||||
|
||||
/**
|
||||
\brief Breakpoint
|
||||
\details Causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __breakpoint(value)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse bit order of value
|
||||
\details Reverses the bit order of the given value.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
|
||||
#define __RBIT __rbit
|
||||
#else
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
|
||||
|
||||
result = value; /* r will be reversed bits of v; first get LSB of v */
|
||||
for (value >>= 1U; value; value >>= 1U)
|
||||
{
|
||||
result <<= 1U;
|
||||
result |= value & 1U;
|
||||
s--;
|
||||
}
|
||||
result <<= s; /* shift when v's highest bits are zero */
|
||||
return(result);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Count leading zeros
|
||||
\details Counts the number of leading zeros of a data value.
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (8 bit)
|
||||
\details Executes a exclusive LDR instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
|
||||
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (16 bit)
|
||||
\details Executes a exclusive LDR instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
|
||||
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
|
||||
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (32 bit)
|
||||
\details Executes a exclusive LDR instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
|
||||
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (8 bit)
|
||||
\details Executes a exclusive STR instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
|
||||
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (16 bit)
|
||||
\details Executes a exclusive STR instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
|
||||
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (32 bit)
|
||||
\details Executes a exclusive STR instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
|
||||
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
|
||||
|
||||
|
||||
/**
|
||||
\brief Remove the exclusive lock
|
||||
\details Removes the exclusive lock which is created by LDREX.
|
||||
*/
|
||||
#define __CLREX __clrex
|
||||
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __ssat
|
||||
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __usat
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right with Extend (32 bit)
|
||||
\details Moves each bit of a bitstring right by one bit.
|
||||
The carry input is shifted in at the left end of the bitstring.
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
rrx r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRBT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRHT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRT(value, ptr) __strt(value, ptr)
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
|
||||
|
||||
#define __SADD8 __sadd8
|
||||
#define __QADD8 __qadd8
|
||||
#define __SHADD8 __shadd8
|
||||
#define __UADD8 __uadd8
|
||||
#define __UQADD8 __uqadd8
|
||||
#define __UHADD8 __uhadd8
|
||||
#define __SSUB8 __ssub8
|
||||
#define __QSUB8 __qsub8
|
||||
#define __SHSUB8 __shsub8
|
||||
#define __USUB8 __usub8
|
||||
#define __UQSUB8 __uqsub8
|
||||
#define __UHSUB8 __uhsub8
|
||||
#define __SADD16 __sadd16
|
||||
#define __QADD16 __qadd16
|
||||
#define __SHADD16 __shadd16
|
||||
#define __UADD16 __uadd16
|
||||
#define __UQADD16 __uqadd16
|
||||
#define __UHADD16 __uhadd16
|
||||
#define __SSUB16 __ssub16
|
||||
#define __QSUB16 __qsub16
|
||||
#define __SHSUB16 __shsub16
|
||||
#define __USUB16 __usub16
|
||||
#define __UQSUB16 __uqsub16
|
||||
#define __UHSUB16 __uhsub16
|
||||
#define __SASX __sasx
|
||||
#define __QASX __qasx
|
||||
#define __SHASX __shasx
|
||||
#define __UASX __uasx
|
||||
#define __UQASX __uqasx
|
||||
#define __UHASX __uhasx
|
||||
#define __SSAX __ssax
|
||||
#define __QSAX __qsax
|
||||
#define __SHSAX __shsax
|
||||
#define __USAX __usax
|
||||
#define __UQSAX __uqsax
|
||||
#define __UHSAX __uhsax
|
||||
#define __USAD8 __usad8
|
||||
#define __USADA8 __usada8
|
||||
#define __SSAT16 __ssat16
|
||||
#define __USAT16 __usat16
|
||||
#define __UXTB16 __uxtb16
|
||||
#define __UXTAB16 __uxtab16
|
||||
#define __SXTB16 __sxtb16
|
||||
#define __SXTAB16 __sxtab16
|
||||
#define __SMUAD __smuad
|
||||
#define __SMUADX __smuadx
|
||||
#define __SMLAD __smlad
|
||||
#define __SMLADX __smladx
|
||||
#define __SMLALD __smlald
|
||||
#define __SMLALDX __smlaldx
|
||||
#define __SMUSD __smusd
|
||||
#define __SMUSDX __smusdx
|
||||
#define __SMLSD __smlsd
|
||||
#define __SMLSDX __smlsdx
|
||||
#define __SMLSLD __smlsld
|
||||
#define __SMLSLDX __smlsldx
|
||||
#define __SEL __sel
|
||||
#define __QADD __qadd
|
||||
#define __QSUB __qsub
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||
|
||||
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||
((int64_t)(ARG3) << 32U) ) >> 32U))
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x04) */
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#endif /* __CMSIS_ARMCC_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,707 @@
|
|||
/* ----------------------------------------------------------------------
|
||||
* $Date: 5. February 2013
|
||||
* $Revision: V1.02
|
||||
*
|
||||
* Project: CMSIS-RTOS API
|
||||
* Title: cmsis_os.h template header file
|
||||
*
|
||||
* Version 0.02
|
||||
* Initial Proposal Phase
|
||||
* Version 0.03
|
||||
* osKernelStart added, optional feature: main started as thread
|
||||
* osSemaphores have standard behavior
|
||||
* osTimerCreate does not start the timer, added osTimerStart
|
||||
* osThreadPass is renamed to osThreadYield
|
||||
* Version 1.01
|
||||
* Support for C++ interface
|
||||
* - const attribute removed from the osXxxxDef_t typedef's
|
||||
* - const attribute added to the osXxxxDef macros
|
||||
* Added: osTimerDelete, osMutexDelete, osSemaphoreDelete
|
||||
* Added: osKernelInitialize
|
||||
* Version 1.02
|
||||
* Control functions for short timeouts in microsecond resolution:
|
||||
* Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec
|
||||
* Removed: osSignalGet
|
||||
*----------------------------------------------------------------------------
|
||||
*
|
||||
* Copyright (c) 2013 ARM LIMITED
|
||||
* All rights reserved.
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* - Neither the name of ARM nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without
|
||||
* specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#ifndef _CMSIS_OS_H
|
||||
#define _CMSIS_OS_H
|
||||
|
||||
/// \note MUST REMAIN UNCHANGED: \b osCMSIS identifies the CMSIS-RTOS API version.
|
||||
#define osCMSIS 0x10002 ///< API version (main [31:16] .sub [15:0])
|
||||
|
||||
/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number.
|
||||
#define osCMSIS_KERNEL 0x10000 ///< RTOS identification and version (main [31:16] .sub [15:0])
|
||||
|
||||
/// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS.
|
||||
#define osKernelSystemId "KERNEL V1.00" ///< RTOS identification string
|
||||
|
||||
/// \note MUST REMAIN UNCHANGED: \b osFeature_xxx shall be consistent in every CMSIS-RTOS.
|
||||
#define osFeature_MainThread 1 ///< main thread 1=main can be thread, 0=not available
|
||||
#define osFeature_Pool 1 ///< Memory Pools: 1=available, 0=not available
|
||||
#define osFeature_MailQ 1 ///< Mail Queues: 1=available, 0=not available
|
||||
#define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available
|
||||
#define osFeature_Signals 8 ///< maximum number of Signal Flags available per thread
|
||||
#define osFeature_Semaphore 30 ///< maximum count for \ref osSemaphoreCreate function
|
||||
#define osFeature_Wait 1 ///< osWait function: 1=available, 0=not available
|
||||
#define osFeature_SysTick 1 ///< osKernelSysTick functions: 1=available, 0=not available
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
// ==== Enumeration, structures, defines ====
|
||||
|
||||
/// Priority used for thread control.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osPriority shall be consistent in every CMSIS-RTOS.
|
||||
typedef enum {
|
||||
osPriorityIdle = -3, ///< priority: idle (lowest)
|
||||
osPriorityLow = -2, ///< priority: low
|
||||
osPriorityBelowNormal = -1, ///< priority: below normal
|
||||
osPriorityNormal = 0, ///< priority: normal (default)
|
||||
osPriorityAboveNormal = +1, ///< priority: above normal
|
||||
osPriorityHigh = +2, ///< priority: high
|
||||
osPriorityRealtime = +3, ///< priority: realtime (highest)
|
||||
osPriorityError = 0x84 ///< system cannot determine priority or thread has illegal priority
|
||||
} osPriority;
|
||||
|
||||
/// Timeout value.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osWaitForever shall be consistent in every CMSIS-RTOS.
|
||||
#define osWaitForever 0xFFFFFFFF ///< wait forever timeout value
|
||||
|
||||
/// Status code values returned by CMSIS-RTOS functions.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osStatus shall be consistent in every CMSIS-RTOS.
|
||||
typedef enum {
|
||||
osOK = 0, ///< function completed; no error or event occurred.
|
||||
osEventSignal = 0x08, ///< function completed; signal event occurred.
|
||||
osEventMessage = 0x10, ///< function completed; message event occurred.
|
||||
osEventMail = 0x20, ///< function completed; mail event occurred.
|
||||
osEventTimeout = 0x40, ///< function completed; timeout occurred.
|
||||
osErrorParameter = 0x80, ///< parameter error: a mandatory parameter was missing or specified an incorrect object.
|
||||
osErrorResource = 0x81, ///< resource not available: a specified resource was not available.
|
||||
osErrorTimeoutResource = 0xC1, ///< resource not available within given time: a specified resource was not available within the timeout period.
|
||||
osErrorISR = 0x82, ///< not allowed in ISR context: the function cannot be called from interrupt service routines.
|
||||
osErrorISRRecursive = 0x83, ///< function called multiple times from ISR with same object.
|
||||
osErrorPriority = 0x84, ///< system cannot determine priority or thread has illegal priority.
|
||||
osErrorNoMemory = 0x85, ///< system is out of memory: it was impossible to allocate or reserve memory for the operation.
|
||||
osErrorValue = 0x86, ///< value of a parameter is out of range.
|
||||
osErrorOS = 0xFF, ///< unspecified RTOS error: run-time error but no other error message fits.
|
||||
os_status_reserved = 0x7FFFFFFF ///< prevent from enum down-size compiler optimization.
|
||||
} osStatus;
|
||||
|
||||
|
||||
/// Timer type value for the timer definition.
|
||||
/// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS.
|
||||
typedef enum {
|
||||
osTimerOnce = 0, ///< one-shot timer
|
||||
osTimerPeriodic = 1 ///< repeating timer
|
||||
} os_timer_type;
|
||||
|
||||
/// Entry point of a thread.
|
||||
/// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS.
|
||||
typedef void (*os_pthread) (void const *argument);
|
||||
|
||||
/// Entry point of a timer call back function.
|
||||
/// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS.
|
||||
typedef void (*os_ptimer) (void const *argument);
|
||||
|
||||
// >>> the following data type definitions may shall adapted towards a specific RTOS
|
||||
|
||||
/// Thread ID identifies the thread (pointer to a thread control block).
|
||||
/// \note CAN BE CHANGED: \b os_thread_cb is implementation specific in every CMSIS-RTOS.
|
||||
typedef struct os_thread_cb *osThreadId;
|
||||
|
||||
/// Timer ID identifies the timer (pointer to a timer control block).
|
||||
/// \note CAN BE CHANGED: \b os_timer_cb is implementation specific in every CMSIS-RTOS.
|
||||
typedef struct os_timer_cb *osTimerId;
|
||||
|
||||
/// Mutex ID identifies the mutex (pointer to a mutex control block).
|
||||
/// \note CAN BE CHANGED: \b os_mutex_cb is implementation specific in every CMSIS-RTOS.
|
||||
typedef struct os_mutex_cb *osMutexId;
|
||||
|
||||
/// Semaphore ID identifies the semaphore (pointer to a semaphore control block).
|
||||
/// \note CAN BE CHANGED: \b os_semaphore_cb is implementation specific in every CMSIS-RTOS.
|
||||
typedef struct os_semaphore_cb *osSemaphoreId;
|
||||
|
||||
/// Pool ID identifies the memory pool (pointer to a memory pool control block).
|
||||
/// \note CAN BE CHANGED: \b os_pool_cb is implementation specific in every CMSIS-RTOS.
|
||||
typedef struct os_pool_cb *osPoolId;
|
||||
|
||||
/// Message ID identifies the message queue (pointer to a message queue control block).
|
||||
/// \note CAN BE CHANGED: \b os_messageQ_cb is implementation specific in every CMSIS-RTOS.
|
||||
typedef struct os_messageQ_cb *osMessageQId;
|
||||
|
||||
/// Mail ID identifies the mail queue (pointer to a mail queue control block).
|
||||
/// \note CAN BE CHANGED: \b os_mailQ_cb is implementation specific in every CMSIS-RTOS.
|
||||
typedef struct os_mailQ_cb *osMailQId;
|
||||
|
||||
|
||||
/// Thread Definition structure contains startup information of a thread.
|
||||
/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS.
|
||||
typedef struct os_thread_def {
|
||||
os_pthread pthread; ///< start address of thread function
|
||||
osPriority tpriority; ///< initial thread priority
|
||||
uint32_t instances; ///< maximum number of instances of that thread function
|
||||
uint32_t stacksize; ///< stack size requirements in bytes; 0 is default stack size
|
||||
} osThreadDef_t;
|
||||
|
||||
/// Timer Definition structure contains timer parameters.
|
||||
/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS.
|
||||
typedef struct os_timer_def {
|
||||
os_ptimer ptimer; ///< start address of a timer function
|
||||
} osTimerDef_t;
|
||||
|
||||
/// Mutex Definition structure contains setup information for a mutex.
|
||||
/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS.
|
||||
typedef struct os_mutex_def {
|
||||
uint32_t dummy; ///< dummy value.
|
||||
} osMutexDef_t;
|
||||
|
||||
/// Semaphore Definition structure contains setup information for a semaphore.
|
||||
/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS.
|
||||
typedef struct os_semaphore_def {
|
||||
uint32_t dummy; ///< dummy value.
|
||||
} osSemaphoreDef_t;
|
||||
|
||||
/// Definition structure for memory block allocation.
|
||||
/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS.
|
||||
typedef struct os_pool_def {
|
||||
uint32_t pool_sz; ///< number of items (elements) in the pool
|
||||
uint32_t item_sz; ///< size of an item
|
||||
void *pool; ///< pointer to memory for pool
|
||||
} osPoolDef_t;
|
||||
|
||||
/// Definition structure for message queue.
|
||||
/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS.
|
||||
typedef struct os_messageQ_def {
|
||||
uint32_t queue_sz; ///< number of elements in the queue
|
||||
uint32_t item_sz; ///< size of an item
|
||||
void *pool; ///< memory array for messages
|
||||
} osMessageQDef_t;
|
||||
|
||||
/// Definition structure for mail queue.
|
||||
/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS.
|
||||
typedef struct os_mailQ_def {
|
||||
uint32_t queue_sz; ///< number of elements in the queue
|
||||
uint32_t item_sz; ///< size of an item
|
||||
void *pool; ///< memory array for mail
|
||||
} osMailQDef_t;
|
||||
|
||||
/// Event structure contains detailed information about an event.
|
||||
/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS.
|
||||
/// However the struct may be extended at the end.
|
||||
typedef struct {
|
||||
osStatus status; ///< status code: event or error information
|
||||
union {
|
||||
uint32_t v; ///< message as 32-bit value
|
||||
void *p; ///< message or mail as void pointer
|
||||
int32_t signals; ///< signal flags
|
||||
} value; ///< event value
|
||||
union {
|
||||
osMailQId mail_id; ///< mail id obtained by \ref osMailCreate
|
||||
osMessageQId message_id; ///< message id obtained by \ref osMessageCreate
|
||||
} def; ///< event definition
|
||||
} osEvent;
|
||||
|
||||
|
||||
// ==== Kernel Control Functions ====
|
||||
|
||||
/// Initialize the RTOS Kernel for creating objects.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osKernelInitialize shall be consistent in every CMSIS-RTOS.
|
||||
osStatus osKernelInitialize (void);
|
||||
|
||||
/// Start the RTOS Kernel.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS.
|
||||
osStatus osKernelStart (void);
|
||||
|
||||
/// Check if the RTOS kernel is already started.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS.
|
||||
/// \return 0 RTOS is not started, 1 RTOS is started.
|
||||
int32_t osKernelRunning(void);
|
||||
|
||||
#if (defined (osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available
|
||||
|
||||
/// Get the RTOS kernel system timer counter
|
||||
/// \note MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS.
|
||||
/// \return RTOS kernel system timer as 32-bit value
|
||||
uint32_t osKernelSysTick (void);
|
||||
|
||||
/// The RTOS kernel system timer frequency in Hz
|
||||
/// \note Reflects the system timer setting and is typically defined in a configuration file.
|
||||
#define osKernelSysTickFrequency 100000000
|
||||
|
||||
/// Convert a microseconds value to a RTOS kernel system timer value.
|
||||
/// \param microsec time value in microseconds.
|
||||
/// \return time value normalized to the \ref osKernelSysTickFrequency
|
||||
#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)
|
||||
|
||||
#endif // System Timer available
|
||||
|
||||
// ==== Thread Management ====
|
||||
|
||||
/// Create a Thread Definition with function, priority, and stack requirements.
|
||||
/// \param name name of the thread function.
|
||||
/// \param priority initial priority of the thread function.
|
||||
/// \param instances number of possible thread instances.
|
||||
/// \param stacksz stack size (in bytes) requirements for the thread function.
|
||||
/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the
|
||||
/// macro body is implementation specific in every CMSIS-RTOS.
|
||||
#if defined (osObjectsExternal) // object is external
|
||||
#define osThreadDef(name, priority, instances, stacksz) \
|
||||
extern const osThreadDef_t os_thread_def_##name
|
||||
#else // define the object
|
||||
#define osThreadDef(name, priority, instances, stacksz) \
|
||||
const osThreadDef_t os_thread_def_##name = \
|
||||
{ (name), (priority), (instances), (stacksz) }
|
||||
#endif
|
||||
|
||||
/// Access a Thread definition.
|
||||
/// \param name name of the thread definition object.
|
||||
/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the
|
||||
/// macro body is implementation specific in every CMSIS-RTOS.
|
||||
#define osThread(name) \
|
||||
&os_thread_def_##name
|
||||
|
||||
/// Create a thread and add it to Active Threads and set it to state READY.
|
||||
/// \param[in] thread_def thread definition referenced with \ref osThread.
|
||||
/// \param[in] argument pointer that is passed to the thread function as start argument.
|
||||
/// \return thread ID for reference by other functions or NULL in case of error.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS.
|
||||
osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument);
|
||||
|
||||
/// Return the thread ID of the current running thread.
|
||||
/// \return thread ID for reference by other functions or NULL in case of error.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS.
|
||||
osThreadId osThreadGetId (void);
|
||||
|
||||
/// Terminate execution of a thread and remove it from Active Threads.
|
||||
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS.
|
||||
osStatus osThreadTerminate (osThreadId thread_id);
|
||||
|
||||
/// Pass control to next thread that is in state \b READY.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS.
|
||||
osStatus osThreadYield (void);
|
||||
|
||||
/// Change priority of an active thread.
|
||||
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
|
||||
/// \param[in] priority new priority value for the thread function.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS.
|
||||
osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);
|
||||
|
||||
/// Get current priority of an active thread.
|
||||
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
|
||||
/// \return current priority value of the thread function.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS.
|
||||
osPriority osThreadGetPriority (osThreadId thread_id);
|
||||
|
||||
|
||||
// ==== Generic Wait Functions ====
|
||||
|
||||
/// Wait for Timeout (Time Delay).
|
||||
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
osStatus osDelay (uint32_t millisec);
|
||||
|
||||
#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available
|
||||
|
||||
/// Wait for Signal, Message, Mail, or Timeout.
|
||||
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
|
||||
/// \return event that contains signal, message, or mail information or error code.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS.
|
||||
osEvent osWait (uint32_t millisec);
|
||||
|
||||
#endif // Generic Wait available
|
||||
|
||||
|
||||
// ==== Timer Management Functions ====
|
||||
/// Define a Timer object.
|
||||
/// \param name name of the timer object.
|
||||
/// \param function name of the timer call back function.
|
||||
/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the
|
||||
/// macro body is implementation specific in every CMSIS-RTOS.
|
||||
#if defined (osObjectsExternal) // object is external
|
||||
#define osTimerDef(name, function) \
|
||||
extern const osTimerDef_t os_timer_def_##name
|
||||
#else // define the object
|
||||
#define osTimerDef(name, function) \
|
||||
const osTimerDef_t os_timer_def_##name = \
|
||||
{ (function) }
|
||||
#endif
|
||||
|
||||
/// Access a Timer definition.
|
||||
/// \param name name of the timer object.
|
||||
/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the
|
||||
/// macro body is implementation specific in every CMSIS-RTOS.
|
||||
#define osTimer(name) \
|
||||
&os_timer_def_##name
|
||||
|
||||
/// Create a timer.
|
||||
/// \param[in] timer_def timer object referenced with \ref osTimer.
|
||||
/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
|
||||
/// \param[in] argument argument to the timer call back function.
|
||||
/// \return timer ID for reference by other functions or NULL in case of error.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS.
|
||||
osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument);
|
||||
|
||||
/// Start or restart a timer.
|
||||
/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
|
||||
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value of the timer.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS.
|
||||
osStatus osTimerStart (osTimerId timer_id, uint32_t millisec);
|
||||
|
||||
/// Stop the timer.
|
||||
/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS.
|
||||
osStatus osTimerStop (osTimerId timer_id);
|
||||
|
||||
/// Delete a timer that was created by \ref osTimerCreate.
|
||||
/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osTimerDelete shall be consistent in every CMSIS-RTOS.
|
||||
osStatus osTimerDelete (osTimerId timer_id);
|
||||
|
||||
|
||||
// ==== Signal Management ====
|
||||
|
||||
/// Set the specified Signal Flags of an active thread.
|
||||
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
|
||||
/// \param[in] signals specifies the signal flags of the thread that should be set.
|
||||
/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS.
|
||||
int32_t osSignalSet (osThreadId thread_id, int32_t signals);
|
||||
|
||||
/// Clear the specified Signal Flags of an active thread.
|
||||
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
|
||||
/// \param[in] signals specifies the signal flags of the thread that shall be cleared.
|
||||
/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS.
|
||||
int32_t osSignalClear (osThreadId thread_id, int32_t signals);
|
||||
|
||||
/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread.
|
||||
/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag.
|
||||
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
|
||||
/// \return event flag information or error code.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS.
|
||||
osEvent osSignalWait (int32_t signals, uint32_t millisec);
|
||||
|
||||
|
||||
// ==== Mutex Management ====
|
||||
|
||||
/// Define a Mutex.
|
||||
/// \param name name of the mutex object.
|
||||
/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the
|
||||
/// macro body is implementation specific in every CMSIS-RTOS.
|
||||
#if defined (osObjectsExternal) // object is external
|
||||
#define osMutexDef(name) \
|
||||
extern const osMutexDef_t os_mutex_def_##name
|
||||
#else // define the object
|
||||
#define osMutexDef(name) \
|
||||
const osMutexDef_t os_mutex_def_##name = { 0 }
|
||||
#endif
|
||||
|
||||
/// Access a Mutex definition.
|
||||
/// \param name name of the mutex object.
|
||||
/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the
|
||||
/// macro body is implementation specific in every CMSIS-RTOS.
|
||||
#define osMutex(name) \
|
||||
&os_mutex_def_##name
|
||||
|
||||
/// Create and Initialize a Mutex object.
|
||||
/// \param[in] mutex_def mutex definition referenced with \ref osMutex.
|
||||
/// \return mutex ID for reference by other functions or NULL in case of error.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS.
|
||||
osMutexId osMutexCreate (const osMutexDef_t *mutex_def);
|
||||
|
||||
/// Wait until a Mutex becomes available.
|
||||
/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
|
||||
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS.
|
||||
osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);
|
||||
|
||||
/// Release a Mutex that was obtained by \ref osMutexWait.
|
||||
/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS.
|
||||
osStatus osMutexRelease (osMutexId mutex_id);
|
||||
|
||||
/// Delete a Mutex that was created by \ref osMutexCreate.
|
||||
/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osMutexDelete shall be consistent in every CMSIS-RTOS.
|
||||
osStatus osMutexDelete (osMutexId mutex_id);
|
||||
|
||||
|
||||
// ==== Semaphore Management Functions ====
|
||||
|
||||
#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0)) // Semaphore available
|
||||
|
||||
/// Define a Semaphore object.
|
||||
/// \param name name of the semaphore object.
|
||||
/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the
|
||||
/// macro body is implementation specific in every CMSIS-RTOS.
|
||||
#if defined (osObjectsExternal) // object is external
|
||||
#define osSemaphoreDef(name) \
|
||||
extern const osSemaphoreDef_t os_semaphore_def_##name
|
||||
#else // define the object
|
||||
#define osSemaphoreDef(name) \
|
||||
const osSemaphoreDef_t os_semaphore_def_##name = { 0 }
|
||||
#endif
|
||||
|
||||
/// Access a Semaphore definition.
|
||||
/// \param name name of the semaphore object.
|
||||
/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the
|
||||
/// macro body is implementation specific in every CMSIS-RTOS.
|
||||
#define osSemaphore(name) \
|
||||
&os_semaphore_def_##name
|
||||
|
||||
/// Create and Initialize a Semaphore object used for managing resources.
|
||||
/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore.
|
||||
/// \param[in] count number of available resources.
|
||||
/// \return semaphore ID for reference by other functions or NULL in case of error.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS.
|
||||
osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count);
|
||||
|
||||
/// Wait until a Semaphore token becomes available.
|
||||
/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
|
||||
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
|
||||
/// \return number of available tokens, or -1 in case of incorrect parameters.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS.
|
||||
int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);
|
||||
|
||||
/// Release a Semaphore token.
|
||||
/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS.
|
||||
osStatus osSemaphoreRelease (osSemaphoreId semaphore_id);
|
||||
|
||||
/// Delete a Semaphore that was created by \ref osSemaphoreCreate.
|
||||
/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osSemaphoreDelete shall be consistent in every CMSIS-RTOS.
|
||||
osStatus osSemaphoreDelete (osSemaphoreId semaphore_id);
|
||||
|
||||
#endif // Semaphore available
|
||||
|
||||
|
||||
// ==== Memory Pool Management Functions ====
|
||||
|
||||
#if (defined (osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool Management available
|
||||
|
||||
/// \brief Define a Memory Pool.
|
||||
/// \param name name of the memory pool.
|
||||
/// \param no maximum number of blocks (objects) in the memory pool.
|
||||
/// \param type data type of a single block (object).
|
||||
/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the
|
||||
/// macro body is implementation specific in every CMSIS-RTOS.
|
||||
#if defined (osObjectsExternal) // object is external
|
||||
#define osPoolDef(name, no, type) \
|
||||
extern const osPoolDef_t os_pool_def_##name
|
||||
#else // define the object
|
||||
#define osPoolDef(name, no, type) \
|
||||
const osPoolDef_t os_pool_def_##name = \
|
||||
{ (no), sizeof(type), NULL }
|
||||
#endif
|
||||
|
||||
/// \brief Access a Memory Pool definition.
|
||||
/// \param name name of the memory pool
|
||||
/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the
|
||||
/// macro body is implementation specific in every CMSIS-RTOS.
|
||||
#define osPool(name) \
|
||||
&os_pool_def_##name
|
||||
|
||||
/// Create and Initialize a memory pool.
|
||||
/// \param[in] pool_def memory pool definition referenced with \ref osPool.
|
||||
/// \return memory pool ID for reference by other functions or NULL in case of error.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS.
|
||||
osPoolId osPoolCreate (const osPoolDef_t *pool_def);
|
||||
|
||||
/// Allocate a memory block from a memory pool.
|
||||
/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
|
||||
/// \return address of the allocated memory block or NULL in case of no memory available.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS.
|
||||
void *osPoolAlloc (osPoolId pool_id);
|
||||
|
||||
/// Allocate a memory block from a memory pool and set memory block to zero.
|
||||
/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
|
||||
/// \return address of the allocated memory block or NULL in case of no memory available.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS.
|
||||
void *osPoolCAlloc (osPoolId pool_id);
|
||||
|
||||
/// Return an allocated memory block back to a specific memory pool.
|
||||
/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
|
||||
/// \param[in] block address of the allocated memory block that is returned to the memory pool.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS.
|
||||
osStatus osPoolFree (osPoolId pool_id, void *block);
|
||||
|
||||
#endif // Memory Pool Management available
|
||||
|
||||
|
||||
// ==== Message Queue Management Functions ====
|
||||
|
||||
#if (defined (osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queues available
|
||||
|
||||
/// \brief Create a Message Queue Definition.
|
||||
/// \param name name of the queue.
|
||||
/// \param queue_sz maximum number of messages in the queue.
|
||||
/// \param type data type of a single message element (for debugger).
|
||||
/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the
|
||||
/// macro body is implementation specific in every CMSIS-RTOS.
|
||||
#if defined (osObjectsExternal) // object is external
|
||||
#define osMessageQDef(name, queue_sz, type) \
|
||||
extern const osMessageQDef_t os_messageQ_def_##name
|
||||
#else // define the object
|
||||
#define osMessageQDef(name, queue_sz, type) \
|
||||
const osMessageQDef_t os_messageQ_def_##name = \
|
||||
{ (queue_sz), sizeof (type) }
|
||||
#endif
|
||||
|
||||
/// \brief Access a Message Queue Definition.
|
||||
/// \param name name of the queue
|
||||
/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the
|
||||
/// macro body is implementation specific in every CMSIS-RTOS.
|
||||
#define osMessageQ(name) \
|
||||
&os_messageQ_def_##name
|
||||
|
||||
/// Create and Initialize a Message Queue.
|
||||
/// \param[in] queue_def queue definition referenced with \ref osMessageQ.
|
||||
/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
|
||||
/// \return message queue ID for reference by other functions or NULL in case of error.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS.
|
||||
osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);
|
||||
|
||||
/// Put a Message to a Queue.
|
||||
/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate.
|
||||
/// \param[in] info message information.
|
||||
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS.
|
||||
osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);
|
||||
|
||||
/// Get a Message or Wait for a Message from a Queue.
|
||||
/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate.
|
||||
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
|
||||
/// \return event information that includes status code.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS.
|
||||
osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);
|
||||
|
||||
#endif // Message Queues available
|
||||
|
||||
|
||||
// ==== Mail Queue Management Functions ====
|
||||
|
||||
#if (defined (osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queues available
|
||||
|
||||
/// \brief Create a Mail Queue Definition.
|
||||
/// \param name name of the queue
|
||||
/// \param queue_sz maximum number of messages in queue
|
||||
/// \param type data type of a single message element
|
||||
/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the
|
||||
/// macro body is implementation specific in every CMSIS-RTOS.
|
||||
#if defined (osObjectsExternal) // object is external
|
||||
#define osMailQDef(name, queue_sz, type) \
|
||||
extern const osMailQDef_t os_mailQ_def_##name
|
||||
#else // define the object
|
||||
#define osMailQDef(name, queue_sz, type) \
|
||||
const osMailQDef_t os_mailQ_def_##name = \
|
||||
{ (queue_sz), sizeof (type) }
|
||||
#endif
|
||||
|
||||
/// \brief Access a Mail Queue Definition.
|
||||
/// \param name name of the queue
|
||||
/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the
|
||||
/// macro body is implementation specific in every CMSIS-RTOS.
|
||||
#define osMailQ(name) \
|
||||
&os_mailQ_def_##name
|
||||
|
||||
/// Create and Initialize mail queue.
|
||||
/// \param[in] queue_def reference to the mail queue definition obtain with \ref osMailQ
|
||||
/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
|
||||
/// \return mail queue ID for reference by other functions or NULL in case of error.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS.
|
||||
osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id);
|
||||
|
||||
/// Allocate a memory block from a mail.
|
||||
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
|
||||
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
|
||||
/// \return pointer to memory block that can be filled with mail or NULL in case of error.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS.
|
||||
void *osMailAlloc (osMailQId queue_id, uint32_t millisec);
|
||||
|
||||
/// Allocate a memory block from a mail and set memory block to zero.
|
||||
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
|
||||
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
|
||||
/// \return pointer to memory block that can be filled with mail or NULL in case of error.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS.
|
||||
void *osMailCAlloc (osMailQId queue_id, uint32_t millisec);
|
||||
|
||||
/// Put a mail to a queue.
|
||||
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
|
||||
/// \param[in] mail memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS.
|
||||
osStatus osMailPut (osMailQId queue_id, void *mail);
|
||||
|
||||
/// Get a mail from a queue.
|
||||
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
|
||||
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
|
||||
/// \return event that contains mail information or error code.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS.
|
||||
osEvent osMailGet (osMailQId queue_id, uint32_t millisec);
|
||||
|
||||
/// Free a memory block from a mail.
|
||||
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
|
||||
/// \param[in] mail pointer to the memory block that was obtained with \ref osMailGet.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
/// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS.
|
||||
osStatus osMailFree (osMailQId queue_id, void *mail);
|
||||
|
||||
#endif // Mail Queues available
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // _CMSIS_OS_H
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,79 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cmFunc.h
|
||||
* @brief CMSIS Cortex-M Core Function Access Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
|
||||
|
||||
#ifndef __CORE_CMFUNC_H
|
||||
#define __CORE_CMFUNC_H
|
||||
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/*------------------ RealView Compiler -----------------*/
|
||||
|
||||
|
||||
|
||||
/*------------------ GNU Compiler ----------------------*/
|
||||
#if defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
/*------------------ ICC Compiler ----------------------*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/
|
||||
#elif defined ( __TMS470__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
/*------------------ TASKING Compiler ------------------*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
#endif /* __CORE_CMFUNC_H */
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cmInstr.h
|
||||
* @brief CMSIS Cortex-M Core Instruction Access Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
|
||||
|
||||
#ifndef __CORE_CMINSTR_H
|
||||
#define __CORE_CMINSTR_H
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/*------------------ RealView Compiler -----------------*/
|
||||
|
||||
|
||||
/*------------------ GNU Compiler ----------------------*/
|
||||
#if defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
/*------------------ ICC Compiler ----------------------*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/
|
||||
#elif defined ( __TMS470__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
/*------------------ TASKING Compiler ------------------*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
#endif /* __CORE_CMINSTR_H */
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cmSimd.h
|
||||
* @brief CMSIS Cortex-M SIMD Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
|
||||
|
||||
#ifndef __CORE_CMSIMD_H
|
||||
#define __CORE_CMSIMD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/*------------------ RealView Compiler -----------------*/
|
||||
|
||||
|
||||
/*------------------ GNU Compiler ----------------------*/
|
||||
#if defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
/*------------------ ICC Compiler ----------------------*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/
|
||||
#elif defined ( __TMS470__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
/*------------------ TASKING Compiler ------------------*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CMSIMD_H */
|
||||
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue