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Merge branch 'develop' of https://git.trustie.net/wwg666/xiuos into develop

This commit is contained in:
Wang_Weigen 2021-05-28 14:41:38 +08:00
parent 9fcd9338d3 013e3c14cc
commit 75c879b9e5
18 changed files with 3412 additions and 342 deletions
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4
arch/arm/cortex-m4/system_init.c
View File

@ -91,10 +91,6 @@ void SystemInit(void)
RCC->CR &= (uint32_t)0xFFFBFFFF;
RCC->CIR = 0x00000000;
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
SystemInitExtMemCtl();
#endif
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET;
#else

6
board/aiit-arm32-board/board.c
View File

@ -164,6 +164,12 @@ void InitBoardHardware()
KPrintf("board initialization......\n");
#endif
#ifdef BSP_USING_EXTMEM
extern int HwSramInit(void);
HwSramInit();
#endif
InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
#ifdef SEPARATE_COMPILE

2
board/aiit-arm32-board/third_party_driver/extmem/Makefile
View File

@ -1,3 +1,3 @@
SRC_FILES := extmem.c
SRC_FILES := hardware_fsmc.c connect_fsmc.c
include $(KERNEL_ROOT)/compiler.mk

133
board/aiit-arm32-board/third_party_driver/extmem/connect_fsmc.c Normal file
View File

@ -0,0 +1,133 @@
#include "hardware_fsmc.h"
#include "hardware_gpio.h"
#include "hardware_rcc.h"
#define SRAM_DATA_WIDTH 16
static FSMC_NORSRAMInitTypeDef hsram;
static FSMC_NORSRAMTimingInitTypeDef hsram_read;
static FSMC_NORSRAMTimingInitTypeDef hsram_write;
int HwSramInit(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD|RCC_AHB1Periph_GPIOE|RCC_AHB1Periph_GPIOF|RCC_AHB1Periph_GPIOG, ENABLE);
RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC,ENABLE);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOD, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOE, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOF, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_10 | GPIO_Pin_12;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOG, &GPIO_InitStructure);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource0,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource1,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource4,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource5,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource8,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource9,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource10,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource11,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource12,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource13,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource14,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource15,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource7,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource8,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource9,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource10,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource11,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource12,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource13,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource14,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource15,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource0,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource1,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource2,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource3,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource4,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource5,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource12,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource13,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource14,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource15,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG,GPIO_PinSource0,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG,GPIO_PinSource1,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG,GPIO_PinSource2,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG,GPIO_PinSource3,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG,GPIO_PinSource4,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG,GPIO_PinSource5,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG,GPIO_PinSource10,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG,GPIO_PinSource12,GPIO_AF_FSMC);
hsram.FSMC_ReadWriteTimingStruct = &hsram_read;
hsram.FSMC_WriteTimingStruct = &hsram_write;
/* hsram.Init */
hsram.FSMC_Bank = FSMC_Bank1_NORSRAM1;
hsram.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
hsram.FSMC_MemoryType = FSMC_MemoryType_SRAM;
#if SRAM_DATA_WIDTH == 8
hsram.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
#elif SRAM_DATA_WIDTH == 16
hsram.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
#else
hsram.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_32b;
#endif
hsram.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
hsram.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
hsram.FSMC_WrapMode = FSMC_WrapMode_Disable;
hsram.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
hsram.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
hsram.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
hsram.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
hsram.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
hsram_read.FSMC_AddressSetupTime = 1;
hsram_read.FSMC_AddressHoldTime = 0;
hsram_read.FSMC_DataSetupTime = 2;
hsram_read.FSMC_BusTurnAroundDuration = 0;
hsram_read.FSMC_CLKDivision = 0;
hsram_read.FSMC_DataLatency = 0;
hsram_read.FSMC_AccessMode = FSMC_AccessMode_A;
hsram_write.FSMC_AddressSetupTime = 1;
hsram_write.FSMC_AddressHoldTime = 0;
hsram_write.FSMC_DataSetupTime = 2;
hsram_write.FSMC_BusTurnAroundDuration = 0;
hsram_write.FSMC_CLKDivision = 0;
hsram_write.FSMC_DataLatency = 0;
hsram_write.FSMC_AccessMode = FSMC_AccessMode_A;
FSMC_NORSRAMInit(&hsram);
FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM1, ENABLE);
return 0;
}

336
board/aiit-arm32-board/third_party_driver/extmem/extmem.c
View File

@ -1,336 +0,0 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file extmem.c
* @brief support extmem function
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-04-25
*/
#include <extmem.h>
#include <stm32f4xx.h>
#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx)
void SystemInitExtMemCtl(void)
{
__IO uint32_t tmp = 0x00;
register uint32_t tmpreg = 0, timeout = 0xFFFF;
register __IO uint32_t index;
RCC->AHB1ENR |= 0x000001F8;
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
GPIOD->AFR[0] = 0x00CCC0CC;
GPIOD->AFR[1] = 0xCCCCCCCC;
GPIOD->MODER = 0xAAAA0A8A;
GPIOD->OSPEEDR = 0xFFFF0FCF;
GPIOD->OTYPER = 0x00000000;
GPIOD->PUPDR = 0x00000000;
GPIOE->AFR[0] = 0xC00CC0CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
GPIOE->MODER = 0xAAAA828A;
GPIOE->OSPEEDR = 0xFFFFC3CF;
GPIOE->OTYPER = 0x00000000;
GPIOE->PUPDR = 0x00000000;
GPIOF->AFR[0] = 0xCCCCCCCC;
GPIOF->AFR[1] = 0xCCCCCCCC;
GPIOF->MODER = 0xAA800AAA;
GPIOF->OSPEEDR = 0xAA800AAA;
GPIOF->OTYPER = 0x00000000;
GPIOF->PUPDR = 0x00000000;
GPIOG->AFR[0] = 0xCCCCCCCC;
GPIOG->AFR[1] = 0xCCCCCCCC;
GPIOG->MODER = 0xAAAAAAAA;
GPIOG->OSPEEDR = 0xAAAAAAAA;
GPIOG->OTYPER = 0x00000000;
GPIOG->PUPDR = 0x00000000;
GPIOH->AFR[0] = 0x00C0CC00;
GPIOH->AFR[1] = 0xCCCCCCCC;
GPIOH->MODER = 0xAAAA08A0;
GPIOH->OSPEEDR = 0xAAAA08A0;
GPIOH->OTYPER = 0x00000000;
GPIOH->PUPDR = 0x00000000;
GPIOI->AFR[0] = 0xCCCCCCCC;
GPIOI->AFR[1] = 0x00000CC0;
GPIOI->MODER = 0x0028AAAA;
GPIOI->OSPEEDR = 0x0028AAAA;
GPIOI->OTYPER = 0x00000000;
GPIOI->PUPDR = 0x00000000;
RCC->AHB3ENR |= 0x00000001;
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
FMC_Bank5_6->SDCR[0] = 0x000019E4;
FMC_Bank5_6->SDTR[0] = 0x01115351;
FMC_Bank5_6->SDCMR = 0x00000011;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
for (index = 0; index<1000; index++);
FMC_Bank5_6->SDCMR = 0x00000012;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
FMC_Bank5_6->SDCMR = 0x00000073;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
FMC_Bank5_6->SDCMR = 0x00046014;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
tmpreg = FMC_Bank5_6->SDRTR;
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
tmpreg = FMC_Bank5_6->SDCR[0];
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
FMC_Bank1->BTCR[2] = 0x00001011;
FMC_Bank1->BTCR[3] = 0x00000201;
FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif
#if defined(STM32F469xx) || defined(STM32F479xx)
FMC_Bank1->BTCR[2] = 0x00001091;
FMC_Bank1->BTCR[3] = 0x00110212;
FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif
(void)(tmp);
}
#endif
#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
void SystemInitExtMemCtl(void)
{
__IO uint32_t tmp = 0x00;
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
#if defined (DATA_IN_ExtSDRAM)
register uint32_t tmpreg = 0, timeout = 0xFFFF;
register __IO uint32_t index;
#if defined(STM32F446xx)
RCC->AHB1ENR |= 0x0000007D;
#else
RCC->AHB1ENR |= 0x000001F8;
#endif
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
#if defined(STM32F446xx)
GPIOA->AFR[0] |= 0xC0000000;
GPIOA->AFR[1] |= 0x00000000;
GPIOA->MODER |= 0x00008000;
GPIOA->OSPEEDR |= 0x00008000;
GPIOA->OTYPER |= 0x00000000;
GPIOA->PUPDR |= 0x00000000;
GPIOC->AFR[0] |= 0x00CC0000;
GPIOC->AFR[1] |= 0x00000000;
GPIOC->MODER |= 0x00000A00;
GPIOC->OSPEEDR |= 0x00000A00;
GPIOC->OTYPER |= 0x00000000;
GPIOC->PUPDR |= 0x00000000;
#endif
GPIOD->AFR[0] = 0x000000CC;
GPIOD->AFR[1] = 0xCC000CCC;
GPIOD->MODER = 0xA02A000A;
GPIOD->OSPEEDR = 0xA02A000A;
GPIOD->OTYPER = 0x00000000;
GPIOD->PUPDR = 0x00000000;
GPIOE->AFR[0] = 0xC00000CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
GPIOE->MODER = 0xAAAA800A;
GPIOE->OSPEEDR = 0xAAAA800A;
GPIOE->OTYPER = 0x00000000;
GPIOE->PUPDR = 0x00000000;
GPIOF->AFR[0] = 0xCCCCCCCC;
GPIOF->AFR[1] = 0xCCCCCCCC;
GPIOF->MODER = 0xAA800AAA;
GPIOF->OSPEEDR = 0xAA800AAA;
GPIOF->OTYPER = 0x00000000;
GPIOF->PUPDR = 0x00000000;
GPIOG->AFR[0] = 0xCCCCCCCC;
GPIOG->AFR[1] = 0xCCCCCCCC;
GPIOG->MODER = 0xAAAAAAAA;
GPIOG->OSPEEDR = 0xAAAAAAAA;
GPIOG->OTYPER = 0x00000000;
GPIOG->PUPDR = 0x00000000;
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx)
GPIOH->AFR[0] = 0x00C0CC00;
GPIOH->AFR[1] = 0xCCCCCCCC;
GPIOH->MODER = 0xAAAA08A0;
GPIOH->OSPEEDR = 0xAAAA08A0;
GPIOH->OTYPER = 0x00000000;
GPIOH->PUPDR = 0x00000000;
GPIOI->AFR[0] = 0xCCCCCCCC;
GPIOI->AFR[1] = 0x00000CC0;
GPIOI->MODER = 0x0028AAAA;
GPIOI->OSPEEDR = 0x0028AAAA;
GPIOI->OTYPER = 0x00000000;
GPIOI->PUPDR = 0x00000000;
#endif
RCC->AHB3ENR |= 0x00000001;
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
#if defined(STM32F446xx)
FMC_Bank5_6->SDCR[0] = 0x00001954;
#else
FMC_Bank5_6->SDCR[0] = 0x000019E4;
#endif
FMC_Bank5_6->SDTR[0] = 0x01115351;
FMC_Bank5_6->SDCMR = 0x00000011;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
for (index = 0; index<1000; index++);
FMC_Bank5_6->SDCMR = 0x00000012;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
#if defined(STM32F446xx)
FMC_Bank5_6->SDCMR = 0x000000F3;
#else
FMC_Bank5_6->SDCMR = 0x00000073;
#endif
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
#if defined(STM32F446xx)
FMC_Bank5_6->SDCMR = 0x00044014;
#else
FMC_Bank5_6->SDCMR = 0x00046014;
#endif
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
tmpreg = FMC_Bank5_6->SDRTR;
#if defined(STM32F446xx)
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));
#else
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
#endif
tmpreg = FMC_Bank5_6->SDCR[0];
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
#endif
#endif
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
|| defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
#if defined(DATA_IN_ExtSRAM)
RCC->AHB1ENR |= 0x00000078;
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
GPIOD->AFR[0] = 0x00CCC0CC;
GPIOD->AFR[1] = 0xCCCCCCCC;
GPIOD->MODER = 0xAAAA0A8A;
GPIOD->OSPEEDR = 0xFFFF0FCF;
GPIOD->OTYPER = 0x00000000;
GPIOD->PUPDR = 0x00000000;
GPIOE->AFR[0] = 0xC00CC0CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
GPIOE->MODER = 0xAAAA828A;
GPIOE->OSPEEDR = 0xFFFFC3CF;
GPIOE->OTYPER = 0x00000000;
GPIOE->PUPDR = 0x00000000;
GPIOF->AFR[0] = 0x00CCCCCC;
GPIOF->AFR[1] = 0xCCCC0000;
GPIOF->MODER = 0xAA000AAA;
GPIOF->OSPEEDR = 0xFF000FFF;
GPIOF->OTYPER = 0x00000000;
GPIOF->PUPDR = 0x00000000;
GPIOG->AFR[0] = 0x00CCCCCC;
GPIOG->AFR[1] = 0x000000C0;
GPIOG->MODER = 0x00085AAA;
GPIOG->OSPEEDR = 0x000CAFFF;
GPIOG->OTYPER = 0x00000000;
GPIOG->PUPDR = 0x00000000;
RCC->AHB3ENR |= 0x00000001;
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
FMC_Bank1->BTCR[2] = 0x00001011;
FMC_Bank1->BTCR[3] = 0x00000201;
FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif
#if defined(STM32F469xx) || defined(STM32F479xx)
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
FMC_Bank1->BTCR[2] = 0x00001091;
FMC_Bank1->BTCR[3] = 0x00110212;
FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
|| defined(STM32F412Zx) || defined(STM32F412Vx)
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
FSMC_Bank1->BTCR[2] = 0x00001011;
FSMC_Bank1->BTCR[3] = 0x00000201;
FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
#endif
#endif
#endif
(void)(tmp);
}
#endif

1101
board/aiit-arm32-board/third_party_driver/extmem/hardware_fsmc.c Normal file
View File

File diff suppressed because it is too large Load Diff

1
board/aiit-arm32-board/third_party_driver/include/hardware_fsmc.h
View File

@ -334,6 +334,7 @@ typedef struct
#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
#define FSMC_MemoryDataWidth_32b ((uint32_t)0x00000020)
#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
((WIDTH) == FSMC_MemoryDataWidth_16b))
/**

6
board/stm32f407zgt6/board.c
View File

@ -125,6 +125,12 @@ void InitBoardHardware()
KPrintf("\nconsole init completed.\n");
KPrintf("board initialization......\n");
#endif
#ifdef BSP_USING_EXTMEM
extern int HwSramInit(void);
HwSramInit();
#endif
InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
#ifdef SEPARATE_COMPILE

6
board/stm32f407zgt6/third_party_driver/Kconfig
View File

@ -15,3 +15,9 @@ if BSP_USING_UART
source "$BSP_DIR/third_party_driver/uart/Kconfig"
endif
menuconfig BSP_USING_EXTMEM
bool "Using extern memory"
default n
if BSP_USING_EXTMEM
source "$BSP_DIR/third_party_driver/extmem/Kconfig"
endif

3
board/stm32f407zgt6/third_party_driver/Makefile
View File

@ -9,5 +9,8 @@ ifeq ($(CONFIG_BSP_USING_UART),y)
SRC_DIR += uart
endif
ifeq ($(CONFIG_BSP_USING_EXTMEM),y)
SRC_DIR += extmem
endif
include $(KERNEL_ROOT)/compiler.mk

53
board/stm32f407zgt6/third_party_driver/extmem/Kconfig Normal file
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@ -0,0 +1,53 @@
if BSP_USING_EXTMEM
config EXTSRAM_MAX_NUM
int
default 4
config BSP_USING_FSMC_BANK1_NORSRAM1
bool "config fsmc bank1 sram1"
default n
if BSP_USING_FSMC_BANK1_NORSRAM1
config BANK1_NORSRAM1_SIZE
hex "config sram1 chip size"
default 0x100000
config BANK1_NORSRAM1_DATA_WIDTH
int "config sram1 chip data width"
default 16
endif
config BSP_USING_FSMC_BANK1_NORSRAM2
bool "config fsmc bank1 sram2"
default n
if BSP_USING_FSMC_BANK1_NORSRAM2
config BANK1_NORSRAM2_SIZE
hex "config sram2 chip size"
default 0x100000
config BANK1_NORSRAM2_DATA_WIDTH
int "config sram2 chip data width"
default 16
endif
config BSP_USING_FSMC_BANK1_NORSRAM3
bool "config fsmc bank1 sram3"
default n
if BSP_USING_FSMC_BANK1_NORSRAM3
config BANK1_NORSRAM3_SIZE
hex "config sram3 chip size"
default 0x100000
config BANK1_NORSRAM3_DATA_WIDTH
int "config sram3 chip data width"
default 16
endif
config BSP_USING_FSMC_BANK1_NORSRAM4
bool "config fsmc bank1 sram4"
default n
if BSP_USING_FSMC_BANK1_NORSRAM4
config BANK1_NORSRAM4_SIZE
hex "config sram4 chip size"
default 0x100000
config BANK1_NORSRAM4_DATA_WIDTH
int "config sram4 chip data width"
default 16
endif
endif

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SRC_FILES := hardware_fsmc.c connect_fsmc.c
include $(KERNEL_ROOT)/compiler.mk

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/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file connect_fsmc.c
* @brief support extern memory by fsmc
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-05-28
*/
#include "connect_fsmc.h"
#include "hardware_fsmc.h"
#include "hardware_gpio.h"
#include "hardware_rcc.h"
static FSMC_NORSRAMInitTypeDef hsram;
static FSMC_NORSRAMTimingInitTypeDef hsram_read;
static FSMC_NORSRAMTimingInitTypeDef hsram_write;
int HwSramInit(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD|RCC_AHB1Periph_GPIOE|RCC_AHB1Periph_GPIOF|RCC_AHB1Periph_GPIOG, ENABLE);
RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC,ENABLE);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOD, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOE, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOF, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_10 | GPIO_Pin_12;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOG, &GPIO_InitStructure);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource0,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource1,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource4,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource5,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource8,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource9,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource10,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource11,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource12,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource13,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource14,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource15,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource7,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource8,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource9,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource10,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource11,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource12,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource13,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource14,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource15,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource0,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource1,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource2,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource3,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource4,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource5,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource12,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource13,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource14,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource15,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG,GPIO_PinSource0,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG,GPIO_PinSource1,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG,GPIO_PinSource2,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG,GPIO_PinSource3,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG,GPIO_PinSource4,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG,GPIO_PinSource5,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG,GPIO_PinSource10,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG,GPIO_PinSource12,GPIO_AF_FSMC);
hsram.FSMC_ReadWriteTimingStruct = &hsram_read;
hsram.FSMC_WriteTimingStruct = &hsram_write;
/* hsram.Init */
hsram.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
hsram.FSMC_MemoryType = FSMC_MemoryType_SRAM;
hsram.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
hsram.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
hsram.FSMC_WrapMode = FSMC_WrapMode_Disable;
hsram.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
hsram.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
hsram.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
hsram.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
hsram.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
hsram_read.FSMC_AddressSetupTime = 1;
hsram_read.FSMC_AddressHoldTime = 0;
hsram_read.FSMC_DataSetupTime = 2;
hsram_read.FSMC_BusTurnAroundDuration = 0;
hsram_read.FSMC_CLKDivision = 0;
hsram_read.FSMC_DataLatency = 0;
hsram_read.FSMC_AccessMode = FSMC_AccessMode_A;
hsram_write.FSMC_AddressSetupTime = 1;
hsram_write.FSMC_AddressHoldTime = 0;
hsram_write.FSMC_DataSetupTime = 2;
hsram_write.FSMC_BusTurnAroundDuration = 0;
hsram_write.FSMC_CLKDivision = 0;
hsram_write.FSMC_DataLatency = 0;
hsram_write.FSMC_AccessMode = FSMC_AccessMode_A;
#ifdef BSP_USING_FSMC_BANK1_NORSRAM1
hsram.FSMC_Bank = FSMC_Bank1_NORSRAM1;
#if BANK1_NORSRAM1_DATA_WIDTH == 8
hsram.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
#elif BANK1_NORSRAM1_DATA_WIDTH == 16
hsram.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
#else
hsram.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_32b;
#endif
FSMC_NORSRAMInit(&hsram);
FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM1, ENABLE);
#endif
#ifdef BSP_USING_FSMC_BANK1_NORSRAM2
hsram.FSMC_Bank = FSMC_Bank1_NORSRAM2;
#if BANK1_NORSRAM2_DATA_WIDTH == 8
hsram.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
#elif BANK1_NORSRAM2_DATA_WIDTH == 16
hsram.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
#else
hsram.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_32b;
#endif
FSMC_NORSRAMInit(&hsram);
FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);
#endif
#ifdef BSP_USING_FSMC_BANK1_NORSRAM3
hsram.FSMC_Bank = FSMC_Bank1_NORSRAM3;
#if BANK1_NORSRAM3_DATA_WIDTH == 8
hsram.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
#elif BANK1_NORSRAM3_DATA_WIDTH == 16
hsram.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
#else
hsram.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_32b;
#endif
FSMC_NORSRAMInit(&hsram);
FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
#endif
#ifdef BSP_USING_FSMC_BANK1_NORSRAM4
hsram.FSMC_Bank = FSMC_Bank1_NORSRAM4;
#if BANK1_NORSRAM4_DATA_WIDTH == 8
hsram.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
#elif BANK1_NORSRAM4_DATA_WIDTH == 16
hsram.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
#else
hsram.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_32b;
#endif
FSMC_NORSRAMInit(&hsram);
FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM4, ENABLE);
#endif
return 0;
}

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/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file connect_fsmc.h
* @brief declare stm32f407zgt6-board fsmc function
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-05-28
*/
#ifndef CONNECT_FSMC_H
#define CONNECT_FSMC_H
#include <xsconfig.h>
#ifdef __cplusplus
extern "C" {
#endif
int HwSramInit(void);
#ifdef __cplusplus
}
#endif
#endif

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/**
******************************************************************************
* @file stm32f4xx_fsmc.h
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the FSMC firmware
* library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/**
* @file: hardware_fsmc.h
* @brief: define hardware fsmc function
* @version: 1.0
* @author: AIIT XUOS Lab
* @date: 2021/4/25
*/
/*************************************************
File name: hardware_fsmc.h
Description: define hardware fsmc function
Others:
History:
1. Date: 2021-04-25
Author: AIIT XUOS Lab
Modification:
1. rename stm32f4xx_fsmc.h for XiUOS
*************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HARDWARE_FSMC_H__
#define __HARDWARE_FSMC_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stm32f4xx.h>
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @addtogroup FSMC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief Timing parameters For NOR/SRAM Banks
*/
typedef struct
{
uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the address setup time.
This parameter can be a value between 0 and 0xF.
@note This parameter is not used with synchronous NOR Flash memories. */
uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
the duration of the address hold time.
This parameter can be a value between 0 and 0xF.
@note This parameter is not used with synchronous NOR Flash memories.*/
uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the data setup time.
This parameter can be a value between 0 and 0xFF.
@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
the duration of the bus turnaround.
This parameter can be a value between 0 and 0xF.
@note This parameter is only used for multiplexed NOR Flash memories. */
uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
This parameter can be a value between 1 and 0xF.
@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
to the memory before getting the first data.
The parameter value depends on the memory type as shown below:
- It must be set to 0 in case of a CRAM
- It is don't care in asynchronous NOR, SRAM or ROM accesses
- It may assume a value between 0 and 0xF in NOR Flash memories
with synchronous burst mode enable */
uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode.
This parameter can be a value of @ref FSMC_Access_Mode */
}FSMC_NORSRAMTimingInitTypeDef;
/**
* @brief FSMC NOR/SRAM Init structure definition
*/
typedef struct
{
uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
This parameter can be a value of @ref FSMC_NORSRAM_Bank */
uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are
multiplexed on the databus or not.
This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to
the corresponding memory bank.
This parameter can be a value of @ref FSMC_Memory_Type */
uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
This parameter can be a value of @ref FSMC_Data_Width */
uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
valid only with synchronous burst Flash memories.
This parameter can be a value of @ref FSMC_Burst_Access_Mode */
uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
valid only with asynchronous Flash memories.
This parameter can be a value of @ref FSMC_AsynchronousWait */
uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
the Flash memory in burst mode.
This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
memory, valid only when accessing Flash memories in burst mode.
This parameter can be a value of @ref FSMC_Wrap_Mode */
uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
clock cycle before the wait state or during the wait state,
valid only when accessing memories in burst mode.
This parameter can be a value of @ref FSMC_Wait_Timing */
uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC.
This parameter can be a value of @ref FSMC_Write_Operation */
uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait
signal, valid for Flash memory access in burst mode.
This parameter can be a value of @ref FSMC_Wait_Signal */
uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.
This parameter can be a value of @ref FSMC_Extended_Mode */
uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.
This parameter can be a value of @ref FSMC_Write_Burst */
FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/
FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/
}FSMC_NORSRAMInitTypeDef;
/**
* @brief Timing parameters For FSMC NAND and PCCARD Banks
*/
typedef struct
{
uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
the command assertion for NAND-Flash read or write access
to common/Attribute or I/O memory space (depending on
the memory space timing to be configured).
This parameter can be a value between 0 and 0xFF.*/
uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to CHECK the
command for NAND-Flash read or write access to
common/Attribute or I/O memory space (depending on the
memory space timing to be configured).
This parameter can be a number between 0x00 and 0xFF */
uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
(and data for write access) after the command deassertion
for NAND-Flash read or write access to common/Attribute
or I/O memory space (depending on the memory space timing
to be configured).
This parameter can be a number between 0x00 and 0xFF */
uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
databus is kept in HiZ after the start of a NAND-Flash
write access to common/Attribute or I/O memory space (depending
on the memory space timing to be configured).
This parameter can be a number between 0x00 and 0xFF */
}FSMC_NAND_PCCARDTimingInitTypeDef;
/**
* @brief FSMC NAND Init structure definition
*/
typedef struct
{
uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used.
This parameter can be a value of @ref FSMC_NAND_Bank */
uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
This parameter can be any value of @ref FSMC_Wait_feature */
uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
This parameter can be any value of @ref FSMC_Data_Width */
uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation.
This parameter can be any value of @ref FSMC_ECC */
uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC.
This parameter can be any value of @ref FSMC_ECC_Page_Size */
uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between CLE low and RE low.
This parameter can be a value between 0 and 0xFF. */
uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between ALE low and RE low.
This parameter can be a number between 0x0 and 0xFF */
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
}FSMC_NANDInitTypeDef;
/**
* @brief FSMC PCCARD Init structure definition
*/
typedef struct
{
uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.
This parameter can be any value of @ref FSMC_Wait_feature */
uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between CLE low and RE low.
This parameter can be a value between 0 and 0xFF. */
uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between ALE low and RE low.
This parameter can be a number between 0x0 and 0xFF */
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */
}FSMC_PCCARDInitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup FSMC_Exported_Constants
* @{
*/
/** @defgroup FSMC_NORSRAM_Bank
* @{
*/
#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
/**
* @}
*/
/** @defgroup FSMC_NAND_Bank
* @{
*/
#define FSMC_Bank2_NAND ((uint32_t)0x00000010)
#define FSMC_Bank3_NAND ((uint32_t)0x00000100)
/**
* @}
*/
/** @defgroup FSMC_PCCARD_Bank
* @{
*/
#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)
/**
* @}
*/
#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
((BANK) == FSMC_Bank1_NORSRAM2) || \
((BANK) == FSMC_Bank1_NORSRAM3) || \
((BANK) == FSMC_Bank1_NORSRAM4))
#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
((BANK) == FSMC_Bank3_NAND))
#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
((BANK) == FSMC_Bank3_NAND) || \
((BANK) == FSMC_Bank4_PCCARD))
#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
((BANK) == FSMC_Bank3_NAND) || \
((BANK) == FSMC_Bank4_PCCARD))
/** @defgroup FSMC_NOR_SRAM_Controller
* @{
*/
/** @defgroup FSMC_Data_Address_Bus_Multiplexing
* @{
*/
#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
((MUX) == FSMC_DataAddressMux_Enable))
/**
* @}
*/
/** @defgroup FSMC_Memory_Type
* @{
*/
#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
((MEMORY) == FSMC_MemoryType_PSRAM)|| \
((MEMORY) == FSMC_MemoryType_NOR))
/**
* @}
*/
/** @defgroup FSMC_Data_Width
* @{
*/
#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
#define FSMC_MemoryDataWidth_32b ((uint32_t)0x00000020)
#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
((WIDTH) == FSMC_MemoryDataWidth_16b))
/**
* @}
*/
/** @defgroup FSMC_Burst_Access_Mode
* @{
*/
#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
((STATE) == FSMC_BurstAccessMode_Enable))
/**
* @}
*/
/** @defgroup FSMC_AsynchronousWait
* @{
*/
#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
((STATE) == FSMC_AsynchronousWait_Enable))
/**
* @}
*/
/** @defgroup FSMC_Wait_Signal_Polarity
* @{
*/
#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
((POLARITY) == FSMC_WaitSignalPolarity_High))
/**
* @}
*/
/** @defgroup FSMC_Wrap_Mode
* @{
*/
#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
#define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
((MODE) == FSMC_WrapMode_Enable))
/**
* @}
*/
/** @defgroup FSMC_Wait_Timing
* @{
*/
#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
/**
* @}
*/
/** @defgroup FSMC_Write_Operation
* @{
*/
#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
((OPERATION) == FSMC_WriteOperation_Enable))
/**
* @}
*/
/** @defgroup FSMC_Wait_Signal
* @{
*/
#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
((SIGNAL) == FSMC_WaitSignal_Enable))
/**
* @}
*/
/** @defgroup FSMC_Extended_Mode
* @{
*/
#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
((MODE) == FSMC_ExtendedMode_Enable))
/**
* @}
*/
/** @defgroup FSMC_Write_Burst
* @{
*/
#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
((BURST) == FSMC_WriteBurst_Enable))
/**
* @}
*/
/** @defgroup FSMC_Address_Setup_Time
* @{
*/
#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
/**
* @}
*/
/** @defgroup FSMC_Address_Hold_Time
* @{
*/
#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
/**
* @}
*/
/** @defgroup FSMC_Data_Setup_Time
* @{
*/
#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
/**
* @}
*/
/** @defgroup FSMC_Bus_Turn_around_Duration
* @{
*/
#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
/**
* @}
*/
/** @defgroup FSMC_CLK_Division
* @{
*/
#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
/**
* @}
*/
/** @defgroup FSMC_Data_Latency
* @{
*/
#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
/**
* @}
*/
/** @defgroup FSMC_Access_Mode
* @{
*/
#define FSMC_AccessMode_A ((uint32_t)0x00000000)
#define FSMC_AccessMode_B ((uint32_t)0x10000000)
#define FSMC_AccessMode_C ((uint32_t)0x20000000)
#define FSMC_AccessMode_D ((uint32_t)0x30000000)
#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
((MODE) == FSMC_AccessMode_B) || \
((MODE) == FSMC_AccessMode_C) || \
((MODE) == FSMC_AccessMode_D))
/**
* @}
*/
/**
* @}
*/
/** @defgroup FSMC_NAND_PCCARD_Controller
* @{
*/
/** @defgroup FSMC_Wait_feature
* @{
*/
#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
((FEATURE) == FSMC_Waitfeature_Enable))
/**
* @}
*/
/** @defgroup FSMC_ECC
* @{
*/
#define FSMC_ECC_Disable ((uint32_t)0x00000000)
#define FSMC_ECC_Enable ((uint32_t)0x00000040)
#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
((STATE) == FSMC_ECC_Enable))
/**
* @}
*/
/** @defgroup FSMC_ECC_Page_Size
* @{
*/
#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
((SIZE) == FSMC_ECCPageSize_512Bytes) || \
((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
((SIZE) == FSMC_ECCPageSize_8192Bytes))
/**
* @}
*/
/** @defgroup FSMC_TCLR_Setup_Time
* @{
*/
#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
/**
* @}
*/
/** @defgroup FSMC_TAR_Setup_Time
* @{
*/
#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
/**
* @}
*/
/** @defgroup FSMC_Setup_Time
* @{
*/
#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
/**
* @}
*/
/** @defgroup FSMC_Wait_Setup_Time
* @{
*/
#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
/**
* @}
*/
/** @defgroup FSMC_Hold_Setup_Time
* @{
*/
#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
/**
* @}
*/
/** @defgroup FSMC_HiZ_Setup_Time
* @{
*/
#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
/**
* @}
*/
/** @defgroup FSMC_Interrupt_sources
* @{
*/
#define FSMC_IT_RisingEdge ((uint32_t)0x00000008)
#define FSMC_IT_Level ((uint32_t)0x00000010)
#define FSMC_IT_FallingEdge ((uint32_t)0x00000020)
#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
((IT) == FSMC_IT_Level) || \
((IT) == FSMC_IT_FallingEdge))
/**
* @}
*/
/** @defgroup FSMC_Flags
* @{
*/
#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)
#define FSMC_FLAG_Level ((uint32_t)0x00000002)
#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)
#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
((FLAG) == FSMC_FLAG_Level) || \
((FLAG) == FSMC_FLAG_FallingEdge) || \
((FLAG) == FSMC_FLAG_FEMPT))
#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/* NOR/SRAM Controller functions **********************************************/
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
/* NAND Controller functions **************************************************/
void FSMC_NANDDeInit(uint32_t FSMC_Bank);
void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
/* PCCARD Controller functions ************************************************/
void FSMC_PCCARDDeInit(void);
void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
void FSMC_PCCARDCmd(FunctionalState NewState);
/* Interrupts and flags management functions **********************************/
void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
#ifdef __cplusplus
}
#endif
#endif /*__HARDWARE_FSMC_H__ */
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

3
kernel/kernel_test/Makefile
View File

@ -1,4 +1,5 @@
SRC_FILES := test_main.c
SRC_FILES := test_main.c
SRC_FILES += extsram_test.c
ifeq ($(CONFIG_KERNEL_TEST_SEM),y)
SRC_FILES += test_sem.c

79
kernel/kernel_test/extsram_test.c Normal file
View File

@ -0,0 +1,79 @@
#include <xiuos.h>
#include <stdint.h>
/* parameters for sram peripheral */
/* stm32f4 Bank3:0X68000000 */
#define SRAM_BANK_ADDR ((uint32_t)0X60000000)
/* data width: 8, 16, 32 */
#define SRAM_DATA_WIDTH 16
/* sram size */
#define SRAM_SIZE ((uint32_t)0x00100000)
int sram_test(void)
{
int i = 0;
uint32_t start_time = 0, time_cast = 0;
#if SRAM_DATA_WIDTH == 8
char data_width = 1;
uint8_t data = 0;
#elif SRAM_DATA_WIDTH == 16
char data_width = 2;
uint16_t data = 0;
#else
char data_width = 4;
uint32_t data = 0;
#endif
/* write data */
KPrintf("Writing the %ld bytes data, waiting....", SRAM_SIZE);
start_time = CurrentTicksGain();
for (i = 0; i < SRAM_SIZE / data_width; i++)
{
#if SRAM_DATA_WIDTH == 8
*(volatile uint8_t *)(SRAM_BANK_ADDR + i * data_width) = (uint8_t)0x55;
#elif SRAM_DATA_WIDTH == 16
*(volatile uint16_t *)(SRAM_BANK_ADDR + i * data_width) = (uint16_t)0x5555;
#else
*(volatile uint32_t *)(SRAM_BANK_ADDR + i * data_width) = (uint32_t)0x55555555;
#endif
}
time_cast = CurrentTicksGain() - start_time;
KPrintf("Write data success, total time: %d.%03dS.\n", time_cast / TICK_PER_SECOND,
time_cast % TICK_PER_SECOND / ((TICK_PER_SECOND * 1 + 999) / 1000));
/* read data */
KPrintf("start Reading and verifying data, waiting....\n");
for (i = 0; i < SRAM_SIZE / data_width; i++)
{
#if SRAM_DATA_WIDTH == 8
data = *(volatile uint8_t *)(SRAM_BANK_ADDR + i * data_width);
if (data != 0x55)
{
KPrintf("SRAM test failed!");
break;
}
#elif SRAM_DATA_WIDTH == 16
data = *(volatile uint16_t *)(SRAM_BANK_ADDR + i * data_width);
if (data != 0x5555)
{
KPrintf("SRAM test failed! data = 0x%x\n",data);
break;
}
#else
data = *(volatile uint32_t *)(SRAM_BANK_ADDR + i * data_width);
if (data != 0x55555555)
{
KPrintf("SRAM test failed!");
break;
}
#endif
}
if (i >= SRAM_SIZE / data_width)
{
KPrintf("SRAM test success!\n");
}
return 0;
}
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0),sram_test, sram_test, sram_test );