161 lines
9.9 KiB
ArmAsm
161 lines
9.9 KiB
ArmAsm
/**
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******************************************************************************
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* @file startup_stm32f407xx.s
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* @author MCD Application Team
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* @brief STM32F407xx Devices vector table for GCC based toolchains.
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* This module performs:
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* - Set the initial SP
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* - Set the initial PC == Reset_Handler,
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* - Set the vector table entries with the exceptions ISR address
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* - Branches to main in the C library (which eventually
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* calls main()).
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* After Reset the Cortex-M4 processor is in Thread mode,
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* priority is Privileged, and the Stack is set to Main.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/**
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* @file coreclock.c
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* @brief derived from ST standard peripheral library
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* @version 1.0
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* @author AIIT XUOS Lab
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* @date 2021-04-25
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*/
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.globl InterruptVectors
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/******************************************************************************
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*******************************************************************************/
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.section .isr_vector,"a",%progbits
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.type InterruptVectors, %object
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.size InterruptVectors, .-InterruptVectors
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InterruptVectors:
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.word __stack_end__
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.word Reset_Handler
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.word NMI_Handler
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.word HardFaultHandler
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.word MemFaultHandler
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.word BusFault_Handler
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.word UsageFault_Handler
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.word IsrEntry
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.word IsrEntry
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.word IsrEntry
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.word IsrEntry
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.word SVC_Entry /* SVC */
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.word IsrEntry /* DebugMon */
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.word IsrEntry
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.word PendSV_Handler
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.word IsrEntry /* SysTick */
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.word IsrEntry /* Window WatchDog */
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.word IsrEntry /* PVD through EXTI Line detection */
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.word IsrEntry /* Tamper and TimeStamps through the EXTI line */
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.word IsrEntry /* RTC Wakeup through the EXTI line */
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.word IsrEntry /* FLASH */
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.word IsrEntry /* RCC */
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.word IsrEntry /* EXTI Line0 */
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.word IsrEntry /* EXTI Line1 */
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.word IsrEntry /* EXTI Line2 */
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.word IsrEntry /* EXTI Line3 */
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.word IsrEntry /* EXTI Line4 */
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.word IsrEntry /* DMA1 Stream 0 */
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.word IsrEntry /* DMA1 Stream 1 */
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.word IsrEntry /* DMA1 Stream 2 */
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.word IsrEntry /* DMA1 Stream 3 */
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.word IsrEntry /* DMA1 Stream 4 */
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.word IsrEntry /* DMA1 Stream 5 */
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.word IsrEntry /* DMA1 Stream 6 */
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.word IsrEntry /* ADC1, ADC2 and ADC3s */
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.word IsrEntry /* CAN1 TX */
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.word IsrEntry /* CAN1 RX0 */
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.word IsrEntry /* CAN1 RX1 */
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.word IsrEntry /* CAN1 SCE */
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.word IsrEntry /* External Line[9:5]s */
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.word IsrEntry /* TIM1 Break and TIM9 */
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.word IsrEntry /* TIM1 Update and TIM10 */
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.word IsrEntry /* TIM1 Trigger and Commutation and TIM11 */
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.word IsrEntry /* TIM1 Capture Compare */
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.word IsrEntry /* TIM2 */
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.word IsrEntry /* TIM3 */
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.word IsrEntry /* TIM4 */
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.word IsrEntry /* I2C1 Event */
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.word IsrEntry /* I2C1 Error */
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.word IsrEntry /* I2C2 Event */
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.word IsrEntry /* I2C2 Error */
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.word IsrEntry /* SPI1 */
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.word IsrEntry /* SPI2 */
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.word IsrEntry /* USART1 */
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.word IsrEntry /* USART2 */
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.word IsrEntry /* USART3 */
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.word IsrEntry /* External Line[15:10]s */
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.word IsrEntry /* RTC Alarm (A and B) through EXTI Line */
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.word IsrEntry /* USB OTG FS Wakeup through EXTI line */
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.word IsrEntry /* TIM8 Break and TIM12 */
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.word IsrEntry /* TIM8 Update and TIM13 */
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.word IsrEntry /* TIM8 Trigger and Commutation and TIM14 */
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.word IsrEntry /* TIM8 Capture Compare */
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.word IsrEntry /* DMA1 Stream7 */
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.word IsrEntry /* FSMC */
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.word IsrEntry /* SDIO */
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.word IsrEntry /* TIM5 */
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.word IsrEntry /* SPI3 */
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.word IsrEntry /* UART4 */
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.word IsrEntry /* UART5 */
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.word IsrEntry /* TIM6 and DAC1&2 underrun errors */
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.word IsrEntry /* TIM7 */
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.word IsrEntry /* DMA2 Stream 0 */
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.word IsrEntry /* DMA2 Stream 1 */
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.word IsrEntry /* DMA2 Stream 2 */
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.word IsrEntry /* DMA2 Stream 3 */
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.word IsrEntry /* DMA2 Stream 4 */
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.word IsrEntry /* Ethernet */
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.word IsrEntry /* Ethernet Wakeup through EXTI line */
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.word IsrEntry /* CAN2 TX */
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.word IsrEntry /* CAN2 RX0 */
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.word IsrEntry /* CAN2 RX1 */
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.word IsrEntry /* CAN2 SCE */
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.word IsrEntry /* USB OTG FS */
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.word IsrEntry /* DMA2 Stream 5 */
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.word IsrEntry /* DMA2 Stream 6 */
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.word IsrEntry /* DMA2 Stream 7 */
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.word IsrEntry /* USART6 */
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.word IsrEntry /* I2C3 event */
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.word IsrEntry /* I2C3 error */
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.word IsrEntry /* USB OTG HS End Point 1 Out */
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.word IsrEntry /* USB OTG HS End Point 1 In */
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.word IsrEntry /* USB OTG HS Wakeup through EXTI */
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.word IsrEntry /* USB OTG HS */
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.word IsrEntry /* DCMI */
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.word IsrEntry /* CRYP crypto */
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.word IsrEntry /* Hash and Rng */
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.word IsrEntry /* FPU */
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