59 lines
2.2 KiB
C
59 lines
2.2 KiB
C
/*
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* Copyright (c) 2020 AIIT XUOS Lab
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* XiUOS is licensed under Mulan PSL v2.
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* You can use this software according to the terms and conditions of the Mulan PSL v2.
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* You may obtain a copy of Mulan PSL v2 at:
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* http://license.coscl.org.cn/MulanPSL2
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* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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* See the Mulan PSL v2 for more details.
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*/
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#ifndef __INC_SVC_HANDLE_H__
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#define __INC_SVC_HANDLE_H__
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#if defined ( __VFP_FP__ ) && !defined(__SOFTFP__)
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#define INT_FPU_REGS (1)
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#else
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#define INT_FPU_REGS (0)
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#endif
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#define HW_INT_REGS (8)
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#define SW_INT_REGS (9 + INT_FPU_REGS)
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#define REG_INT_R0 (SW_INT_REGS + 0) /* R0 */
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#define REG_INT_R1 (SW_INT_REGS + 1) /* R1 */
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#define REG_INT_R2 (SW_INT_REGS + 2) /* R2 */
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#define REG_INT_R3 (SW_INT_REGS + 3) /* R3 */
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#define REG_INT_R12 (SW_INT_REGS + 4) /* R12 */
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#define REG_INT_R14 (SW_INT_REGS + 5) /* R14 = LR */
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#define REG_INT_PC (SW_INT_REGS + 6) /* R15 = PC */
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#define REG_INT_XPSR (SW_INT_REGS + 7) /* xPSR */
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#if defined ( __VFP_FP__ ) && !defined(__SOFTFP__)
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#define REG_INT_FPU_FLAG (0) /* fpu flag */
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#define REG_INT_PRIMASK (1) /* PRIMASK */
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#define REG_INT_R4 (2) /* R4 */
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#define REG_INT_R5 (3) /* R5 */
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#define REG_INT_R6 (4) /* R6 */
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#define REG_INT_R7 (5) /* R7 */
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#define REG_INT_R8 (6) /* R8 */
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#define REG_INT_R9 (7) /* R9 */
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#define REG_INT_R10 (8) /* R10 */
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#define REG_INT_R11 (9) /* R11 */
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#else
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#define REG_INT_PRIMASK (0) /* PRIMASK */
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#define REG_INT_R4 (1) /* R4 */
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#define REG_INT_R5 (2) /* R5 */
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#define REG_INT_R6 (3) /* R6 */
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#define REG_INT_R7 (4) /* R7 */
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#define REG_INT_R8 (5) /* R8 */
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#define REG_INT_R9 (6) /* R9 */
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#define REG_INT_R10 (7) /* R10 */
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#define REG_INT_R11 (8) /* R11 */
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#endif
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#endif
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