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optimize code standard

This commit is contained in:
Liu_Weichao 2021-04-30 16:01:38 +08:00
parent 3ba05d0a71
commit adcfd5e7f6
70 changed files with 1596 additions and 1773 deletions
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14
arch/arm/cortex-m4/kswitch.h
View File

@ -210,7 +210,7 @@ static inline unsigned long KSwitch0(unsigned int knum)
{
uintptr_t param[1] = {0};
uint8_t num = 0;
(struct Kernel_Service*)SERVICETABLE[knum].fun(knum, param, num);
(struct KernelService*)SERVICETABLE[knum].fun(knum, param, num);
}
static inline unsigned long KSwitch1(unsigned int knum, unsigned long arg1)
@ -218,7 +218,7 @@ static inline unsigned long KSwitch1(unsigned int knum, unsigned long arg1)
uintptr_t param[1] = {0};
uint8_t num = 1;
param[0] = arg1;
(struct Kernel_Service*)SERVICETABLE[knum].fun(knum, param, num);
(struct KernelService*)SERVICETABLE[knum].fun(knum, param, num);
}
@ -229,7 +229,7 @@ static inline unsigned long KSwitch2(unsigned int knum, unsigned long arg1,
uint8_t num = 2;
param[0] = arg1;
param[1] = arg2;
(struct Kernel_Service*)SERVICETABLE[knum].fun(knum, param, num);
(struct KernelService*)SERVICETABLE[knum].fun(knum, param, num);
}
@ -242,7 +242,7 @@ static inline unsigned long KSwitch3(unsigned int knum, unsigned long arg1,
param[1] = arg2;
param[2] = arg3;
(struct Kernel_Service*)SERVICETABLE[knum].fun(knum, param, num);
(struct KernelService*)SERVICETABLE[knum].fun(knum, param, num);
}
static inline unsigned long KSwitch4(unsigned int knum, unsigned long arg1,
@ -255,7 +255,7 @@ static inline unsigned long KSwitch4(unsigned int knum, unsigned long arg1,
param[1] = arg2;
param[2] = arg3;
param[3] = arg4;
(struct Kernel_Service*)SERVICETABLE[knum].fun(knum, param, num);
(struct KernelService*)SERVICETABLE[knum].fun(knum, param, num);
}
static inline unsigned long KSwitch5(unsigned int knum, unsigned long arg1,
@ -269,7 +269,7 @@ static inline unsigned long KSwitch5(unsigned int knum, unsigned long arg1,
param[2] = arg3;
param[3] = arg4;
param[4] = arg5;
(struct Kernel_Service*)SERVICETABLE[knum].fun(knum, param, num);
(struct KernelService*)SERVICETABLE[knum].fun(knum, param, num);
}
static inline unsigned long KSwitch6(unsigned int knum, unsigned long arg1,
@ -285,7 +285,7 @@ static inline unsigned long KSwitch6(unsigned int knum, unsigned long arg1,
param[3] = arg4;
param[4] = arg5;
param[5] = arg6;
(struct Kernel_Service*)SERVICETABLE[knum].fun(knum, param, num);
(struct KernelService*)SERVICETABLE[knum].fun(knum, param, num);
}
#endif

64
board/aiit-arm32-board/third_party_driver/can/connect_can.c
View File

@ -33,15 +33,14 @@ Modification:
static struct CanSendConfigure can_send_deconfig =
{
.stdid = 0x12,
.exdid = 0x12,
.ide = 0 ,
.rtr = 0,
.data_lenth = 8
.stdid = 0x12,
.exdid = 0x12,
.ide = 0 ,
.rtr = 0,
.data_lenth = 8
};
static void CanGPIOInit(void)
static void CanGPIOInit(void)
{
CAN_FilterInitTypeDef can1_filter;
GPIO_InitTypeDef gpio_initstructure;
@ -63,14 +62,14 @@ static void CanGPIOInit(void)
static void Can1NvicConfig(void)
{
NVIC_InitTypeDef can_nvic_config;
NVIC_InitTypeDef can_nvic_config;
can_nvic_config.NVIC_IRQChannel = CAN1_RX0_IRQn;
can_nvic_config.NVIC_IRQChannelPreemptionPriority = 2;
can_nvic_config.NVIC_IRQChannelSubPriority = 2;
can_nvic_config.NVIC_IRQChannelCmd = ENABLE;
CAN_ITConfig(CAN1, CAN_IT_FMP0, ENABLE);
NVIC_Init(&can_nvic_config);
can_nvic_config.NVIC_IRQChannel = CAN1_RX0_IRQn;
can_nvic_config.NVIC_IRQChannelPreemptionPriority = 2;
can_nvic_config.NVIC_IRQChannelSubPriority = 2;
can_nvic_config.NVIC_IRQChannelCmd = ENABLE;
CAN_ITConfig(CAN1, CAN_IT_FMP0, ENABLE);
NVIC_Init(&can_nvic_config);
}
static uint32 CanModeInit(void *drv, struct BusConfigureInfo *configure_info)
@ -129,18 +128,17 @@ static uint32 CanSendMsg(void * dev , struct BusBlockWriteParam *write_param )
tx_data.RTR = 0;
tx_data.DLC = write_param->size;
for(i = 0;i<tx_data.DLC;i++)
{
for(i = 0;i < tx_data.DLC;i ++) {
tx_data.Data[i] = data[i];
}
messege_box = CAN_Transmit(CAN1,&tx_data);
while(CAN_TransmitStatus(CAN1,messege_box)== CAN_TxStatus_Failed &&timer_count){
timer_count--;
while (CAN_TransmitStatus(CAN1,messege_box)== CAN_TxStatus_Failed &&timer_count) {
timer_count--;
}
if(timer_count<=0){
if (timer_count<=0) {
return ERROR;
}
return EOK;
@ -152,17 +150,16 @@ static uint32 CanRecvMsg(void *dev , struct BusBlockReadParam *databuf)
int i;
uint8 * buf = (uint8 *)databuf->buffer;
CanRxMsg msg;
if(CAN_MessagePending(CAN1, CAN_FIFO0) == 0)
if (CAN_MessagePending(CAN1, CAN_FIFO0) == 0)
return 0;
CAN_Receive(CAN1, CAN_FIFO0, &msg);
for(i = 0 ;i<msg.DLC ;i++)
for(i = 0 ;i < msg.DLC;i ++)
buf[i] = msg.Data[i];
databuf->size = msg.DLC ;
return msg.DLC;
}
static struct CanDevDone dev_done =
{
.open = NONE,
@ -171,43 +168,41 @@ static struct CanDevDone dev_done =
.read = CanRecvMsg
};
static struct CanHardwareDevice dev;
#ifdef CAN_USING_INTERRUPT
void CAN1_RX0_IRQHandler(void)
{
CanRxMsg rxmsg;
int i = 0;
CAN_Receive(CAN1, 0, &rxmsg);
for(i = 0;i<8;i++)
for (i = 0;i < 8;i ++)
KPrintf("rxbuf [%d] = :%d",i,rxmsg.Data[i]);
}
DECLARE_HW_IRQ(CAN1_RX0_IRQn, CAN1_RX0_IRQHandler, NONE);
#endif
static int BoardCanBusInit(struct Stm32Can *stm32can_bus, struct CanDriver *can_driver)
{
x_err_t ret = EOK;
/*Init the can bus */
ret = CanBusInit(&stm32can_bus->can_bus, stm32can_bus->bus_name);
if(EOK != ret){
if (EOK != ret) {
KPrintf("Board_can_init canBusInit error %d\n", ret);
return ERROR;
}
/*Init the can driver*/
ret = CanDriverInit(can_driver, CAN_DRIVER_NAME);
if(EOK != ret){
if (EOK != ret) {
KPrintf("Board_can_init canDriverInit error %d\n", ret);
return ERROR;
}
/*Attach the can driver to the can bus*/
ret = CanDriverAttachToBus(CAN_DRIVER_NAME, stm32can_bus->bus_name);
if(EOK != ret){
if (EOK != ret) {
KPrintf("Board_can_init CanDriverAttachToBus error %d\n", ret);
return ERROR;
}
@ -215,8 +210,6 @@ static int BoardCanBusInit(struct Stm32Can *stm32can_bus, struct CanDriver *can_
return ret;
}
static x_err_t HwCanDeviceAttach(const char *bus_name, const char *device_name)
{
NULL_PARAM_CHECK(bus_name);
@ -232,13 +225,13 @@ static x_err_t HwCanDeviceAttach(const char *bus_name, const char *device_name)
can_device->dev_done = &dev_done;
result = CanDeviceRegister(can_device, NONE, device_name);
if(EOK != result){
if (EOK != result) {
KPrintf("board_can_init canDeviceInit device %s error %d\n", "can1", result);
return ERROR;
}
result = CanDeviceAttachToBus(device_name, bus_name);
if (result != EOK){
if (result != EOK) {
SYS_ERR("%s attach to %s faild, %d\n", device_name, bus_name, result);
}
@ -249,7 +242,6 @@ static x_err_t HwCanDeviceAttach(const char *bus_name, const char *device_name)
return result;
}
struct Stm32Can can1;
int Stm32HwCanBusInit(void)
@ -269,13 +261,13 @@ struct Stm32Can can1;
ret = BoardCanBusInit(stm32_can_bus, &can_driver);
if(EOK != ret){
if (EOK != ret) {
KPrintf(" can_bus_init %s error ret %u\n", stm32_can_bus->bus_name, ret);
return ERROR;
}
ret = HwCanDeviceAttach(CAN_BUS_NAME_1,CAN_1_DEVICE_NAME_1);
if(EOK != ret) {
if (EOK != ret) {
KPrintf(" HwCanDeviceAttach %s error ret %u\n", stm32_can_bus->bus_name, ret);
return ERROR;
}

172
board/aiit-arm32-board/third_party_driver/ch438/connect_ch438.c
View File

@ -20,14 +20,14 @@
#include <connect_ch438.h>
static const uint8 offsetadd[] = {0x00,0x10,0x20,0x30,0x08,0x18,0x28,0x38,}; /* uart offset address*/
static const uint8 Interruptnum[8] = {0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80,}; /* SSR register data*/
static const uint8 offset_addr[] = {0x00,0x10,0x20,0x30,0x08,0x18,0x28,0x38,}; /* uart offset address*/
static const uint8 interrupt_num[8] = {0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80,}; /* SSR register data*/
static BusType ch438_pin;
static int Ch438Sem = NONE;
static int ch438_sem = NONE;
static void Ch438Irq(void *parameter)
{
KSemaphoreAbandon(Ch438Sem);
KSemaphoreAbandon(ch438_sem);
}
/**
@ -43,8 +43,7 @@ static void Stm32Udelay(uint32 us)
ticks = us * reload / (1000000 / TICK_PER_SECOND);
told = SysTick->VAL;
while (1)
{
while (1) {
tnow = SysTick->VAL;
if (tnow != told) {
if (tnow < told) {
@ -612,14 +611,13 @@ void WriteCH438Data(uint8 addr, uint8 dat)
********************************************************************************************************/
void WriteCH438Block(uint8 maddr, uint8 mlen, uint8 *mbuf)
{
while (mlen--)
{
while (mlen--) {
WriteCH438Data(maddr, *mbuf++);
}
}
/*********************************************************************************************************
** Function name: CH438UartSend
** Function name: Ch438UartSend
** Function: active FIFO mode, CH438 send multibyte data by uart 0, max length is 128 bytes a single time
** input: send data cache address, send data length
**
@ -631,15 +629,14 @@ void WriteCH438Block(uint8 maddr, uint8 mlen, uint8 *mbuf)
** date:
**-------------------------------------------------------------------------------------------------------
********************************************************************************************************/
void CH438UartSend( uint8 ext_uart_no,uint8 *data, uint8 Num )
void Ch438UartSend( uint8 ext_uart_no,uint8 *data, uint8 Num )
{
uint8 REG_LSR_ADDR,REG_THR_ADDR;
REG_LSR_ADDR = offsetadd[ext_uart_no] | REG_LSR0_ADDR;
REG_THR_ADDR = offsetadd[ext_uart_no] | REG_THR0_ADDR;
REG_LSR_ADDR = offset_addr[ext_uart_no] | REG_LSR0_ADDR;
REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR;
while (1)
{
while (1) {
while((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_TEMT) == 0); /* wait for sending data done, THR and TSR is NULL */
if (Num <= 128) {
@ -654,7 +651,7 @@ void CH438UartSend( uint8 ext_uart_no,uint8 *data, uint8 Num )
}
/*********************************************************************************************************
** Function name: CH438UARTRcv
** Function name: Ch438UartRcv
** Function: forbidden FIFO mode, CH438 receive multibyte data from uart 0
** input: recv data address
**
@ -666,7 +663,7 @@ void CH438UartSend( uint8 ext_uart_no,uint8 *data, uint8 Num )
** date:
**-------------------------------------------------------------------------------------------------------
********************************************************************************************************/
uint8 CH438UARTRcv(uint8 ext_uart_no, uint8 *buf, x_size_t size)
uint8 Ch438UartRcv(uint8 ext_uart_no, uint8 *buf, x_size_t size)
{
uint8 rcv_num = 0;
uint8 dat = 0;
@ -676,13 +673,12 @@ uint8 CH438UARTRcv(uint8 ext_uart_no, uint8 *buf, x_size_t size)
read_buffer = buf;
REG_LSR_ADDR = offsetadd[ext_uart_no] | REG_LSR0_ADDR;
REG_RBR_ADDR = offsetadd[ext_uart_no] | REG_RBR0_ADDR;
REG_LSR_ADDR = offset_addr[ext_uart_no] | REG_LSR0_ADDR;
REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR;
while ((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_DATARDY) == 0); /* wait for data is ready */
while (((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_DATARDY) == 0x01) && (size != 0))
{
while (((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_DATARDY) == 0x01) && (size != 0)) {
dat = ReadCH438Data(REG_RBR_ADDR);
*read_buffer = dat;
@ -705,50 +701,42 @@ static void Timeout438Proc(void *parameter)
{
uint8_t rbr,lsr;
while( ( ReadCH438Data( REG_LSR0_ADDR ) & BIT_LSR_DATARDY ) == 0x01 )
{
while( ( ReadCH438Data( REG_LSR0_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) {
rbr = ReadCH438Data( REG_RBR0_ADDR );
KPrintf("0.RBR=%02x\r\n",rbr);
}
while( ( ReadCH438Data( REG_LSR1_ADDR ) & BIT_LSR_DATARDY ) == 0x01 )
{
while( ( ReadCH438Data( REG_LSR1_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) {
rbr = ReadCH438Data( REG_RBR1_ADDR );
KPrintf("1.RBR=%02x\r\n",rbr);
}
while( ( ReadCH438Data( REG_LSR2_ADDR ) & BIT_LSR_DATARDY ) == 0x01 )
{
while( ( ReadCH438Data( REG_LSR2_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) {
rbr = ReadCH438Data( REG_RBR2_ADDR );
KPrintf("2.RBR=%02x\r\n",rbr);
}
while( ( ReadCH438Data( REG_LSR3_ADDR ) & BIT_LSR_DATARDY ) == 0x01 )
{
while( ( ReadCH438Data( REG_LSR3_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) {
rbr = ReadCH438Data( REG_RBR3_ADDR );
KPrintf("3.RBR=%02x\r\n",rbr);
}
while( ( ReadCH438Data( REG_LSR4_ADDR ) & BIT_LSR_DATARDY ) == 0x01 )
{
while( ( ReadCH438Data( REG_LSR4_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) {
rbr = ReadCH438Data( REG_RBR4_ADDR );
KPrintf("4.RBR=%02x\r\n",rbr);
}
while( ( ReadCH438Data( REG_LSR5_ADDR ) & BIT_LSR_DATARDY ) == 0x01 )
{
while( ( ReadCH438Data( REG_LSR5_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) {
rbr = ReadCH438Data( REG_RBR5_ADDR );
KPrintf("5.RBR=%02x\r\n",rbr);
}
while( ( ReadCH438Data( REG_LSR6_ADDR ) & BIT_LSR_DATARDY ) == 0x01 )
{
while( ( ReadCH438Data( REG_LSR6_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) {
rbr = ReadCH438Data( REG_RBR6_ADDR );
KPrintf("6.RBR=%02x\r\n",rbr);
}
while( ( ReadCH438Data( REG_LSR7_ADDR ) & BIT_LSR_DATARDY ) == 0x01 )
{
while( ( ReadCH438Data( REG_LSR7_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) {
rbr = ReadCH438Data( REG_RBR7_ADDR );
KPrintf("7.RBR=%02x\r\n",rbr);
}
@ -804,7 +792,7 @@ void Set485Output(uint8 ch_no)
}
}
void CH438_PORT_INIT( uint8 ext_uart_no,uint32 BaudRate )
void Ch438PortInit( uint8 ext_uart_no,uint32 BaudRate )
{
uint32 div;
uint8 DLL,DLM,dlab;
@ -818,15 +806,15 @@ void CH438_PORT_INIT( uint8 ext_uart_no,uint32 BaudRate )
uint8 REG_THR_ADDR;
uint8 REG_IIR_ADDR;
REG_LCR_ADDR = offsetadd[ext_uart_no] | REG_LCR0_ADDR;
REG_DLL_ADDR = offsetadd[ext_uart_no] | REG_DLL0_ADDR;
REG_DLM_ADDR = offsetadd[ext_uart_no] | REG_DLM0_ADDR;
REG_IER_ADDR = offsetadd[ext_uart_no] | REG_IER0_ADDR;
REG_MCR_ADDR = offsetadd[ext_uart_no] | REG_MCR0_ADDR;
REG_FCR_ADDR = offsetadd[ext_uart_no] | REG_FCR0_ADDR;
REG_RBR_ADDR = offsetadd[ext_uart_no] | REG_RBR0_ADDR;
REG_THR_ADDR = offsetadd[ext_uart_no] | REG_THR0_ADDR;
REG_IIR_ADDR = offsetadd[ext_uart_no] | REG_IIR0_ADDR;
REG_LCR_ADDR = offset_addr[ext_uart_no] | REG_LCR0_ADDR;
REG_DLL_ADDR = offset_addr[ext_uart_no] | REG_DLL0_ADDR;
REG_DLM_ADDR = offset_addr[ext_uart_no] | REG_DLM0_ADDR;
REG_IER_ADDR = offset_addr[ext_uart_no] | REG_IER0_ADDR;
REG_MCR_ADDR = offset_addr[ext_uart_no] | REG_MCR0_ADDR;
REG_FCR_ADDR = offset_addr[ext_uart_no] | REG_FCR0_ADDR;
REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR;
REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR;
REG_IIR_ADDR = offset_addr[ext_uart_no] | REG_IIR0_ADDR;
WriteCH438Data(REG_IER_ADDR, BIT_IER_RESET); /* reset the uart */
MdelayKTask(50);
@ -869,15 +857,15 @@ void CH438PortInitParityCheck(uint8 ext_uart_no, uint32 BaudRate)
uint8 REG_THR_ADDR;
uint8 REG_IIR_ADDR;
REG_LCR_ADDR = offsetadd[ext_uart_no] | REG_LCR0_ADDR;
REG_DLL_ADDR = offsetadd[ext_uart_no] | REG_DLL0_ADDR;
REG_DLM_ADDR = offsetadd[ext_uart_no] | REG_DLM0_ADDR;
REG_IER_ADDR = offsetadd[ext_uart_no] | REG_IER0_ADDR;
REG_MCR_ADDR = offsetadd[ext_uart_no] | REG_MCR0_ADDR;
REG_FCR_ADDR = offsetadd[ext_uart_no] | REG_FCR0_ADDR;
REG_RBR_ADDR = offsetadd[ext_uart_no] | REG_RBR0_ADDR;
REG_THR_ADDR = offsetadd[ext_uart_no] | REG_THR0_ADDR;
REG_IIR_ADDR = offsetadd[ext_uart_no] | REG_IIR0_ADDR;
REG_LCR_ADDR = offset_addr[ext_uart_no] | REG_LCR0_ADDR;
REG_DLL_ADDR = offset_addr[ext_uart_no] | REG_DLL0_ADDR;
REG_DLM_ADDR = offset_addr[ext_uart_no] | REG_DLM0_ADDR;
REG_IER_ADDR = offset_addr[ext_uart_no] | REG_IER0_ADDR;
REG_MCR_ADDR = offset_addr[ext_uart_no] | REG_MCR0_ADDR;
REG_FCR_ADDR = offset_addr[ext_uart_no] | REG_FCR0_ADDR;
REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR;
REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR;
REG_IIR_ADDR = offset_addr[ext_uart_no] | REG_IIR0_ADDR;
WriteCH438Data(REG_IER_ADDR, BIT_IER_RESET); /* reset the uart */
MdelayKTask(50);
@ -913,7 +901,7 @@ static uint32 Stm32Ch438Configure(struct SerialCfgParam *ext_serial_cfg)
switch (ext_serial_cfg->data_cfg.port_configure)
{
case PORT_CFG_INIT:
CH438_PORT_INIT(ext_serial_cfg->data_cfg.ext_uart_no, ext_serial_cfg->data_cfg.serial_baud_rate);
Ch438PortInit(ext_serial_cfg->data_cfg.ext_uart_no, ext_serial_cfg->data_cfg.serial_baud_rate);
break;
case PORT_CFG_PARITY_CHECK:
CH438PortInitParityCheck(ext_serial_cfg->data_cfg.ext_uart_no, ext_serial_cfg->data_cfg.serial_baud_rate);
@ -1040,11 +1028,11 @@ static uint32 Stm32Ch438DrvConfigure(void *drv, struct BusConfigureInfo *configu
switch (configure_info->configure_cmd)
{
case OPE_INT:
ret = Stm32Ch438Init(serial_drv, ext_serial_cfg);
break;
default:
break;
case OPE_INT:
ret = Stm32Ch438Init(serial_drv, ext_serial_cfg);
break;
default:
break;
}
return ret;
@ -1058,7 +1046,7 @@ static uint32 Stm32Ch438WriteData(void *dev, struct BusBlockWriteParam *write_pa
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)dev;
struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
CH438UartSend(dev_param->ext_uart_no, (uint8 *)write_param->buffer, write_param->size);
Ch438UartSend(dev_param->ext_uart_no, (uint8 *)write_param->buffer, write_param->size);
return EOK;
}
@ -1088,7 +1076,7 @@ static uint32 Stm32Ch438ReadData(void *dev, struct BusBlockReadParam *read_param
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)dev;
struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
result = KSemaphoreObtain(Ch438Sem, WAITING_FOREVER);
result = KSemaphoreObtain(ch438_sem, WAITING_FOREVER);
if (EOK == result) {
gInterruptStatus = ReadCH438Data(REG_SSR_ADDR);
if (!gInterruptStatus) {
@ -1102,18 +1090,18 @@ static uint32 Stm32Ch438ReadData(void *dev, struct BusBlockReadParam *read_param
dat = ReadCH438Data(REG_IIR0_ADDR);
dat = dat ;
} else {
if (gInterruptStatus & Interruptnum[dev_param->ext_uart_no]) { /* check which uart port triggers interrupt*/
REG_LCR_ADDR = offsetadd[dev_param->ext_uart_no] | REG_LCR0_ADDR;
REG_DLL_ADDR = offsetadd[dev_param->ext_uart_no] | REG_DLL0_ADDR;
REG_DLM_ADDR = offsetadd[dev_param->ext_uart_no] | REG_DLM0_ADDR;
REG_IER_ADDR = offsetadd[dev_param->ext_uart_no] | REG_IER0_ADDR;
REG_MCR_ADDR = offsetadd[dev_param->ext_uart_no] | REG_MCR0_ADDR;
REG_FCR_ADDR = offsetadd[dev_param->ext_uart_no] | REG_FCR0_ADDR;
REG_RBR_ADDR = offsetadd[dev_param->ext_uart_no] | REG_RBR0_ADDR;
REG_THR_ADDR = offsetadd[dev_param->ext_uart_no] | REG_THR0_ADDR;
REG_IIR_ADDR = offsetadd[dev_param->ext_uart_no] | REG_IIR0_ADDR;
REG_LSR_ADDR = offsetadd[dev_param->ext_uart_no] | REG_LSR0_ADDR;
REG_MSR_ADDR = offsetadd[dev_param->ext_uart_no] | REG_MSR0_ADDR;
if (gInterruptStatus & interrupt_num[dev_param->ext_uart_no]) { /* check which uart port triggers interrupt*/
REG_LCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_LCR0_ADDR;
REG_DLL_ADDR = offset_addr[dev_param->ext_uart_no] | REG_DLL0_ADDR;
REG_DLM_ADDR = offset_addr[dev_param->ext_uart_no] | REG_DLM0_ADDR;
REG_IER_ADDR = offset_addr[dev_param->ext_uart_no] | REG_IER0_ADDR;
REG_MCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_MCR0_ADDR;
REG_FCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_FCR0_ADDR;
REG_RBR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_RBR0_ADDR;
REG_THR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_THR0_ADDR;
REG_IIR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_IIR0_ADDR;
REG_LSR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_LSR0_ADDR;
REG_MSR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_MSR0_ADDR;
InterruptStatus = ReadCH438Data( REG_IIR_ADDR ) & 0x0f; /* read the status of the uart port*/
@ -1125,7 +1113,7 @@ static uint32 Stm32Ch438ReadData(void *dev, struct BusBlockReadParam *read_param
break;
case INT_RCV_OVERTIME: /* RECV OVERTIME INTERRUPT*/
case INT_RCV_SUCCESS: /* RECV INTERRUPT SUCCESSFULLY*/
rcv_num = CH438UARTRcv(dev_param->ext_uart_no, (uint8 *)read_param->buffer, read_param->size);
rcv_num = Ch438UartRcv(dev_param->ext_uart_no, (uint8 *)read_param->buffer, read_param->size);
read_param->read_length = rcv_num;
break;
case INT_RCV_LINES: /* RECV LINES INTERRUPT */
@ -1162,8 +1150,8 @@ static void Stm32Ch438InitDefault(struct SerialDriver *serial_drv)
configure_info.configure_cmd = OPE_CFG;
configure_info.private_data = (void *)&PinCfg;
Ch438Sem = KSemaphoreCreate(0);
if (Ch438Sem < 0) {
ch438_sem = KSemaphoreCreate(0);
if (ch438_sem < 0) {
KPrintf("Ch438InitDefault create sem failed .\n");
return ;
}
@ -1375,21 +1363,21 @@ void CH438RegTest(unsigned char num)//for test
{
uint8 dat;
KPrintf("current test serilnum: %02x \r\n",offsetadd[num]);
KPrintf("IER: %02x\r\n",ReadCH438Data(offsetadd[num] | REG_IER0_ADDR));//?IER
KPrintf("IIR: %02x\r\n",ReadCH438Data(offsetadd[num] | REG_IIR0_ADDR));//?IIR
KPrintf("LCR: %02x\r\n",ReadCH438Data(offsetadd[num] | REG_LCR0_ADDR));//?LCR
KPrintf("MCR: %02x\r\n",ReadCH438Data(offsetadd[num] | REG_MCR0_ADDR));//?MCR
KPrintf("LSR: %02x\r\n",ReadCH438Data(offsetadd[num] | REG_LSR0_ADDR));//?LSR
KPrintf("MSR: %02x\r\n",ReadCH438Data(offsetadd[num] | REG_MSR0_ADDR));//?MSR
KPrintf("FCR: %02x\r\n",ReadCH438Data(offsetadd[num] | REG_FCR0_ADDR));//?FCR
KPrintf("SSR: %02x\r\n",ReadCH438Data( offsetadd[num] | REG_SSR_ADDR ));//?SSR
KPrintf("current test serilnum: %02x \r\n",offset_addr[num]);
KPrintf("IER: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_IER0_ADDR));//?IER
KPrintf("IIR: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_IIR0_ADDR));//?IIR
KPrintf("LCR: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_LCR0_ADDR));//?LCR
KPrintf("MCR: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_MCR0_ADDR));//?MCR
KPrintf("LSR: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_LSR0_ADDR));//?LSR
KPrintf("MSR: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_MSR0_ADDR));//?MSR
KPrintf("FCR: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_FCR0_ADDR));//?FCR
KPrintf("SSR: %02x\r\n",ReadCH438Data( offset_addr[num] | REG_SSR_ADDR ));//?SSR
KPrintf("SCR0: %02x\r\n",(unsigned short)ReadCH438Data(offsetadd[num] | REG_SCR0_ADDR));//?SCR
KPrintf("SCR0: %02x\r\n",(unsigned short)ReadCH438Data(offset_addr[num] | REG_SCR0_ADDR));//?SCR
dat = 0x55;
WriteCH438Data(offsetadd[num] | REG_SCR0_ADDR, dat);
KPrintf("SCR55: %02x\r\n",(unsigned short)ReadCH438Data(offsetadd[num] | REG_SCR0_ADDR));//?SCR
WriteCH438Data(offset_addr[num] | REG_SCR0_ADDR, dat);
KPrintf("SCR55: %02x\r\n",(unsigned short)ReadCH438Data(offset_addr[num] | REG_SCR0_ADDR));//?SCR
dat = 0xAA;
WriteCH438Data(offsetadd[num] | REG_SCR0_ADDR, dat);
KPrintf("SCRAA: %02x\r\n",(unsigned short)ReadCH438Data(offsetadd[num] | REG_SCR0_ADDR));//?SCR
WriteCH438Data(offset_addr[num] | REG_SCR0_ADDR, dat);
KPrintf("SCRAA: %02x\r\n",(unsigned short)ReadCH438Data(offset_addr[num] | REG_SCR0_ADDR));//?SCR
}

134
board/aiit-arm32-board/third_party_driver/gpio/connect_gpio.c
View File

@ -55,7 +55,7 @@ struct PinIrq
{
uint8 port_source;
uint8 pin_source;
enum IRQn irq_exti_Channel;
enum IRQn irq_exti_channel;
uint32 exti_line;
};
@ -510,8 +510,7 @@ static int32 GpioConfigMode(int mode, const struct PinIndex* index)
static __inline int32 Bit2Bitnum(uint32 bit)
{
for (int i = 0; i < 32; i++)
{
for (int i = 0; i < 32; i++) {
if ((1UL << i) == bit) {
return i;
}
@ -521,10 +520,9 @@ static __inline int32 Bit2Bitnum(uint32 bit)
static __inline int32 Bitno2Bit(uint32 bitno)
{
if (bitno <= 32){
if (bitno <= 32) {
return 1UL << bitno;
}
else{
} else {
return 0;
}
}
@ -533,7 +531,7 @@ static const struct PinIrq *GetPinIrq(uint16_t pin)
static struct PinIrq irq;
const struct PinIndex* index = GetPin(pin);
if (index == NONE){
if (index == NONE) {
return NONE;
}
@ -542,35 +540,35 @@ static const struct PinIrq *GetPinIrq(uint16_t pin)
irq.port_source = ((uint32_t)index->gpio - GPIOA_BASE) / (GPIOB_BASE - GPIOA_BASE);
switch (irq.pin_source)
{
case 0 : irq.irq_exti_Channel = EXTI0_IRQn;break;
case 1 : irq.irq_exti_Channel = EXTI1_IRQn;break;
case 2 : irq.irq_exti_Channel = EXTI2_IRQn;break;
case 3 : irq.irq_exti_Channel = EXTI3_IRQn;break;
case 4 : irq.irq_exti_Channel = EXTI4_IRQn;break;
case 5 :
case 6 :
case 7 :
case 8 :
case 9 : irq.irq_exti_Channel = EXTI9_5_IRQn;break;
case 10 :
case 11 :
case 12 :
case 13 :
case 14 :
case 15 : irq.irq_exti_Channel = EXTI15_10_IRQn;break;
default : return NONE;
case 0 : irq.irq_exti_channel = EXTI0_IRQn;break;
case 1 : irq.irq_exti_channel = EXTI1_IRQn;break;
case 2 : irq.irq_exti_channel = EXTI2_IRQn;break;
case 3 : irq.irq_exti_channel = EXTI3_IRQn;break;
case 4 : irq.irq_exti_channel = EXTI4_IRQn;break;
case 5 :
case 6 :
case 7 :
case 8 :
case 9 : irq.irq_exti_channel = EXTI9_5_IRQn;break;
case 10 :
case 11 :
case 12 :
case 13 :
case 14 :
case 15 : irq.irq_exti_channel = EXTI15_10_IRQn;break;
default : return NONE;
}
return &irq;
};
static int32 GpioIrqRegister(int32 pin, int32 mode, void (*hdr)(void *args), void *args)
{
const struct PinIndex* index = GetPin(pin);
int32 irqindex = -1;
irqindex = Bit2Bitnum(index->pin);
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab))
{
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab)) {
return -ENONESYS;
}
@ -584,7 +582,7 @@ static int32 GpioIrqRegister(int32 pin, int32 mode, void (*hdr)(void *args), voi
CriticalAreaUnLock(level);
return EOK;
}
if (pin_irq_hdr_tab[irqindex].pin != -1){
if (pin_irq_hdr_tab[irqindex].pin != -1) {
CriticalAreaUnLock(level);
return -EDEV_BUSY;
}
@ -603,7 +601,7 @@ static uint32 GpioIrqFree(int32 pin)
int32 irqindex = -1;
irqindex = Bit2Bitnum(index->pin);
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab)){
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab)) {
return ENONESYS;
}
@ -630,17 +628,17 @@ static int32 GpioIrqEnable(x_base pin)
EXTI_InitTypeDef exit_init_structure;
irqindex = Bit2Bitnum(index->pin);
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab)){
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab)) {
return -ENONESYS;
}
x_base level = CriticalAreaLock();
if (pin_irq_hdr_tab[irqindex].pin == -1){
if (pin_irq_hdr_tab[irqindex].pin == -1) {
CriticalAreaUnLock(level);
return -ENONESYS;
}
irq = GetPinIrq(pin);
if (irq == NONE){
if (irq == NONE) {
CriticalAreaUnLock(level);
return -ENONESYS;
}
@ -649,19 +647,19 @@ static int32 GpioIrqEnable(x_base pin)
exit_init_structure.EXTI_Mode = EXTI_Mode_Interrupt;
switch (pin_irq_hdr_tab[irqindex].mode)
{
case GPIO_IRQ_EDGE_RISING:
exit_init_structure.EXTI_Trigger = EXTI_Trigger_Rising;
break;
case GPIO_IRQ_EDGE_FALLING:
exit_init_structure.EXTI_Trigger = EXTI_Trigger_Falling;
break;
case GPIO_IRQ_EDGE_BOTH:
exit_init_structure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
break;
case GPIO_IRQ_EDGE_RISING:
exit_init_structure.EXTI_Trigger = EXTI_Trigger_Rising;
break;
case GPIO_IRQ_EDGE_FALLING:
exit_init_structure.EXTI_Trigger = EXTI_Trigger_Falling;
break;
case GPIO_IRQ_EDGE_BOTH:
exit_init_structure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
break;
}
exit_init_structure.EXTI_LineCmd = ENABLE;
EXTI_Init(&exit_init_structure);
NVIC_InitStructure.NVIC_IRQChannel = irq->irq_exti_Channel;
NVIC_InitStructure.NVIC_IRQChannel = irq->irq_exti_channel;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
@ -724,7 +722,7 @@ static uint32 Stm32PinInit(void)
{
static x_bool PinInitFlag = RET_FALSE;
if(!PinInitFlag) {
if (!PinInitFlag) {
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
PinInitFlag = RET_TRUE;
}
@ -742,15 +740,15 @@ static uint32 Stm32GpioDrvConfigure(void *drv, struct BusConfigureInfo *configur
switch (configure_info->configure_cmd)
{
case OPE_INT:
ret = Stm32PinInit();
break;
case OPE_CFG:
param = (struct PinParam *)configure_info->private_data;
ret = Stm32PinConfigure(param);
break;
default:
break;
case OPE_INT:
ret = Stm32PinInit();
break;
case OPE_CFG:
param = (struct PinParam *)configure_info->private_data;
ret = Stm32PinConfigure(param);
break;
default:
break;
}
return ret;
@ -764,10 +762,9 @@ uint32 Stm32PinWrite(void *dev, struct BusBlockWriteParam *write_param)
const struct PinIndex* index = GetPin(pinstat->pin);
NULL_PARAM_CHECK(index);
if (GPIO_LOW == pinstat->val){
if (GPIO_LOW == pinstat->val) {
GPIO_ResetBits(index->gpio, index->pin);
}
else{
} else {
GPIO_SetBits(index->gpio, index->pin);
}
return EOK;
@ -781,7 +778,7 @@ uint32 Stm32PinRead(void *dev, struct BusBlockReadParam *read_param)
const struct PinIndex* index = GetPin(pinstat->pin);
NULL_PARAM_CHECK(index);
if(GPIO_ReadInputDataBit(index->gpio, index->pin) == Bit_RESET) {
if (GPIO_ReadInputDataBit(index->gpio, index->pin) == Bit_RESET) {
pinstat->val = GPIO_LOW;
} else {
pinstat->val = GPIO_HIGH;
@ -804,7 +801,7 @@ int Stm32HwGpioInit(void)
static struct PinBus pin;
ret = PinBusInit(&pin, PIN_BUS_NAME);
if(ret != EOK){
if (ret != EOK) {
KPrintf("gpio bus init error %d\n", ret);
return ERROR;
}
@ -813,12 +810,12 @@ int Stm32HwGpioInit(void)
drv.configure = &Stm32GpioDrvConfigure;
ret = PinDriverInit(&drv, PIN_DRIVER_NAME, NONE);
if(ret != EOK){
if (ret != EOK) {
KPrintf("pin driver init error %d\n", ret);
return ERROR;
}
ret = PinDriverAttachToBus(PIN_DRIVER_NAME, PIN_BUS_NAME);
if(ret != EOK) {
if (ret != EOK) {
KPrintf("pin driver attach error %d\n", ret);
return ERROR;
}
@ -827,12 +824,12 @@ int Stm32HwGpioInit(void)
dev.dev_done = &dev_done;
ret = PinDeviceRegister(&dev, NONE, PIN_DEVICE_NAME);
if(ret != EOK) {
if (ret != EOK) {
KPrintf("pin device register error %d\n", ret);
return ERROR;
}
ret = PinDeviceAttachToBus(PIN_DEVICE_NAME, PIN_BUS_NAME);
if(ret != EOK) {
if (ret != EOK) {
KPrintf("pin device register error %d\n", ret);
return ERROR;
}
@ -843,8 +840,7 @@ int Stm32HwGpioInit(void)
static __inline void PinIrqHdr(int irqno)
{
EXTI_ClearITPendingBit(Bitno2Bit(irqno));
if (pin_irq_hdr_tab[irqno].hdr)
{
if (pin_irq_hdr_tab[irqno].hdr) {
pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
}
}
@ -881,19 +877,19 @@ DECLARE_HW_IRQ(EXTI4_IRQn, EXTI4_IRQHandler, NONE);
void EXTI9_5_IRQHandler(int irq_num, void *arg)
{
if (EXTI_GetITStatus(EXTI_Line5) != RESET){
if (EXTI_GetITStatus(EXTI_Line5) != RESET) {
PinIrqHdr(5);
}
if (EXTI_GetITStatus(EXTI_Line6) != RESET){
if (EXTI_GetITStatus(EXTI_Line6) != RESET) {
PinIrqHdr(6);
}
if (EXTI_GetITStatus(EXTI_Line7) != RESET){
if (EXTI_GetITStatus(EXTI_Line7) != RESET) {
PinIrqHdr(7);
}
if (EXTI_GetITStatus(EXTI_Line8) != RESET){
if (EXTI_GetITStatus(EXTI_Line8) != RESET) {
PinIrqHdr(8);
}
if (EXTI_GetITStatus(EXTI_Line9) != RESET){
if (EXTI_GetITStatus(EXTI_Line9) != RESET) {
PinIrqHdr(9);
}
}
@ -907,10 +903,10 @@ void EXTI15_10_IRQHandler(int irq_num, void *arg)
if (EXTI_GetITStatus(EXTI_Line11) != RESET) {
PinIrqHdr(11);
}
if (EXTI_GetITStatus(EXTI_Line12) != RESET){
if (EXTI_GetITStatus(EXTI_Line12) != RESET) {
PinIrqHdr(12);
}
if (EXTI_GetITStatus(EXTI_Line13) != RESET){
if (EXTI_GetITStatus(EXTI_Line13) != RESET) {
PinIrqHdr(13);
}
if (EXTI_GetITStatus(EXTI_Line14) != RESET) {

38
board/aiit-arm32-board/third_party_driver/i2c/connect_i2c.c
View File

@ -49,11 +49,11 @@ static BusType pin;
#define SET_SDA(done, val) done->SetSdaState(done->data, val)
#define SET_SCL(done, val) done->SetSclState(done->data, val)
#define GET_SDA(done) done->GetSdaState(done->data)
#define GET_SCL(done) done->GetSclState(done->data)
#define SdaLow(done) SET_SDA(done, 0)
#define SdaHigh(done) SET_SDA(done, 1)
#define SclLow(done) SET_SCL(done, 0)
#define GET_SDA(done) done->GetSdaState(done->data)
#define GET_SCL(done) done->GetSclState(done->data)
#define SdaLow(done) SET_SDA(done, 0)
#define SdaHigh(done) SET_SDA(done, 1)
#define SclLow(done) SET_SCL(done, 0)
static void I2cGpioInit(const I2cBusParam *bus_param)
{
@ -117,7 +117,6 @@ static void I2cGpioInit(const I2cBusParam *bus_param)
i2c_sda_stat.val = GPIO_HIGH;
write_param.buffer = (void *)&i2c_sda_stat;
BusDevWriteData(pin->owner_haldev, &write_param);
}
static void SetSdaState(void *data, uint8 sda_state)
@ -192,8 +191,7 @@ static uint8 GetSclState(void *data)
ticks = us * reload / (1000000 / TICK_PER_SECOND);
told = SysTick->VAL;
while (1)
{
while (1) {
tnow = SysTick->VAL;
if (tnow != told) {
if (tnow < told) {
@ -227,8 +225,7 @@ static x_err_t I2cBusReset(const I2cBusParam *bus_param)
int32 i = 0;
if (GPIO_LOW == GetSdaState((void *)bus_param)) {
while (i++ < 9)
{
while (i++ < 9) {
SetSclState((void *)bus_param,GPIO_HIGH);
Stm32Udelay(100);
SetSclState((void *)bus_param,GPIO_LOW);
@ -258,13 +255,12 @@ static x_err_t SclHigh(struct I2cHalDrvDone *done)
SET_SCL(done, 1);
if(!done->GetSclState)
if (!done->GetSclState)
goto done;
start = CurrentTicksGain();
while (!GET_SCL(done))
{
if((CurrentTicksGain() - start) > done->timeout)
while (!GET_SCL(done)) {
if ((CurrentTicksGain() - start) > done->timeout)
return -ETIMEOUT;
DelayKTask((done->timeout + 1) >> 1);
}
@ -310,7 +306,7 @@ static __inline x_bool I2cWaitack(struct I2cHalDrvDone *done)
GET_SDA(done);
I2cDelay(done);
if(SclHigh(done) < 0) {
if (SclHigh(done) < 0) {
KPrintf("wait ack timeout");
return -ETIMEOUT;
}
@ -384,8 +380,7 @@ static x_size_t I2cSendBytes(struct I2cBus *bus, struct I2cDataStandard *msg)
int32 count = msg->len;
uint16 ignore_nack = msg->flags & I2C_IGNORE_NACK;
while (count > 0)
{
while (count > 0) {
ret = I2cWriteb(bus, *ptr);
if ((ret > 0) || (ignore_nack && (ret == 0))) {
@ -431,8 +426,7 @@ static x_size_t I2cRecvBytes(struct I2cBus *bus, struct I2cDataStandard *msg)
int32 count = msg->len;
const uint32 flags = msg->flags;
while (count > 0)
{
while (count > 0) {
val = I2cReadb(bus);
if (val >= 0) {
*ptr = val;
@ -536,8 +530,7 @@ static uint32 I2cWriteData(struct I2cHardwareDevice *i2c_dev, struct I2cDataStan
uint16 ignore_nack;
I2cStart(done);
while (NONE != msg)
{
while (NONE != msg) {
ignore_nack = msg->flags & I2C_IGNORE_NACK;
if (!(msg->flags & I2C_NO_START)) {
if (i) {
@ -579,8 +572,7 @@ static uint32 I2cReadData(struct I2cHardwareDevice *i2c_dev, struct I2cDataStand
uint16 ignore_nack;
I2cStart(done);
while (NONE != msg)
{
while (NONE != msg) {
ignore_nack = msg->flags & I2C_IGNORE_NACK;
if (!(msg->flags & I2C_NO_START)) {
if (i) {

3
board/aiit-arm32-board/third_party_driver/include/connect_can.h
View File

@ -32,13 +32,10 @@ struct Stm32Can
CAN_InitTypeDef init;
uint8 can_flag;
struct CanBus can_bus;
};
int Stm32HwCanBusInit(void);
#endif

170
board/aiit-arm32-board/third_party_driver/include/connect_ch438.h
View File

@ -33,47 +33,47 @@
#define REG_RBR0_ADDR 0x00 /* serial port0receive buffer register address */
#define REG_THR0_ADDR 0x00 /* serial port0send hold register address */
#define REG_IER0_ADDR 0x01 /* serial port0interrupt enable register address */
#define REG_IIR0_ADDR 0x02 /* serial port0interrupt identifies register address */
#define REG_IER0_ADDR 0x01 /* serial port0interrupt enable register address */
#define REG_IIR0_ADDR 0x02 /* serial port0interrupt identifies register address */
#define REG_FCR0_ADDR 0x02 /* serial port0FIFO controls register address */
#define REG_LCR0_ADDR 0x03 /* serial port0circuit control register address */
#define REG_LCR0_ADDR 0x03 /* serial port0circuit control register address */
#define REG_MCR0_ADDR 0x04 /* serial port0MODEM controls register address */
#define REG_LSR0_ADDR 0x05 /* serial port0line status register address */
#define REG_LSR0_ADDR 0x05 /* serial port0line status register address */
#define REG_MSR0_ADDR 0x06 /* serial port0address of MODEM status register */
#define REG_SCR0_ADDR 0x07 /* serial port0the user can define the register address */
#define REG_DLL0_ADDR 0x00 /* Baud rate divisor latch low 8-bit byte address */
#define REG_SCR0_ADDR 0x07 /* serial port0the user can define the register address */
#define REG_DLL0_ADDR 0x00 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM0_ADDR 0x01 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port1 register address */
#define REG_RBR1_ADDR 0x10 /* serial port1receive buffer register address */
#define REG_THR1_ADDR 0x10 /* serial port1send hold register address */
#define REG_IER1_ADDR 0x11 /* serial port1interrupt enable register address */
#define REG_IIR1_ADDR 0x12 /* serial port1interrupt identifies register address */
#define REG_IER1_ADDR 0x11 /* serial port1interrupt enable register address */
#define REG_IIR1_ADDR 0x12 /* serial port1interrupt identifies register address */
#define REG_FCR1_ADDR 0x12 /* serial port1FIFO controls register address */
#define REG_LCR1_ADDR 0x13 /* serial port1circuit control register address */
#define REG_MCR1_ADDR 0x14 /* serial port1MODEM controls register address */
#define REG_MCR1_ADDR 0x14 /* serial port1MODEM controls register address */
#define REG_LSR1_ADDR 0x15 /* serial port1line status register address */
#define REG_MSR1_ADDR 0x16 /* serial port1address of MODEM status register */
#define REG_MSR1_ADDR 0x16 /* serial port1address of MODEM status register */
#define REG_SCR1_ADDR 0x17 /* serial port1the user can define the register address */
#define REG_DLL1_ADDR 0x10 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM1_ADDR 0x11 /* Baud rate divisor latch high 8-bit byte address */
#define REG_DLM1_ADDR 0x11 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port2 register address */
#define REG_RBR2_ADDR 0x20 /* serial port2receive buffer register address */
#define REG_THR2_ADDR 0x20 /* serial port2send hold register address */
#define REG_IER2_ADDR 0x21 /* serial port2interrupt enable register address */
#define REG_IIR2_ADDR 0x22 /* serial port2interrupt identifies register address */
#define REG_IER2_ADDR 0x21 /* serial port2interrupt enable register address */
#define REG_IIR2_ADDR 0x22 /* serial port2interrupt identifies register address */
#define REG_FCR2_ADDR 0x22 /* serial port2FIFO controls register address */
#define REG_LCR2_ADDR 0x23 /* serial port2circuit control register address */
#define REG_MCR2_ADDR 0x24 /* serial port2MODEM controls register address */
#define REG_MCR2_ADDR 0x24 /* serial port2MODEM controls register address */
#define REG_LSR2_ADDR 0x25 /* serial port2line status register address */
#define REG_MSR2_ADDR 0x26 /* serial port2address of MODEM status register */
#define REG_MSR2_ADDR 0x26 /* serial port2address of MODEM status register */
#define REG_SCR2_ADDR 0x27 /* serial port2the user can define the register address */
#define REG_DLL2_ADDR 0x20 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM2_ADDR 0x21 /* Baud rate divisor latch high 8-bit byte address */
#define REG_DLM2_ADDR 0x21 /* Baud rate divisor latch high 8-bit byte address */
@ -81,32 +81,32 @@
#define REG_RBR3_ADDR 0x30 /* serial port3receive buffer register address */
#define REG_THR3_ADDR 0x30 /* serial port3send hold register address */
#define REG_IER3_ADDR 0x31 /* serial port3interrupt enable register address */
#define REG_IIR3_ADDR 0x32 /* serial port3interrupt identifies register address */
#define REG_IER3_ADDR 0x31 /* serial port3interrupt enable register address */
#define REG_IIR3_ADDR 0x32 /* serial port3interrupt identifies register address */
#define REG_FCR3_ADDR 0x32 /* serial port3FIFO controls register address */
#define REG_LCR3_ADDR 0x33 /* serial port3circuit control register address */
#define REG_MCR3_ADDR 0x34 /* serial port3MODEM controls register address */
#define REG_MCR3_ADDR 0x34 /* serial port3MODEM controls register address */
#define REG_LSR3_ADDR 0x35 /* serial port3line status register address */
#define REG_MSR3_ADDR 0x36 /* serial port3address of MODEM status register */
#define REG_MSR3_ADDR 0x36 /* serial port3address of MODEM status register */
#define REG_SCR3_ADDR 0x37 /* serial port3the user can define the register address */
#define REG_DLL3_ADDR 0x30 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM3_ADDR 0x31 /* Baud rate divisor latch high 8-bit byte address */
#define REG_DLM3_ADDR 0x31 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port4 register address */
#define REG_RBR4_ADDR 0x08 /* serial port4receive buffer register address */
#define REG_THR4_ADDR 0x08 /* serial port4send hold register address */
#define REG_IER4_ADDR 0x09 /* serial port4interrupt enable register address */
#define REG_IIR4_ADDR 0x0A /* serial port4interrupt identifies register address */
#define REG_IER4_ADDR 0x09 /* serial port4interrupt enable register address */
#define REG_IIR4_ADDR 0x0A /* serial port4interrupt identifies register address */
#define REG_FCR4_ADDR 0x0A /* serial port4FIFO controls register address */
#define REG_LCR4_ADDR 0x0B /* serial port4circuit control register address */
#define REG_MCR4_ADDR 0x0C /* serial port4MODEM controls register address */
#define REG_MCR4_ADDR 0x0C /* serial port4MODEM controls register address */
#define REG_LSR4_ADDR 0x0D /* serial port4line status register address */
#define REG_MSR4_ADDR 0x0E /* serial port4address of MODEM status register */
#define REG_MSR4_ADDR 0x0E /* serial port4address of MODEM status register */
#define REG_SCR4_ADDR 0x0F /* serial port4the user can define the register address */
#define REG_DLL4_ADDR 0x08 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM4_ADDR 0x09 /* Baud rate divisor latch high 8-bit byte address */
#define REG_DLM4_ADDR 0x09 /* Baud rate divisor latch high 8-bit byte address */
@ -114,48 +114,48 @@
#define REG_RBR5_ADDR 0x18 /* serial port5receive buffer register address */
#define REG_THR5_ADDR 0x18 /* serial port5send hold register address */
#define REG_IER5_ADDR 0x19 /* serial port5interrupt enable register address */
#define REG_IIR5_ADDR 0x1A /* serial port5interrupt identifies register address */
#define REG_IER5_ADDR 0x19 /* serial port5interrupt enable register address */
#define REG_IIR5_ADDR 0x1A /* serial port5interrupt identifies register address */
#define REG_FCR5_ADDR 0x1A /* serial port5FIFO controls register address */
#define REG_LCR5_ADDR 0x1B /* serial port5circuit control register address */
#define REG_MCR5_ADDR 0x1C /* serial port5MODEM controls register address */
#define REG_MCR5_ADDR 0x1C /* serial port5MODEM controls register address */
#define REG_LSR5_ADDR 0x1D /* serial port5line status register address */
#define REG_MSR5_ADDR 0x1E /* serial port5address of MODEM status register */
#define REG_MSR5_ADDR 0x1E /* serial port5address of MODEM status register */
#define REG_SCR5_ADDR 0x1F /* serial port5the user can define the register address */
#define REG_DLL5_ADDR 0x18 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM5_ADDR 0x19 /* Baud rate divisor latch high 8-bit byte address */
#define REG_DLM5_ADDR 0x19 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port6 register address */
#define REG_RBR6_ADDR 0x28 /* serial port6receive buffer register address */
#define REG_THR6_ADDR 0x28 /* serial port6send hold register address */
#define REG_IER6_ADDR 0x29 /* serial port6interrupt enable register address */
#define REG_IIR6_ADDR 0x2A /* serial port6interrupt identifies register address */
#define REG_IER6_ADDR 0x29 /* serial port6interrupt enable register address */
#define REG_IIR6_ADDR 0x2A /* serial port6interrupt identifies register address */
#define REG_FCR6_ADDR 0x2A /* serial port6FIFO controls register address */
#define REG_LCR6_ADDR 0x2B /* serial port6circuit control register address */
#define REG_MCR6_ADDR 0x2C /* serial port6MODEM controls register address */
#define REG_MCR6_ADDR 0x2C /* serial port6MODEM controls register address */
#define REG_LSR6_ADDR 0x2D /* serial port6line status register address */
#define REG_MSR6_ADDR 0x2E /* serial port6address of MODEM status register */
#define REG_MSR6_ADDR 0x2E /* serial port6address of MODEM status register */
#define REG_SCR6_ADDR 0x2F /* serial port6the user can define the register address */
#define REG_DLL6_ADDR 0x28 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM6_ADDR 0x29 /* Baud rate divisor latch high 8-bit byte address */
#define REG_DLM6_ADDR 0x29 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port7 register address */
#define REG_RBR7_ADDR 0x38 /* serial port7receive buffer register address */
#define REG_THR7_ADDR 0x38 /* serial port7send hold register address */
#define REG_IER7_ADDR 0x39 /* serial port7interrupt enable register address */
#define REG_IIR7_ADDR 0x3A /* serial port7interrupt identifies register address */
#define REG_IER7_ADDR 0x39 /* serial port7interrupt enable register address */
#define REG_IIR7_ADDR 0x3A /* serial port7interrupt identifies register address */
#define REG_FCR7_ADDR 0x3A /* serial port7FIFO controls register address */
#define REG_LCR7_ADDR 0x3B /* serial port7circuit control register address */
#define REG_MCR7_ADDR 0x3C /* serial port7MODEM controls register address */
#define REG_MCR7_ADDR 0x3C /* serial port7MODEM controls register address */
#define REG_LSR7_ADDR 0x3D /* serial port7line status register address */
#define REG_MSR7_ADDR 0x3E /* serial port7address of MODEM status register */
#define REG_MSR7_ADDR 0x3E /* serial port7address of MODEM status register */
#define REG_SCR7_ADDR 0x3F /* serial port7the user can define the register address */
#define REG_DLL7_ADDR 0x38 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM7_ADDR 0x39 /* Baud rate divisor latch high 8-bit byte address */
#define REG_DLM7_ADDR 0x39 /* Baud rate divisor latch high 8-bit byte address */
#define REG_SSR_ADDR 0x4F /* pecial status register address */
@ -163,14 +163,14 @@
/* IER register bit */
#define BIT_IER_RESET 0x80 /* The bit is 1 soft reset serial port */
#define BIT_IER_RESET 0x80 /* The bit is 1 soft reset serial port */
#define BIT_IER_LOWPOWER 0x40 /* The bit is 1 close serial port internal reference clock */
#define BIT_IER_SLP 0x20 /* serial port0 is SLP, 1 close clock vibrator */
#define BIT_IER1_CK2X 0x20 /* serial port1 is CK2X, 1 force the external clock signal after 2 times as internal reference clock */
#define BIT_IER_IEMODEM 0x08 /* The bit is 1 allows MODEM input status to interrupt */
#define BIT_IER_IELINES 0x04 /* The bit is 1 allow receiving line status to be interrupted */
#define BIT_IER_IETHRE 0x02 /* The bit is 1 allows the send hold register to break in mid-air */
#define BIT_IER_IERECV 0x01 /* The bit is 1 allows receiving data interrupts */
#define BIT_IER_SLP 0x20 /* serial port0 is SLP, 1 close clock vibrator */
#define BIT_IER1_CK2X 0x20 /* serial port1 is CK2X, 1 force the external clock signal after 2 times as internal reference clock */
#define BIT_IER_IEMODEM 0x08 /* The bit is 1 allows MODEM input status to interrupt */
#define BIT_IER_IELINES 0x04 /* The bit is 1 allow receiving line status to be interrupted */
#define BIT_IER_IETHRE 0x02 /* The bit is 1 allows the send hold register to break in mid-air */
#define BIT_IER_IERECV 0x01 /* The bit is 1 allows receiving data interrupts */
/* IIR register bit */
@ -182,7 +182,7 @@
#define BIT_IIR_IID3 0x08
#define BIT_IIR_IID2 0x04
#define BIT_IIR_IID1 0x02
#define BIT_IIR_NOINT 0x01
#define BIT_IIR_NOINT 0x01
/* FCR register bit */
@ -192,18 +192,18 @@
#define BIT_FCR_TFIFORST 0x04 /* The bit is 1 empty the data sent in FIFO */
#define BIT_FCR_RFIFORST 0x02 /* The bit is 1 empty the data sent in FIFO */
#define BIT_FCR_FIFOEN 0x01 /* The bit is 1 use FIFO, 0 disable FIFO */
#define BIT_FCR_FIFOEN 0x01 /* The bit is 1 use FIFO, 0 disable FIFO */
/* LCR register bit */
#define BIT_LCR_DLAB 0x80 /* To access DLL, DLM, 0 to access RBR/THR/IER */
#define BIT_LCR_DLAB 0x80 /* To access DLL, DLM, 0 to access RBR/THR/IER */
#define BIT_LCR_BREAKEN 0x40 /* 1 forces a BREAK line interval*/
/* Set the check format: when PAREN is 1, 00 odd check, 01 even check, 10 MARK (set 1), 11 blank (SPACE, clear 0) */
#define BIT_LCR_PARMODE1 0x20 /* Sets the parity bit format */
#define BIT_LCR_PARMODE0 0x10 /* Sets the parity bit format */
#define BIT_LCR_PAREN 0x08 /* A value of 1 allows you to generate and receive parity bits when sending */
#define BIT_LCR_PAREN 0x08 /* A value of 1 allows you to generate and receive parity bits when sending */
#define BIT_LCR_STOPBIT 0x04 /* If is 1, then two stop bits, is 0, a stop bit */
/* Set word length: 00 for 5 data bits, 01 for 6 data bits, 10 for 7 data bits and 11 for 8 data bits */
@ -212,42 +212,42 @@
/* MCR register bit */
#define BIT_MCR_AFE 0x20 /* For 1 allows automatic flow control of CTS and RTS hardware */
#define BIT_MCR_AFE 0x20 /* For 1 allows automatic flow control of CTS and RTS hardware */
#define BIT_MCR_LOOP 0x10 /* Is the test mode of 1 enabling internal loop */
#define BIT_MCR_OUT2 0x08 /* 1 Allows an interrupt request for the serial port output */
#define BIT_MCR_OUT1 0x04 /* The MODEM control bit defined for the user */
#define BIT_MCR_RTS 0x02 /* The bit is 1 RTS pin output effective */
#define BIT_MCR_DTR 0x01 /* The bit is 1 DTR pin output effective */
#define BIT_MCR_RTS 0x02 /* The bit is 1 RTS pin output effective */
#define BIT_MCR_DTR 0x01 /* The bit is 1 DTR pin output effective */
/* LSR register bit */
#define BIT_LSR_RFIFOERR 0x80 /* 1 said There is at least one error in receiving FIFO */
#define BIT_LSR_TEMT 0x40 /* 1 said THR and TSR are empty */
#define BIT_LSR_THRE 0x20 /* 1 said THR is empty*/
#define BIT_LSR_TEMT 0x40 /* 1 said THR and TSR are empty */
#define BIT_LSR_THRE 0x20 /* 1 said THR is empty*/
#define BIT_LSR_BREAKINT 0x10 /* The bit is 1 said the BREAK line interval was detected*/
#define BIT_LSR_FRAMEERR 0x08 /* The bit is 1 said error reading data frame */
#define BIT_LSR_PARERR 0x04 /* The bit is 1 said parity error */
#define BIT_LSR_OVERR 0x02 /* 1 said receive FIFO buffer overflow */
#define BIT_LSR_DATARDY 0x01 /* The bit is 1 said receive data received in FIFO */
#define BIT_LSR_FRAMEERR 0x08 /* The bit is 1 said error reading data frame */
#define BIT_LSR_PARERR 0x04 /* The bit is 1 said parity error */
#define BIT_LSR_OVERR 0x02 /* 1 said receive FIFO buffer overflow */
#define BIT_LSR_DATARDY 0x01 /* The bit is 1 said receive data received in FIFO */
/* MSR register bit */
#define BIT_MSR_DCD 0x80 /* The bit is 1 said DCD pin effective */
#define BIT_MSR_RI 0x40 /* The bit is 1 said RI pin effective */
#define BIT_MSR_RI 0x40 /* The bit is 1 said RI pin effective */
#define BIT_MSR_DSR 0x20 /* The bit is 1 said DSR pin effective */
#define BIT_MSR_CTS 0x10 /* The bit is 1 said CTS pin effective */
#define BIT_MSR_DDCD 0x08 /* The bit is 1 said DCD pin The input state has changed */
#define BIT_MSR_CTS 0x10 /* The bit is 1 said CTS pin effective */
#define BIT_MSR_DDCD 0x08 /* The bit is 1 said DCD pin The input state has changed */
#define BIT_MSR_TERI 0x04 /* The bit is 1 said RI pin The input state has changed */
#define BIT_MSR_DDSR 0x02 /* The bit is 1 said DSR pin The input state has changed */
#define BIT_MSR_DCTS 0x01 /* The bit is 1 said CTS pin The input state has changed */
#define BIT_MSR_DDSR 0x02 /* The bit is 1 said DSR pin The input state has changed */
#define BIT_MSR_DCTS 0x01 /* The bit is 1 said CTS pin The input state has changed */
/* Interrupt status code */
#define INT_NOINT 0x01 /* There is no interruption */
#define INT_THR_EMPTY 0x02 /* THR empty interruption */
#define INT_RCV_OVERTIME 0x0C /* Receive timeout interrupt */
#define INT_RCV_SUCCESS 0x04 /* Interrupts are available to receive data */
#define INT_RCV_LINES 0x06 /* Receiving line status interrupted */
#define INT_NOINT 0x01 /* There is no interruption */
#define INT_THR_EMPTY 0x02 /* THR empty interruption */
#define INT_RCV_OVERTIME 0x0C /* Receive timeout interrupt */
#define INT_RCV_SUCCESS 0x04 /* Interrupts are available to receive data */
#define INT_RCV_LINES 0x06 /* Receiving line status interrupted */
#define INT_MODEM_CHANGE 0x00 /* MODEM input changes interrupt */
#define CH438_IIR_FIFOS_ENABLED 0xC0 /* use FIFO */
@ -269,21 +269,21 @@
#define CH438_ALE_PIN GET_PIN(B,2)
#define CH438_INT_PIN GET_PIN(C,13)
#endif
#define CH438_D0_PIN 1
#define CH438_D1_PIN 2
#define CH438_D2_PIN 3
#define CH438_D3_PIN 4
#define CH438_D4_PIN 5
#define CH438_D5_PIN 18
#define CH438_D6_PIN 19
#define CH438_D7_PIN 20
#define CH438_D0_PIN 1
#define CH438_D1_PIN 2
#define CH438_D2_PIN 3
#define CH438_D3_PIN 4
#define CH438_D4_PIN 5
#define CH438_D5_PIN 18
#define CH438_D6_PIN 19
#define CH438_D7_PIN 20
#define CH438_NWR_PIN 44
#define CH438_NRD_PIN 45
#define CH438_NCS_PIN 47
#define CH438_ALE_PIN 48
#define CH438_INT_PIN 7
#define DIR_485CH1_PIN 22 //485ch1 = ext_uart3
#define DIR_485CH2_PIN 21 //485ch2 = ext_uart2
#define CH438_NRD_PIN 45
#define CH438_NCS_PIN 47
#define CH438_ALE_PIN 48
#define CH438_INT_PIN 7
#define DIR_485CH1_PIN 22 //485ch1 = ext_uart3
#define DIR_485CH2_PIN 21 //485ch2 = ext_uart2
#define DIR_485CH3_PIN 123 //485ch3 = ext_uart7
void CH438RegTest(unsigned char num);

6
board/aiit-arm32-board/third_party_driver/include/connect_spi.h
View File

@ -54,7 +54,7 @@ struct Stm32Spi
{
SPI_TypeDef *instance;
char *BusName;
char *bus_name;
SPI_InitTypeDef init;
@ -65,11 +65,11 @@ struct Stm32Spi
}dma;
uint8 spi_dma_flag;
struct SpiBus SpiBus;
struct SpiBus spi_bus;
};
int Stm32HwSpiInit(void);
x_err_t HwSpiDeviceAttach(const char *BusName, const char *device_name, GPIO_TypeDef *cs_gpiox, uint16_t cs_gpio_pin);
x_err_t HwSpiDeviceAttach(const char *bus_name, const char *device_name, GPIO_TypeDef *cs_gpiox, uint16_t cs_gpio_pin);
#ifdef __cplusplus
}

45
board/aiit-arm32-board/third_party_driver/include/connect_touch.h
View File

@ -20,7 +20,7 @@
#include <stm32f4xx.h>
#define BITBAND(addr, bitnum) ((addr & 0xF0000000)+0x2000000+((addr &0xFFFFF)<<5)+(bitnum<<2))
#define MEM_ADDR(addr) *((volatile unsigned long *)(addr))
#define MEM_ADDR(addr) (*((volatile unsigned long *)(addr)))
#define BIT_ADDR(addr, bitnum) MEM_ADDR(BITBAND(addr, bitnum))
#define GPIOA_ODR_Addr (GPIOA_BASE+20) //0x40020014
@ -31,7 +31,7 @@
#define GPIOF_ODR_Addr (GPIOF_BASE+20) //0x40021414
#define GPIOG_ODR_Addr (GPIOG_BASE+20) //0x40021814
#define GPIOH_ODR_Addr (GPIOH_BASE+20) //0x40021C14
#define GPIOI_ODR_Addr (GPIOI_BASE+20) //0x40022014
#define GPIOI_ODR_Addr (GPIOI_BASE+20) //0x40022014
#define GPIOA_IDR_Addr (GPIOA_BASE+16) //0x40020010
#define GPIOB_IDR_Addr (GPIOB_BASE+16) //0x40020410
@ -41,38 +41,38 @@
#define GPIOF_IDR_Addr (GPIOF_BASE+16) //0x40021410
#define GPIOG_IDR_Addr (GPIOG_BASE+16) //0x40021810
#define GPIOH_IDR_Addr (GPIOH_BASE+16) //0x40021C10
#define GPIOI_IDR_Addr (GPIOI_BASE+16) //0x40022010
#define GPIOI_IDR_Addr (GPIOI_BASE+16) //0x40022010
#define PAout(n) BIT_ADDR(GPIOA_ODR_Addr,n) //output
#define PAin(n) BIT_ADDR(GPIOA_IDR_Addr,n) //input
#define PAin(n) BIT_ADDR(GPIOA_IDR_Addr,n) //input
#define PBout(n) BIT_ADDR(GPIOB_ODR_Addr,n) //output
#define PBin(n) BIT_ADDR(GPIOB_IDR_Addr,n) //input
#define PBin(n) BIT_ADDR(GPIOB_IDR_Addr,n) //input
#define PCout(n) BIT_ADDR(GPIOC_ODR_Addr,n) //output
#define PCin(n) BIT_ADDR(GPIOC_IDR_Addr,n) //input
#define PCin(n) BIT_ADDR(GPIOC_IDR_Addr,n) //input
#define PDout(n) BIT_ADDR(GPIOD_ODR_Addr,n) //output
#define PDin(n) BIT_ADDR(GPIOD_IDR_Addr,n) //input
#define PDin(n) BIT_ADDR(GPIOD_IDR_Addr,n) //input
#define PEout(n) BIT_ADDR(GPIOE_ODR_Addr,n) //output
#define PEin(n) BIT_ADDR(GPIOE_IDR_Addr,n) //input
#define PEin(n) BIT_ADDR(GPIOE_IDR_Addr,n) //input
#define PFout(n) BIT_ADDR(GPIOF_ODR_Addr,n) //output
#define PFin(n) BIT_ADDR(GPIOF_IDR_Addr,n) //input
#define PFin(n) BIT_ADDR(GPIOF_IDR_Addr,n) //input
#define PGout(n) BIT_ADDR(GPIOG_ODR_Addr,n) //output
#define PGin(n) BIT_ADDR(GPIOG_IDR_Addr,n) //input
#define PGin(n) BIT_ADDR(GPIOG_IDR_Addr,n) //input
#define PHout(n) BIT_ADDR(GPIOH_ODR_Addr,n) //output
#define PHin(n) BIT_ADDR(GPIOH_IDR_Addr,n) //input
#define PHin(n) BIT_ADDR(GPIOH_IDR_Addr,n) //input
#define PIout(n) BIT_ADDR(GPIOI_ODR_Addr,n) //output
#define PIin(n) BIT_ADDR(GPIOI_IDR_Addr,n) //input
#define PIin(n) BIT_ADDR(GPIOI_IDR_Addr,n) //input
#define TP_PRES_DOWN 0x80
#define TP_CATH_PRES 0x40
#define TP_CATH_PRES 0x40
//touch screen control struct
typedef struct
@ -90,20 +90,21 @@ typedef struct
extern touch_device_info tp_dev;
//save data struct
typedef struct {
s32 ty_xfac;
s32 ty_yfac;
short x_pos;
short y_pos;
u8 iic_touchtype;
typedef struct
{
s32 ty_xfac;
s32 ty_yfac;
short x_pos;
short y_pos;
u8 iic_touchtype;
u8 iic_flag;
}TP_modify_save;
//io pin define
#define PEN PDin(6)
#define T_MISO PBin(4)
#define T_MOSI PBout(5)
#define T_CLK PBout(3)
#define T_MISO PBin(4)
#define T_MOSI PBout(5)
#define T_CLK PBout(3)
#define TCS PGout(13)
int Stm32HwTouchBusInit(void);

6
board/aiit-arm32-board/third_party_driver/include/connect_usart.h
View File

@ -29,8 +29,8 @@
extern "C" {
#endif
#define KERNEL_CONSOLE_BUS_NAME SERIAL_BUS_NAME_1
#define KERNEL_CONSOLE_DRV_NAME SERIAL_DRV_NAME_1
#define KERNEL_CONSOLE_BUS_NAME SERIAL_BUS_NAME_1
#define KERNEL_CONSOLE_DRV_NAME SERIAL_DRV_NAME_1
#define KERNEL_CONSOLE_DEVICE_NAME SERIAL_1_DEVICE_NAME_0
struct UsartHwCfg
@ -51,7 +51,7 @@ struct Stm32Usart
x_size_t LastRecvIndex;
} dma;
struct SerialBus SerialBus;
struct SerialBus serial_bus;
};
int Stm32HwUsartInit(void);

2
board/aiit-arm32-board/third_party_driver/rtc/connect_rtc.c
View File

@ -95,7 +95,7 @@ static uint32 RtcConfigure(void *drv, struct BusConfigureInfo *configure_info)
rtc_date_structure.RTC_Date = tm_new.tm_mday;
rtc_date_structure.RTC_WeekDay = GetWeekDay(tm_new.tm_year+1900,tm_new.tm_mon+1,tm_new.tm_mday);
RTC_SetDate(RTC_Format_BIN, &rtc_date_structure);
if (tm_new.tm_hour > 11){
if (tm_new.tm_hour > 11) {
rtc_time_structure.RTC_H12 = RTC_H12_PM;
}
else{

73
board/aiit-arm32-board/third_party_driver/sdio/connect_sdio.c
View File

@ -40,15 +40,14 @@ static uint32 SdioConfigure(void *drv, struct BusConfigureInfo *ConfigureInfo)
NULL_PARAM_CHECK(drv);
NULL_PARAM_CHECK(ConfigureInfo);
if(ConfigureInfo->configure_cmd == OPER_BLK_GETGEOME)
{
if (ConfigureInfo->configure_cmd == OPER_BLK_GETGEOME) {
NULL_PARAM_CHECK(ConfigureInfo->private_data);
struct DeviceBlockArrange *args = (struct DeviceBlockArrange *)ConfigureInfo->private_data;
SD_GetCardInfo(&SDCardInfo);
args->size_perbank = SDCardInfo.CardBlockSize;
args->block_size = SDCardInfo.CardBlockSize;
if(SDCardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD)
if (SDCardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD)
args->bank_num = (SDCardInfo.SD_csd.DeviceSize + 1) * 1024;
else
args->bank_num = SDCardInfo.CardCapacity;
@ -64,13 +63,11 @@ static uint32 SdioOpen(void *dev)
{
NULL_PARAM_CHECK(dev);
if(SDLock >= 0)
{
if (SDLock >= 0) {
KSemaphoreDelete(SDLock);
}
SDLock = KSemaphoreCreate(1);
if (SDLock < 0)
{
if (SDLock < 0) {
return ERROR;
}
@ -92,26 +89,22 @@ static uint32 SdioRead(void *dev, struct BusBlockReadParam *read_param)
KSemaphoreObtain(SDLock, WAITING_FOREVER);
if(((uint32)read_param->buffer & 0x03) != 0)
{
if (((uint32)read_param->buffer & 0x03) != 0) {
uint64_t sector;
uint8_t* temp;
sector = (uint64_t)read_param->pos * SDCARD_SECTOR_SIZE;
temp = (uint8_t*)read_param->buffer;
for (uint8 i = 0; i < read_param->size; i++)
{
for (uint8 i = 0; i < read_param->size; i++) {
ret = SD_ReadBlock((uint8_t *)SDBuffer, sector, 1);
if(ret != SD_OK)
{
if (ret != SD_OK) {
KPrintf("read failed: %d, buffer 0x%08x\n", ret, temp);
return 0;
}
#if defined (SD_DMA_MODE)
ret = SD_WaitReadOperation();
if(ret != SD_OK)
{
if (ret != SD_OK) {
KPrintf("read failed: %d, buffer 0x%08x\n", ret, temp);
return 0;
}
@ -121,19 +114,15 @@ static uint32 SdioRead(void *dev, struct BusBlockReadParam *read_param)
sector += SDCARD_SECTOR_SIZE;
temp += SDCARD_SECTOR_SIZE;
}
}
else
{
} else {
ret = SD_ReadBlock((uint8_t *)read_param->buffer, (uint64_t)read_param->pos * SDCARD_SECTOR_SIZE, read_param->size);
if(ret != SD_OK)
{
if (ret != SD_OK) {
KPrintf("read failed: %d, buffer 0x%08x\n", ret, (uint8_t *)read_param->buffer);
return 0;
}
#if defined (SD_DMA_MODE)
ret = SD_WaitReadOperation();
if(ret != SD_OK)
{
if (ret != SD_OK) {
KPrintf("read failed: %d, buffer 0x%08x\n", ret, (uint8_t *)read_param->buffer);
return 0;
}
@ -151,28 +140,24 @@ static uint32 SdioWrite(void *dev, struct BusBlockWriteParam *write_param)
KSemaphoreObtain(SDLock, WAITING_FOREVER);
if(((uint32)write_param->buffer & 0x03) != 0)
{
if (((uint32)write_param->buffer & 0x03) != 0) {
uint64_t sector;
uint8_t* temp;
sector = (uint64_t)write_param->pos * SDCARD_SECTOR_SIZE;
temp = (uint8_t*)write_param->buffer;
for (uint8 i = 0; i < write_param->size; i++)
{
for (uint8 i = 0; i < write_param->size; i++) {
memcpy(SDBuffer, temp, SDCARD_SECTOR_SIZE);
ret = SD_WriteBlock((uint8_t *)SDBuffer, sector, 1);
if(ret != SD_OK)
{
if (ret != SD_OK) {
KPrintf("write failed: %d, buffer 0x%08x\n", ret, temp);
return 0;
}
#if defined (SD_DMA_MODE)
ret = SD_WaitWriteOperation();
if(ret != SD_OK)
{
if (ret != SD_OK) {
KPrintf("write failed: %d, buffer 0x%08x\n", ret, temp);
return 0;
}
@ -180,19 +165,15 @@ static uint32 SdioWrite(void *dev, struct BusBlockWriteParam *write_param)
sector += SDCARD_SECTOR_SIZE;
temp += SDCARD_SECTOR_SIZE;
}
}
else
{
} else {
ret = SD_WriteBlock((uint8_t *)write_param->buffer, (uint64_t)write_param->pos * SDCARD_SECTOR_SIZE, write_param->size);
if(ret != SD_OK)
{
if (ret != SD_OK) {
KPrintf("write failed: %d, buffer 0x%08x\n", ret, (uint8_t *)write_param->buffer);
return 0;
}
#if defined (SD_DMA_MODE)
ret = SD_WaitWriteOperation();
if(ret != SD_OK)
{
if (ret != SD_OK) {
KPrintf("write failed: %d, buffer 0x%08x\n", ret, (uint8_t *)write_param->buffer);
return 0;
}
@ -220,42 +201,36 @@ int HwSdioInit(void)
x_err_t ret = EOK;
ret = SD_Init();
if(ret != SD_OK)
{
if (ret != SD_OK) {
KPrintf("SD init failed!");
return ERROR;
}
ret = SdioBusInit(&bus, SDIO_BUS_NAME);
if(ret != EOK)
{
if (ret != EOK) {
KPrintf("Sdio bus init error %d\n", ret);
return ERROR;
}
ret = SdioDriverInit(&drv, SDIO_DRIVER_NAME);
if(ret != EOK)
{
if (ret != EOK) {
KPrintf("Sdio driver init error %d\n", ret);
return ERROR;
}
ret = SdioDriverAttachToBus(SDIO_DRIVER_NAME, SDIO_BUS_NAME);
if(ret != EOK)
{
if (ret != EOK) {
KPrintf("Sdio driver attach error %d\n", ret);
return ERROR;
}
dev.dev_done = &dev_done;
ret = SdioDeviceRegister(&dev, SDIO_DEVICE_NAME);
if(ret != EOK)
{
if (ret != EOK) {
KPrintf("Sdio device register error %d\n", ret);
return ERROR;
}
ret = SdioDeviceAttachToBus(SDIO_DEVICE_NAME, SDIO_BUS_NAME);
if(ret != EOK)
{
if (ret != EOK) {
KPrintf("Sdio device register error %d\n", ret);
return ERROR;
}

6
board/aiit-arm32-board/third_party_driver/spi/connect_flash_spi.c
View File

@ -42,13 +42,11 @@ int FlashW25qxxSpiDeviceInit(void)
tmpreg = RCC->AHB1ENR & RCC_AHB1ENR_GPIOBEN;
(void)tmpreg;
if(EOK != HwSpiDeviceAttach(SPI_BUS_NAME_1, "spi1_dev0", GPIOB, GPIO_Pin_0))
{
if (EOK != HwSpiDeviceAttach(SPI_BUS_NAME_1, "spi1_dev0", GPIOB, GPIO_Pin_0)) {
return ERROR;
}
if(NONE == SpiFlashInit(SPI_BUS_NAME_1, "spi1_dev0", SPI_1_DRV_NAME, "W25Q64"))
{
if (NONE == SpiFlashInit(SPI_BUS_NAME_1, "spi1_dev0", SPI_1_DRV_NAME, "W25Q64")) {
return ERROR;
}

264
board/aiit-arm32-board/third_party_driver/spi/connect_spi.c
View File

@ -251,7 +251,7 @@ static x_err_t Stm32SpiInit(struct Stm32Spi *SpiDrv, struct SpiMasterParam *cfg)
/**
* This function Use DMA during spi transfer
*
* @param SpiBus SPI bus handle
* @param spi_bus SPI bus handle
*
* @param SettingLen Set data length
*
@ -262,9 +262,9 @@ static x_err_t Stm32SpiInit(struct Stm32Spi *SpiDrv, struct SpiMasterParam *cfg)
* @return none
*/
static void DmaSpiConfig(struct SpiBus *SpiBus, uint32_t setting_len, void *rx_base_addr, void *tx_base_addr)
static void DmaSpiConfig(struct SpiBus *spi_bus, uint32_t setting_len, void *rx_base_addr, void *tx_base_addr)
{
struct Stm32Spi *spi = (struct Stm32Spi *)SpiBus->private_data;
struct Stm32Spi *spi = (struct Stm32Spi *)spi_bus->private_data;
uint32 tmpreg = 0x00U;
NVIC_InitTypeDef NVIC_InitStructure;
@ -351,13 +351,13 @@ static void DmaSpiConfig(struct SpiBus *SpiBus, uint32_t setting_len, void *rx_b
/**
* This function DMA receiving completion interrupt
*
* @param SpiBus SPI bus pointer
* @param spi_bus SPI bus pointer
*
* @return none
*/
static void DmaRxDoneIsr(struct SpiBus *SpiBus)
static void DmaRxDoneIsr(struct SpiBus *spi_bus)
{
struct Stm32Spi *spi = (struct Stm32Spi *) SpiBus->bus.private_data;
struct Stm32Spi *spi = (struct Stm32Spi *) spi_bus->bus.private_data;
x_size_t recv_len;
x_base level;
@ -375,13 +375,13 @@ static void DmaRxDoneIsr(struct SpiBus *SpiBus)
/**
* This function DMA sending completion interrupt
*
* @param SpiBus SPI bus pointer
* @param spi_bus SPI bus pointer
*
* @return none
*/
static void DmaTxDoneIsr(struct SpiBus *SpiBus)
static void DmaTxDoneIsr(struct SpiBus *spi_bus)
{
struct Stm32Spi *spi = (struct Stm32Spi *) SpiBus->bus.private_data;
struct Stm32Spi *spi = (struct Stm32Spi *) spi_bus->bus.private_data;
x_size_t send_len;
x_base level;
@ -1158,27 +1158,23 @@ static uint32 Stm32SpiWriteData(struct SpiHardwareDevice *spi_dev, struct SpiDat
NULL_PARAM_CHECK(spi_dev);
NULL_PARAM_CHECK(spi_datacfg);
struct Stm32Spi *StmSpi = CONTAINER_OF(spi_dev->haldev.owner_bus, struct Stm32Spi, SpiBus);
struct Stm32Spi *StmSpi = CONTAINER_OF(spi_dev->haldev.owner_bus, struct Stm32Spi, spi_bus);
SPI_TypeDef *SpiInstance = StmSpi->instance;
SPI_InitTypeDef *SpiInit = &StmSpi->init;
struct Stm32HwSpiCs *cs = (struct Stm32HwSpiCs *)spi_dev->haldev.private_data;
struct Stm32HwSpiCs *cs = (struct Stm32HwSpiCs *)spi_dev->private_data;
while(NONE != spi_datacfg)
{
if(spi_datacfg->spi_chip_select)
{
while(NONE != spi_datacfg) {
if (spi_datacfg->spi_chip_select) {
GPIO_WriteBit(cs->GPIOx, cs->GPIO_Pin, Bit_RESET);
}
message_length = spi_datacfg->length;
WriteBuf = spi_datacfg->tx_buff;
while (message_length)
{
while (message_length) {
if (message_length > 65535) {
send_length = 65535;
message_length = message_length - 65535;
}
else{
} else {
send_length = message_length;
message_length = 0;
}
@ -1188,12 +1184,10 @@ static uint32 Stm32SpiWriteData(struct SpiHardwareDevice *spi_dev, struct SpiDat
WriteBuf = (uint8 *)spi_datacfg->tx_buff + already_send_length;
/* start once data exchange in DMA mode */
if (spi_datacfg->tx_buff)
{
if (spi_datacfg->tx_buff) {
if (StmSpi->spi_dma_flag & SPI_USING_TX_DMA_FLAG) {
state = SpiTransmitDma(*SpiInit, SpiInstance, StmSpi->dma.dma_tx.init, StmSpi->dma.dma_tx.instance, (uint8_t *)WriteBuf, send_length);
}
else{
} else {
state = SpiTransmit(*SpiInit, SpiInstance, (uint8_t *)WriteBuf, send_length, 1000);
}
}
@ -1204,7 +1198,7 @@ static uint32 Stm32SpiWriteData(struct SpiHardwareDevice *spi_dev, struct SpiDat
}
}
if (spi_datacfg->spi_cs_release){
if (spi_datacfg->spi_cs_release) {
GPIO_WriteBit(cs->GPIOx, cs->GPIO_Pin, Bit_SET);
}
@ -1233,26 +1227,23 @@ static uint32 Stm32SpiReadData(struct SpiHardwareDevice *spi_dev, struct SpiData
NULL_PARAM_CHECK(spi_dev);
NULL_PARAM_CHECK(spi_datacfg);
struct Stm32Spi *StmSpi = CONTAINER_OF(spi_dev->haldev.owner_bus, struct Stm32Spi, SpiBus);
struct Stm32Spi *StmSpi = CONTAINER_OF(spi_dev->haldev.owner_bus, struct Stm32Spi, spi_bus);
SPI_TypeDef *SpiInstance = StmSpi->instance;
SPI_InitTypeDef *SpiInit = &StmSpi->init;
struct Stm32HwSpiCs *cs = (struct Stm32HwSpiCs *)spi_dev->haldev.private_data;
struct Stm32HwSpiCs *cs = (struct Stm32HwSpiCs *)spi_dev->private_data;
while(NONE != spi_datacfg)
{
while(NONE != spi_datacfg) {
if(spi_datacfg->spi_chip_select) {
GPIO_WriteBit(cs->GPIOx, cs->GPIO_Pin, Bit_RESET);
}
message_length = spi_datacfg->length;
ReadBuf = spi_datacfg->rx_buff;
while (message_length)
{
while (message_length) {
if (message_length > 65535){
send_length = 65535;
message_length = message_length - 65535;
}
else{
} else {
send_length = message_length;
message_length = 0;
}
@ -1262,24 +1253,22 @@ static uint32 Stm32SpiReadData(struct SpiHardwareDevice *spi_dev, struct SpiData
ReadBuf = (uint8 *)spi_datacfg->rx_buff + already_send_length;
/* start once data exchange in DMA mode */
if (spi_datacfg->rx_buff)
{
if (spi_datacfg->rx_buff) {
memset((uint8_t *)ReadBuf, 0xff, send_length);
if (StmSpi->spi_dma_flag & SPI_USING_RX_DMA_FLAG) {
state = SpiReceiveDma(*SpiInit, SpiInstance, StmSpi->dma.dma_rx.init, StmSpi->dma.dma_rx.instance, StmSpi->dma.dma_tx.init, StmSpi->dma.dma_tx.instance, (uint8_t *)ReadBuf, send_length);
}
else{
} else {
state = SpiReceive(*SpiInit, SpiInstance, (uint8_t *)ReadBuf, send_length, 1000);
}
}
if (state != 0){
if (state != 0) {
KPrintf("spi transfer error : %d\n", state);
spi_datacfg->length = 0;
}
}
if (spi_datacfg->spi_cs_release){
if (spi_datacfg->spi_cs_release) {
GPIO_WriteBit(cs->GPIOx, cs->GPIO_Pin, Bit_SET);
}
@ -1302,7 +1291,7 @@ static uint32 SpiDrvInit(struct SpiDriver *spi_drv)
SpiDeviceParam *dev_param = (SpiDeviceParam *)(spi_drv->driver.private_data);
struct Stm32Spi *StmSpi = CONTAINER_OF(spi_drv->driver.owner_bus, struct Stm32Spi, SpiBus);
struct Stm32Spi *StmSpi = CONTAINER_OF(spi_drv->driver.owner_bus, struct Stm32Spi, spi_bus);
return Stm32SpiInit(StmSpi, dev_param->spi_master_param);
}
@ -1341,15 +1330,15 @@ static uint32 Stm32SpiDrvConfigure(void *drv, struct BusConfigureInfo *configure
switch (configure_info->configure_cmd)
{
case OPE_INT:
ret = SpiDrvInit(spi_drv);
break;
case OPE_CFG:
spi_param = (struct SpiMasterParam *)configure_info->private_data;
ret = SpiDrvConfigure(spi_drv, spi_param);
break;
default:
break;
case OPE_INT:
ret = SpiDrvInit(spi_drv);
break;
case OPE_CFG:
spi_param = (struct SpiMasterParam *)configure_info->private_data;
ret = SpiDrvConfigure(spi_drv, spi_param);
break;
default:
break;
}
return ret;
@ -1358,10 +1347,10 @@ static uint32 Stm32SpiDrvConfigure(void *drv, struct BusConfigureInfo *configure
/*manage the spi device operations*/
static const struct SpiDevDone spi_dev_done =
{
.open = NONE,
.close = NONE,
.write = Stm32SpiWriteData,
.read = Stm32SpiReadData,
.open = NONE,
.close = NONE,
.write = Stm32SpiWriteData,
.read = Stm32SpiReadData,
};
#if defined(BSP_USING_SPI1)
@ -1369,7 +1358,7 @@ struct Stm32Spi spi1;
#if defined(BSP_SPI1_TX_USING_DMA)
void DMA2_Stream3_IRQHandler(int irq_num, void *arg)
{
DmaTxDoneIsr(&spi1.SpiBus);
DmaTxDoneIsr(&spi1.spi_bus);
}
DECLARE_HW_IRQ(DMA2_Stream3_IRQn, DMA2_Stream3_IRQHandler, NONE);
#endif
@ -1377,7 +1366,7 @@ DECLARE_HW_IRQ(DMA2_Stream3_IRQn, DMA2_Stream3_IRQHandler, NONE);
#if defined(BSP_SPI1_RX_USING_DMA)
void DMA2_Stream0_IRQHandler(int irq_num, void *arg)
{
DmaRxDoneIsr(&spi1.SpiBus);
DmaRxDoneIsr(&spi1.spi_bus);
}
DECLARE_HW_IRQ(DMA2_Stream0_IRQn, DMA2_Stream0_IRQHandler, NONE);
#endif
@ -1388,7 +1377,7 @@ struct Stm32Spi spi2;
#if defined(BSP_SPI2_TX_USING_DMA)
void DMA1_Stream4_IRQHandler(int irq_num, void *arg)
{
DmaTxDoneIsr(&spi2.SpiBus);
DmaTxDoneIsr(&spi2.spi_bus);
}
DECLARE_HW_IRQ(DMA1_Stream4_IRQn, DMA1_Stream4_IRQHandler, NONE);
#endif
@ -1396,7 +1385,7 @@ DECLARE_HW_IRQ(DMA1_Stream4_IRQn, DMA1_Stream4_IRQHandler, NONE);
#if defined(BSP_SPI2_RX_USING_DMA)
void DMA1_Stream3_IRQHandler(int irq_num, void *arg)
{
DmaTxDoneIsr(&spi2.SpiBus);
DmaTxDoneIsr(&spi2.spi_bus);
}
DECLARE_HW_IRQ(DMA1_Stream3_IRQn, DMA1_Stream3_IRQHandler, NONE);
#endif
@ -1407,7 +1396,7 @@ struct Stm32Spi spi3;
#if defined(BSP_SPI3_TX_USING_DMA)
void DMA1_Stream7_IRQHandler(int irq_num, void *arg)
{
DmaTxDoneIsr(&spi3.SpiBus);
DmaTxDoneIsr(&spi3.spi_bus);
}
DECLARE_HW_IRQ(DMA1_Stream7_IRQn, DMA1_Stream7_IRQHandler, NONE);
#endif
@ -1420,11 +1409,12 @@ DECLARE_HW_IRQ(DMA1_Stream7_IRQn, DMA1_Stream7_IRQHandler, NONE);
*/
void DMA1_Stream2_IRQHandler(int irq_num, void *arg)
{
DmaRxDoneIsr(&spi3.SpiBus);
DmaRxDoneIsr(&spi3.spi_bus);
}
DECLARE_HW_IRQ(DMA1_Stream2_IRQn, DMA1_Stream2_IRQHandler, NONE);
#endif
#endif
/**
* This function RCC clock configuration function
*
@ -1457,57 +1447,56 @@ static void RCCConfiguration(void)
*/
static void GPIOConfiguration(void)
{
GPIO_InitTypeDef gpio_initstructure;
GPIO_InitTypeDef gpio_initstructure;
gpio_initstructure.GPIO_Mode = GPIO_Mode_AF; /* Reuse function */
gpio_initstructure.GPIO_OType = GPIO_OType_PP; /* Multiplex push-pull*/
gpio_initstructure.GPIO_PuPd = GPIO_PuPd_UP; /* pull up */
gpio_initstructure.GPIO_Speed = GPIO_Speed_2MHz; /* Level reversal speed */
gpio_initstructure.GPIO_Mode = GPIO_Mode_AF; /* Reuse function */
gpio_initstructure.GPIO_OType = GPIO_OType_PP; /* Multiplex push-pull*/
gpio_initstructure.GPIO_PuPd = GPIO_PuPd_UP; /* pull up */
gpio_initstructure.GPIO_Speed = GPIO_Speed_2MHz; /* Level reversal speed */
#ifdef BSP_USING_SPI1
gpio_initstructure.GPIO_Pin = SPI1_GPIO_NSS | SPI1_GPIO_SCK | SPI1_GPIO_MISO | SPI1_GPIO_MOSI;
/* Connect alternate function */
GPIO_PinAFConfig(SPI1_GPIO, SPI1_NSS_PIN_SOURCE, GPIO_AF_SPI1);
GPIO_PinAFConfig(SPI1_GPIO, SPI1_SCK_PIN_SOURCE, GPIO_AF_SPI1);
GPIO_PinAFConfig(SPI1_GPIO, SPI1_MISO_PIN_SOURCE, GPIO_AF_SPI1);
GPIO_PinAFConfig(SPI1_GPIO, SPI1_MOSI_PIN_SOURCE, GPIO_AF_SPI1);
GPIO_Init(SPI1_GPIO, &gpio_initstructure); /*SPI pin initialization*/
gpio_initstructure.GPIO_Pin = SPI1_GPIO_NSS | SPI1_GPIO_SCK | SPI1_GPIO_MISO | SPI1_GPIO_MOSI;
/* Connect alternate function */
GPIO_PinAFConfig(SPI1_GPIO, SPI1_NSS_PIN_SOURCE, GPIO_AF_SPI1);
GPIO_PinAFConfig(SPI1_GPIO, SPI1_SCK_PIN_SOURCE, GPIO_AF_SPI1);
GPIO_PinAFConfig(SPI1_GPIO, SPI1_MISO_PIN_SOURCE, GPIO_AF_SPI1);
GPIO_PinAFConfig(SPI1_GPIO, SPI1_MOSI_PIN_SOURCE, GPIO_AF_SPI1);
GPIO_Init(SPI1_GPIO, &gpio_initstructure); /*SPI pin initialization*/
#endif
#ifdef BSP_USING_SPI2
gpio_initstructure.GPIO_Pin = SPI2_GPIO_SCK;
/* Connect alternate function */
GPIO_PinAFConfig(SPI2_SCK, SPI2_SCK_PIN_SOURCE, GPIO_AF_SPI2);
gpio_initstructure.GPIO_Pin = SPI2_GPIO_SCK;
/* Connect alternate function */
GPIO_PinAFConfig(SPI2_SCK, SPI2_SCK_PIN_SOURCE, GPIO_AF_SPI2);
GPIO_Init(SPI2_SCK, &gpio_initstructure);
GPIO_Init(SPI2_SCK, &gpio_initstructure);
gpio_initstructure.GPIO_Pin = SPI2_GPIO_NSS | SPI2_GPIO_MISO | SPI2_GPIO_MOSI;
/* Connect alternate function */
GPIO_PinAFConfig(SPI2_GPIO, SPI2_NSS_PIN_SOURCE, GPIO_AF_SPI2);
GPIO_PinAFConfig(SPI2_GPIO, SPI2_MISO_PIN_SOURCE, GPIO_AF_SPI2);
GPIO_PinAFConfig(SPI2_GPIO, SPI2_MOSI_PIN_SOURCE, GPIO_AF_SPI2);
GPIO_Init(SPI2_GPIO, &gpio_initstructure);
gpio_initstructure.GPIO_Pin = SPI2_GPIO_NSS | SPI2_GPIO_MISO | SPI2_GPIO_MOSI;
/* Connect alternate function */
GPIO_PinAFConfig(SPI2_GPIO, SPI2_NSS_PIN_SOURCE, GPIO_AF_SPI2);
GPIO_PinAFConfig(SPI2_GPIO, SPI2_MISO_PIN_SOURCE, GPIO_AF_SPI2);
GPIO_PinAFConfig(SPI2_GPIO, SPI2_MOSI_PIN_SOURCE, GPIO_AF_SPI2);
GPIO_Init(SPI2_GPIO, &gpio_initstructure);
#endif
#ifdef BSP_USING_SPI3
gpio_initstructure.GPIO_Pin = SPI3_GPIO_NSS;
/* Connect alternate function */
GPIO_PinAFConfig(SPI3_NSS, SPI3_NSS_PIN_SOURCE, GPIO_AF_SPI3);
gpio_initstructure.GPIO_Pin = SPI3_GPIO_NSS;
/* Connect alternate function */
GPIO_PinAFConfig(SPI3_NSS, SPI3_NSS_PIN_SOURCE, GPIO_AF_SPI3);
GPIO_Init(SPI3_NSS, &gpio_initstructure);
GPIO_Init(SPI3_NSS, &gpio_initstructure);
gpio_initstructure.GPIO_Pin = SPI3_GPIO_SCK | SPI3_GPIO_MISO | SPI3_GPIO_MOSI;
GPIO_PinAFConfig(SPI3_GPIO, SPI3_SCK_PIN_SOURCE, GPIO_AF_SPI3);
GPIO_PinAFConfig(SPI3_GPIO, SPI3_MISO_PIN_SOURCE, GPIO_AF_SPI3);
GPIO_PinAFConfig(SPI3_GPIO, SPI3_MOSI_PIN_SOURCE, GPIO_AF_SPI3);
GPIO_Init(SPI3_GPIO, &gpio_initstructure);
gpio_initstructure.GPIO_Pin = SPI3_GPIO_SCK | SPI3_GPIO_MISO | SPI3_GPIO_MOSI;
GPIO_PinAFConfig(SPI3_GPIO, SPI3_SCK_PIN_SOURCE, GPIO_AF_SPI3);
GPIO_PinAFConfig(SPI3_GPIO, SPI3_MISO_PIN_SOURCE, GPIO_AF_SPI3);
GPIO_PinAFConfig(SPI3_GPIO, SPI3_MOSI_PIN_SOURCE, GPIO_AF_SPI3);
GPIO_Init(SPI3_GPIO, &gpio_initstructure);
#endif
}
/**
* This function Init the spi bus 、spi driver and attach to the bus
*
@ -1522,22 +1511,22 @@ static int BoardSpiBusInit(struct Stm32Spi *stm32spi_bus, struct SpiDriver *spi_
x_err_t ret = EOK;
/*Init the spi bus */
ret = SpiBusInit(&stm32spi_bus->SpiBus, stm32spi_bus->BusName);
if(EOK != ret){
ret = SpiBusInit(&stm32spi_bus->spi_bus, stm32spi_bus->bus_name);
if (EOK != ret) {
KPrintf("Board_Spi_init SpiBusInit error %d\n", ret);
return ERROR;
}
/*Init the spi driver*/
ret = SpiDriverInit(spi_driver, drv_name);
if(EOK != ret){
if (EOK != ret) {
KPrintf("Board_Spi_init SpiDriverInit error %d\n", ret);
return ERROR;
}
/*Attach the spi driver to the spi bus*/
ret = SpiDriverAttachToBus(drv_name, stm32spi_bus->BusName);
if(EOK != ret){
ret = SpiDriverAttachToBus(drv_name, stm32spi_bus->bus_name);
if (EOK != ret) {
KPrintf("Board_Spi_init SpiDriverAttachToBus error %d\n", ret);
return ERROR;
}
@ -1561,9 +1550,9 @@ static int Stm32HwSpiBusInit(void)
#ifdef BSP_USING_SPI1
StmSpiBus = &spi1;
StmSpiBus->instance = SPI1;
StmSpiBus->BusName = SPI_BUS_NAME_1;
StmSpiBus->SpiBus.private_data = &spi1;
DmaSpiConfig(&StmSpiBus->SpiBus, 0, NONE, NONE);
StmSpiBus->bus_name = SPI_BUS_NAME_1;
StmSpiBus->spi_bus.private_data = &spi1;
DmaSpiConfig(&StmSpiBus->spi_bus, 0, NONE, NONE);
static struct SpiDriver spi_driver_1;
memset(&spi_driver_1, 0, sizeof(struct SpiDriver));
@ -1571,9 +1560,8 @@ static int Stm32HwSpiBusInit(void)
spi_driver_1.configure = &(Stm32SpiDrvConfigure);
ret = BoardSpiBusInit(StmSpiBus, &spi_driver_1, SPI_1_DRV_NAME);
if(EOK != ret)
{
KPrintf("Board_Spi_Init spi_bus_init %s error ret %u\n", StmSpiBus->BusName, ret);
if (EOK != ret) {
KPrintf("Board_Spi_Init spi_bus_init %s error ret %u\n", StmSpiBus->bus_name, ret);
return ERROR;
}
#endif
@ -1581,9 +1569,9 @@ static int Stm32HwSpiBusInit(void)
#ifdef BSP_USING_SPI2
StmSpiBus = &spi2;
StmSpiBus->instance = SPI2;
StmSpiBus->BusName = SPI_BUS_NAME_2;
StmSpiBus->SpiBus.private_data = &spi2;
DmaSpiConfig(&StmSpiBus->SpiBus, 0, NONE, NONE);
StmSpiBus->bus_name = SPI_BUS_NAME_2;
StmSpiBus->spi_bus.private_data = &spi2;
DmaSpiConfig(&StmSpiBus->spi_bus, 0, NONE, NONE);
static struct SpiDriver spi_driver_2;
memset(&spi_driver_2, 0, sizeof(struct SpiDriver));
@ -1591,8 +1579,7 @@ static int Stm32HwSpiBusInit(void)
spi_driver_2.configure = &(Stm32SpiDrvConfigure);
ret = BoardSpiBusInit(StmSpiBus, &spi_driver_2, SPI_2_DRV_NAME);
if(EOK != ret)
{
if (EOK != ret) {
return ERROR;
}
#endif
@ -1600,9 +1587,9 @@ static int Stm32HwSpiBusInit(void)
#ifdef BSP_USING_SPI3
StmSpiBus = &spi3;
StmSpiBus->instance = SPI3;
StmSpiBus->BusName = SPI_BUS_NAME_3;
StmSpiBus->SpiBus.private_data = &spi3;
DmaSpiConfig(&StmSpiBus->SpiBus, 0, NONE, NONE);
StmSpiBus->bus_name = SPI_BUS_NAME_3;
StmSpiBus->spi_bus.private_data = &spi3;
DmaSpiConfig(&StmSpiBus->spi_bus, 0, NONE, NONE);
static struct SpiDriver spi_driver_3;
memset(&spi_driver_3, 0, sizeof(struct SpiDriver));
@ -1610,9 +1597,8 @@ static int Stm32HwSpiBusInit(void)
spi_driver_3.configure = &(Stm32SpiDrvConfigure);
ret = BoardSpiBusInit(StmSpiBus, &spi_driver_3, SPI_3_DRV_NAME);
if(EOK != ret)
{
KPrintf("Board_Spi_Init spi_bus_init %s error ret %u\n", StmSpiBus->BusName, ret);
if (EOK != ret) {
KPrintf("Board_Spi_Init spi_bus_init %s error ret %u\n", StmSpiBus->bus_name, ret);
return ERROR;
}
#endif
@ -1622,7 +1608,7 @@ static int Stm32HwSpiBusInit(void)
/**
* This function Mount the spi device to the bus
*
* @param BusName Bus Name
* @param bus_name Bus Name
*
* @param device_name spi device name
*
@ -1632,14 +1618,16 @@ static int Stm32HwSpiBusInit(void)
*
* @return EOK
*/
x_err_t HwSpiDeviceAttach(const char *BusName, const char *device_name, GPIO_TypeDef *cs_gpiox, uint16_t cs_gpio_pin)
x_err_t HwSpiDeviceAttach(const char *bus_name, const char *device_name, GPIO_TypeDef *cs_gpiox, uint16_t cs_gpio_pin)
{
NULL_PARAM_CHECK(BusName);
NULL_PARAM_CHECK(bus_name);
NULL_PARAM_CHECK(device_name);
x_err_t result;
struct SpiHardwareDevice *SpiDevice;
struct Stm32HwSpiCs *CsPin;
struct SpiHardwareDevice *spi_device;
struct Stm32HwSpiCs *cs_pin_param;
static SpiDeviceParam spi_dev_param;
memset(&spi_dev_param, 0, sizeof(SpiDeviceParam));
/* initialize the cs pin && select the slave*/
GPIO_InitTypeDef GPIO_Initure;
@ -1651,34 +1639,35 @@ x_err_t HwSpiDeviceAttach(const char *BusName, const char *device_name, GPIO_Typ
GPIO_WriteBit(cs_gpiox, cs_gpio_pin, Bit_SET);
/* attach the device to spi bus*/
SpiDevice = (struct SpiHardwareDevice *)x_malloc(sizeof(struct SpiHardwareDevice));
CHECK(SpiDevice);
memset(SpiDevice, 0, sizeof(struct SpiHardwareDevice));
CsPin = (struct Stm32HwSpiCs *)x_malloc(sizeof(struct Stm32HwSpiCs));
CHECK(CsPin);
memset(CsPin, 0, sizeof(struct Stm32HwSpiCs));
CsPin->GPIOx = cs_gpiox;
CsPin->GPIO_Pin = cs_gpio_pin;
spi_device = (struct SpiHardwareDevice *)x_malloc(sizeof(struct SpiHardwareDevice));
CHECK(spi_device);
memset(spi_device, 0, sizeof(struct SpiHardwareDevice));
cs_pin_param = (struct Stm32HwSpiCs *)x_malloc(sizeof(struct Stm32HwSpiCs));
CHECK(cs_pin_param);
memset(cs_pin_param, 0, sizeof(struct Stm32HwSpiCs));
cs_pin_param->GPIOx = cs_gpiox;
cs_pin_param->GPIO_Pin = cs_gpio_pin;
SpiDevice->spi_dev_done = &spi_dev_done;
spi_device->spi_dev_done = &spi_dev_done;
spi_device->private_data = (void *)cs_pin_param;
result = SpiDeviceRegister(SpiDevice, (void *)CsPin, device_name);
if (result != EOK)
{
SYS_ERR("%s device %p register faild, %d\n", device_name, SpiDevice, result);
result = SpiDeviceRegister(spi_device, (void *)&spi_dev_param, device_name);
if (result != EOK) {
SYS_ERR("%s device %p register faild, %d\n", device_name, spi_device, result);
}
result = SpiDeviceAttachToBus(device_name, BusName);
if (result != EOK){
SYS_ERR("%s attach to %s faild, %d\n", device_name, BusName, result);
result = SpiDeviceAttachToBus(device_name, bus_name);
if (result != EOK) {
SYS_ERR("%s attach to %s faild, %d\n", device_name, bus_name, result);
}
CHECK(result == EOK);
KPrintf("%s attach to %s done\n", device_name, BusName);
KPrintf("%s attach to %s done\n", device_name, bus_name);
return result;
}
/**
* This function Get DMA information
*
@ -1731,6 +1720,7 @@ static void Stm32GetDmaInfo(void)
spi3.dma.dma_tx.dma_irq = DMA1_Stream7_IRQn; /*Enable DMA interrupt line*/
#endif
}
/**
* This function hardware spi initialization
*

27
board/aiit-arm32-board/third_party_driver/timer/connect_hwtimer.c
View File

@ -40,17 +40,15 @@ Modification:
static struct HwtimerCallBackInfo *ptim2_cb_info = NULL;
#ifdef ENABLE_TIM2
void TIM2_IRQHandler(int irq_num, void *arg)
{
TIM_ClearITPendingBit(TIM2, TIM_IT_Update);
KPrintf("hwtimer 2 ... come ...\n");
if (ptim2_cb_info)
{
if (ptim2_cb_info->TimeoutCb){
ptim2_cb_info->TimeoutCb(ptim2_cb_info->param);
if (ptim2_cb_info) {
if (ptim2_cb_info->timeout_callback){
ptim2_cb_info->timeout_callback(ptim2_cb_info->param);
}
}
}
@ -97,10 +95,10 @@ uint32 HwtimerClose(void *dev)
/*manage the hwtimer device operations*/
static const struct HwtimerDevDone dev_done =
{
.open = HwtimerOpen,
.close = HwtimerClose,
.write = NONE,
.read = NONE,
.open = HwtimerOpen,
.close = HwtimerClose,
.write = NONE,
.read = NONE,
};
/*Init hwtimer bus*/
@ -110,7 +108,7 @@ static int BoardHwtimerBusInit(struct HwtimerBus *hwtimer_bus, struct HwtimerDri
/*Init the hwtimer bus */
ret = HwtimerBusInit(hwtimer_bus, HWTIMER_BUS_NAME_2);
if (EOK != ret){
if (EOK != ret) {
KPrintf("board_hwtimer_init HwtimerBusInit error %d\n", ret);
return ERROR;
}
@ -119,7 +117,7 @@ static int BoardHwtimerBusInit(struct HwtimerBus *hwtimer_bus, struct HwtimerDri
/*Init the hwtimer driver*/
hwtimer_driver->configure = NONE;
ret = HwtimerDriverInit(hwtimer_driver, HWTIMER_DRIVER_NAME_2);
if (EOK != ret){
if (EOK != ret) {
KPrintf("board_hwtimer_init HwtimerDriverInit error %d\n", ret);
return ERROR;
}
@ -146,7 +144,7 @@ static int BoardHwtimerDevBend(void)
hwtimer_device_2.dev_done = &dev_done;
ret = HwtimerDeviceRegister(&hwtimer_device_2, NONE, HWTIMER_2_DEVICE_NAME_2);
if (EOK != ret){
if (EOK != ret) {
KPrintf("board_hwtimer_init HWTIMERDeviceInit device %s error %d\n", HWTIMER_2_DEVICE_NAME_2, ret);
return ERROR;
}
@ -171,15 +169,14 @@ int Stm32HwTimerInit(void)
static struct HwtimerDriver hwtimer_driver;
memset(&hwtimer_driver, 0, sizeof(struct HwtimerDriver));
ret = BoardHwtimerBusInit(&hwtimer_bus, &hwtimer_driver);
if (EOK != ret){
if (EOK != ret) {
KPrintf("board_hwtimer_Init error ret %u\n", ret);
return ERROR;
}
ret = BoardHwtimerDevBend();
if (EOK != ret){
if (EOK != ret) {
KPrintf("board_hwtimer_Init error ret %u\n", ret);
return ERROR;
}

210
board/aiit-arm32-board/third_party_driver/touch/connect_touch.c
View File

@ -32,27 +32,25 @@ Modification:
#include <hardware_rcc.h>
#include <misc.h>
touch_device_info tp_dev=
touch_device_info tp_dev =
{
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
};
unsigned char CMD_RDX=0XD0;
unsigned char CMD_RDY=0X90;
TP_modify_save modify_save={
0,0,0,0,0,0
};
TP_modify_save modify_save =
{
0,0,0,0,0,0
};
static int Stm32Udelay(uint32 us)
{
@ -62,8 +60,7 @@ unsigned char CMD_RDY=0X90;
ticks = us * reload / (1000000 / TICK_PER_SECOND);
told = SysTick->VAL;
while (1)
{
while (1) {
tnow = SysTick->VAL;
if (tnow != told) {
if (tnow < told) {
@ -83,61 +80,65 @@ unsigned char CMD_RDY=0X90;
void TouchWriteByte(unsigned char num)
{
u8 count=0;
for(count=0;count<8;count++)
{
if(num&0x80)T_MOSI=1;
else T_MOSI=0;
num<<=1;
T_CLK =0;
for(count = 0;count < 8;count ++) {
if (num & 0x80)
T_MOSI=1;
else
T_MOSI=0;
num <<= 1;
T_CLK = 0;
Stm32Udelay(1);
T_CLK =1;
T_CLK = 1;
}
}
u16 TP_Read_AD(u8 cmd)
u16 TpReadAd(u8 cmd)
{
u8 count=0;
u16 Num=0;
T_CLK =0;
T_MOSI=0;
TCS=0;
u8 count = 0;
u16 Num = 0;
T_CLK =0;
T_MOSI = 0;
TCS = 0;
TouchWriteByte(cmd);
Stm32Udelay(6);
T_CLK =0;
T_CLK = 0;
Stm32Udelay(1);
T_CLK =1;
T_CLK = 1;
Stm32Udelay(1);
T_CLK =0;
for(count=0;count<16;count++)
{
Num<<=1;
T_CLK =0;
T_CLK = 0;
for(count = 0;count < 16;count ++) {
Num <<= 1;
T_CLK = 0;
Stm32Udelay(1);
T_CLK =1;
if(T_MISO == 1)Num++;
T_CLK =1;
if (T_MISO == 1)
Num++;
}
Num>>=4;
TCS=1;
Num >>= 4;
TCS = 1;
return(Num);
}
#define READ_TIMES 5
#define LOST_VAL 1
u16 TP_Read_XOY(u8 xy)
u16 TpReadXoy(u8 xy)
{
u16 i, j;
u16 buf[READ_TIMES];
u16 sum=0;
u16 temp;
for(i=0;i<READ_TIMES;i++)buf[i]=TP_Read_AD(xy);
for(i=0;i<READ_TIMES-1; i++)
{
for(j=i+1;j<READ_TIMES;j++)
{
if(buf[i]>buf[j])
{
for(i = 0;i < READ_TIMES;i ++)
buf[i]=TpReadAd(xy);
for(i = 0;i < READ_TIMES-1; i ++) {
for(j = i+1;j < READ_TIMES;j ++) {
if (buf[i] > buf[j]) {
temp=buf[i];
buf[i]=buf[j];
buf[j]=temp;
@ -145,16 +146,17 @@ u16 TP_Read_XOY(u8 xy)
}
}
sum=0;
for(i=LOST_VAL;i<READ_TIMES-LOST_VAL;i++)sum+=buf[i];
for(i = LOST_VAL;i < READ_TIMES - LOST_VAL;i ++)
sum+=buf[i];
temp=sum/(READ_TIMES-2*LOST_VAL);
return temp;
}
u8 TP_Read_XY(u16 *x,u16 *y)
u8 TpReadXy(u16 *x, u16 *y)
{
u16 xtemp,ytemp;
xtemp=TP_Read_XOY(CMD_RDX);
ytemp=TP_Read_XOY(CMD_RDY);
xtemp=TpReadXoy(CMD_RDX);
ytemp=TpReadXoy(CMD_RDY);
*x=xtemp;
*y=ytemp;
@ -163,64 +165,57 @@ u8 TP_Read_XY(u16 *x,u16 *y)
static uint32 TouchRead(void *dev, struct BusBlockReadParam *read_param)
{
uint32 ret = EOK;
NULL_PARAM_CHECK(read_param);
struct TouchDataStandard * data = ( struct TouchDataStandard*)read_param->buffer;
TP_Read_XY(&data->x,&data->y);
return ret;
uint32 ret = EOK;
NULL_PARAM_CHECK(read_param);
struct TouchDataStandard * data = ( struct TouchDataStandard*)read_param->buffer;
TpReadXy(&data->x,&data->y);
return ret;
}
static uint32 TouchConfigure(void *drv, struct BusConfigureInfo *configure_info)
static uint32 TouchConfigure(void *drv, struct BusConfigureInfo *configure_info)
{
GPIO_InitTypeDef gpio_initstructure;
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB|RCC_AHB1Periph_GPIOG|RCC_AHB1Periph_GPIOD, ENABLE);
GPIO_InitTypeDef gpio_initstructure;
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB|RCC_AHB1Periph_GPIOG|RCC_AHB1Periph_GPIOD, ENABLE);
gpio_initstructure.GPIO_Pin =GPIO_Pin_4;
gpio_initstructure.GPIO_Mode = GPIO_Mode_IN;
gpio_initstructure.GPIO_OType = GPIO_OType_PP;
gpio_initstructure.GPIO_Speed = GPIO_Speed_100MHz;
gpio_initstructure.GPIO_PuPd = GPIO_PuPd_UP;
GPIO_Init(GPIOB, &gpio_initstructure);
gpio_initstructure.GPIO_Pin = GPIO_Pin_3;
gpio_initstructure.GPIO_Mode = GPIO_Mode_OUT;
GPIO_Init(GPIOB, &gpio_initstructure);
gpio_initstructure.GPIO_Pin = GPIO_Pin_13;
gpio_initstructure.GPIO_Mode = GPIO_Mode_OUT;
GPIO_Init(GPIOG, &gpio_initstructure);
gpio_initstructure.GPIO_Pin = GPIO_Pin_5;
gpio_initstructure.GPIO_Mode = GPIO_Mode_OUT;
GPIO_Init(GPIOB, &gpio_initstructure);
gpio_initstructure.GPIO_Pin = GPIO_Pin_6;
gpio_initstructure.GPIO_Mode = GPIO_Mode_OUT;
GPIO_Init(GPIOD, &gpio_initstructure);
gpio_initstructure.GPIO_Pin = GPIO_Pin_3;
gpio_initstructure.GPIO_Mode = GPIO_Mode_OUT;
GPIO_Init(GPIOB, &gpio_initstructure);
gpio_initstructure.GPIO_Pin = GPIO_Pin_13;
gpio_initstructure.GPIO_Mode = GPIO_Mode_OUT;
GPIO_Init(GPIOG, &gpio_initstructure);
return 0;
gpio_initstructure.GPIO_Pin = GPIO_Pin_5;
gpio_initstructure.GPIO_Mode = GPIO_Mode_OUT;
GPIO_Init(GPIOB, &gpio_initstructure);
gpio_initstructure.GPIO_Pin = GPIO_Pin_6;
gpio_initstructure.GPIO_Mode = GPIO_Mode_OUT;
GPIO_Init(GPIOD, &gpio_initstructure);
return 0;
}
struct TouchDevDone touch_dev_done ={
.open = NONE,
.close = NONE,
.write = NONE,
.read = TouchRead
struct TouchDevDone touch_dev_done =
{
.open = NONE,
.close = NONE,
.write = NONE,
.read = TouchRead
};
struct Stm32Touch
{
char *BusName;
struct TouchBus touchbus;
char *bus_name;
struct TouchBus touch_bus;
};
struct Stm32Touch touch;
@ -230,22 +225,22 @@ static int BoardTouchBusInit(struct Stm32Touch *stm32touch_bus, struct TouchDriv
x_err_t ret = EOK;
/*Init the touch bus */
ret = TouchBusInit(&stm32touch_bus->touchbus, stm32touch_bus->BusName);
if(EOK != ret) {
ret = TouchBusInit(&stm32touch_bus->touch_bus, stm32touch_bus->bus_name);
if (EOK != ret) {
KPrintf("Board_touch_init touchBusInit error %d\n", ret);
return ERROR;
}
/*Init the touch driver*/
ret = TouchDriverInit(touch_driver, TOUCH_DRV_NAME_1);
if(EOK != ret){
if (EOK != ret){
KPrintf("Board_touch_init touchDriverInit error %d\n", ret);
return ERROR;
}
/*Attach the touch driver to the touch bus*/
ret = TouchDriverAttachToBus(TOUCH_DRV_NAME_1, stm32touch_bus->BusName);
if(EOK != ret){
ret = TouchDriverAttachToBus(TOUCH_DRV_NAME_1, stm32touch_bus->bus_name);
if (EOK != ret){
KPrintf("Board_touch_init TouchDriverAttachToBus error %d\n", ret);
return ERROR;
}
@ -253,8 +248,6 @@ static int BoardTouchBusInit(struct Stm32Touch *stm32touch_bus, struct TouchDriv
return ret;
}
/*Attach the touch device to the touch bus*/
static int BoardTouchDevBend(void)
{
@ -265,13 +258,13 @@ static int BoardTouchDevBend(void)
touch_device.dev_done = &touch_dev_done;
ret = TouchDeviceRegister(&touch_device, NONE, TOUCH_1_DEVICE_NAME_0);
if(EOK != ret){
if (EOK != ret){
KPrintf("TouchDeviceRegister device %s error %d\n", TOUCH_1_DEVICE_NAME_0, ret);
return ERROR;
}
ret = TouchDeviceAttachToBus(TOUCH_1_DEVICE_NAME_0, TOUCH_BUS_NAME_1);
if(EOK != ret) {
if (EOK != ret) {
KPrintf("TouchDeviceAttachToBus device %s error %d\n", TOUCH_1_DEVICE_NAME_0, ret);
return ERROR;
}
@ -290,15 +283,16 @@ int Stm32HwTouchBusInit(void)
touch_driver.configure = TouchConfigure;
Stmtouch = &touch;
Stmtouch->BusName = TOUCH_BUS_NAME_1;
Stmtouch->touchbus.private_data = &touch;
Stmtouch->bus_name = TOUCH_BUS_NAME_1;
Stmtouch->touch_bus.private_data = &touch;
ret = BoardTouchBusInit(Stmtouch, &touch_driver);
if(EOK != ret) {
if (EOK != ret) {
return ERROR;
}
ret = BoardTouchDevBend();
if(EOK != ret){
ret = BoardTouchDevBend();
if (EOK != ret) {
KPrintf("board_touch_Init error ret %u\n", ret);
return ERROR;
}

86
board/aiit-arm32-board/third_party_driver/uart/connect_usart.c
View File

@ -198,7 +198,7 @@ static void DmaUartConfig(struct Stm32UsartDma *dma, USART_TypeDef *uart_device,
static void DMAConfiguration(struct SerialHardwareDevice *serial_dev, USART_TypeDef *uart_device)
{
struct Stm32Usart *serial = CONTAINER_OF(serial_dev->haldev.owner_bus, struct Stm32Usart, SerialBus);
struct Stm32Usart *serial = CONTAINER_OF(serial_dev->haldev.owner_bus, struct Stm32Usart, serial_bus);
struct Stm32UsartDma *dma = &serial->dma;
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
@ -264,7 +264,7 @@ static uint32 Stm32SerialInit(struct SerialDriver *serial_drv, struct BusConfigu
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
if(configure_info->private_data){
if (configure_info->private_data) {
struct SerialCfgParam *serial_cfg_new = (struct SerialCfgParam *)configure_info->private_data;
SerialCfgParamCheck(serial_cfg, serial_cfg_new);
}
@ -275,25 +275,21 @@ static uint32 Stm32SerialInit(struct SerialDriver *serial_drv, struct BusConfigu
if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_8) {
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
}
else if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_9){
} else if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_9) {
USART_InitStructure.USART_WordLength = USART_WordLength_9b;
}
if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_1) {
USART_InitStructure.USART_StopBits = USART_StopBits_1;
}
else if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_2) {
} else if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_2) {
USART_InitStructure.USART_StopBits = USART_StopBits_2;
}
if (serial_cfg->data_cfg.serial_parity_mode == PARITY_NONE){
if (serial_cfg->data_cfg.serial_parity_mode == PARITY_NONE) {
USART_InitStructure.USART_Parity = USART_Parity_No;
}
else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_ODD){
} else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_ODD) {
USART_InitStructure.USART_Parity = USART_Parity_Odd;
}
else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_EVEN){
} else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_EVEN) {
USART_InitStructure.USART_Parity = USART_Parity_Even;
}
@ -379,7 +375,7 @@ static void DmaRxDoneIsr(struct Stm32Usart *serial, struct SerialDriver *serial_
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
if (DMA_GetFlagStatus(dma->RxStream, dma->RxFlag) != RESET){
if (DMA_GetFlagStatus(dma->RxStream, dma->RxFlag) != RESET) {
x_base level = CriticalAreaLock();
x_size_t recv_len = dma->SettingRecvLen - dma->LastRecvIndex;
@ -398,17 +394,17 @@ static void UartIsr(struct Stm32Usart *serial, struct SerialDriver *serial_drv,
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
if(USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_RXNE) != RESET){
if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_RXNE) != RESET) {
SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND);
USART_ClearITPendingBit(serial_hw_cfg->uart_device, USART_IT_RXNE);
}
if(USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_IDLE) != RESET){
if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_IDLE) != RESET) {
DmaUartRxIdleIsr(serial_dev, dma, serial_hw_cfg->uart_device);
}
if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_TC) != RESET){
if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_TC) != RESET) {
USART_ClearITPendingBit(serial_hw_cfg->uart_device, USART_IT_TC);
}
if (USART_GetFlagStatus(serial_hw_cfg->uart_device, USART_FLAG_ORE) == SET){
if (USART_GetFlagStatus(serial_hw_cfg->uart_device, USART_FLAG_ORE) == SET) {
USART_ReceiveData(serial_hw_cfg->uart_device);
}
}
@ -559,15 +555,15 @@ static uint32 Stm32SerialDrvConfigure(void *drv, struct BusConfigureInfo *config
switch (configure_info->configure_cmd)
{
case OPE_INT:
ret = Stm32SerialInit(serial_drv, configure_info);
break;
case OPE_CFG:
serial_operation_cmd = *(int *)configure_info->private_data;
ret = Stm32SerialConfigure(serial_drv, serial_operation_cmd);
break;
default:
break;
case OPE_INT:
ret = Stm32SerialInit(serial_drv, configure_info);
break;
case OPE_CFG:
serial_operation_cmd = *(int *)configure_info->private_data;
ret = Stm32SerialConfigure(serial_drv, serial_operation_cmd);
break;
default:
break;
}
return ret;
@ -604,21 +600,21 @@ static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver
/*Init the serial bus */
ret = SerialBusInit(serial_bus, bus_name);
if(EOK != ret){
if (EOK != ret) {
KPrintf("hw_serial_init SerialBusInit error %d\n", ret);
return ERROR;
}
/*Init the serial driver*/
ret = SerialDriverInit(serial_driver, drv_name);
if(EOK != ret){
if (EOK != ret) {
KPrintf("hw_serial_init SerialDriverInit error %d\n", ret);
return ERROR;
}
/*Attach the serial driver to the serial bus*/
ret = SerialDriverAttachToBus(drv_name, bus_name);
if(EOK != ret){
if (EOK != ret) {
KPrintf("hw_serial_init SerialDriverAttachToBus error %d\n", ret);
return ERROR;
}
@ -632,13 +628,13 @@ static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *
x_err_t ret = EOK;
ret = SerialDeviceRegister(serial_device, serial_param, dev_name);
if(EOK != ret){
if (EOK != ret) {
KPrintf("hw_serial_init SerialDeviceInit device %s error %d\n", dev_name, ret);
return ERROR;
}
ret = SerialDeviceAttachToBus(dev_name, bus_name);
if(EOK != ret){
if (EOK != ret) {
KPrintf("hw_serial_init SerialDeviceAttachToBus device %s error %d\n", dev_name, ret);
return ERROR;
}
@ -681,14 +677,14 @@ int Stm32HwUsartInit(void)
NVIC_Configuration(serial_hw_cfg_1.irq);
ret = BoardSerialBusInit(&serial_1.SerialBus, &serial_driver_1, SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1);
if(EOK != ret){
ret = BoardSerialBusInit(&serial_1.serial_bus, &serial_driver_1, SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1);
if (EOK != ret) {
KPrintf("Stm32HwUsartInit usart1 error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device_1, (void *)&serial_cfg_1, SERIAL_BUS_NAME_1, SERIAL_1_DEVICE_NAME_0);
if(EOK != ret){
if (EOK != ret) {
KPrintf("Stm32HwUsartInit usart1 error ret %u\n", ret);
return ERROR;
}
@ -723,14 +719,14 @@ int Stm32HwUsartInit(void)
NVIC_Configuration(serial_hw_cfg_2.irq);
ret = BoardSerialBusInit(&serial_2.SerialBus, &serial_driver_2, SERIAL_BUS_NAME_2, SERIAL_DRV_NAME_2);
if(EOK != ret){
ret = BoardSerialBusInit(&serial_2.serial_bus, &serial_driver_2, SERIAL_BUS_NAME_2, SERIAL_DRV_NAME_2);
if (EOK != ret) {
KPrintf("Stm32HwUsartInit usart2 error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device_2, (void *)&serial_cfg_2, SERIAL_BUS_NAME_2, SERIAL_2_DEVICE_NAME_0);
if(EOK != ret){
if (EOK != ret) {
KPrintf("Stm32HwUsartInit usart2 error ret %u\n", ret);
return ERROR;
}
@ -765,14 +761,14 @@ int Stm32HwUsartInit(void)
NVIC_Configuration(serial_hw_cfg_3.irq);
ret = BoardSerialBusInit(&serial_3.SerialBus, &serial_driver_3, SERIAL_BUS_NAME_3, SERIAL_DRV_NAME_3);
if(EOK != ret) {
ret = BoardSerialBusInit(&serial_3.serial_bus, &serial_driver_3, SERIAL_BUS_NAME_3, SERIAL_DRV_NAME_3);
if (EOK != ret) {
KPrintf("Stm32HwUsartInit usart3 error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device_3, (void *)&serial_cfg_3, SERIAL_BUS_NAME_3, SERIAL_3_DEVICE_NAME_0);
if(EOK != ret){
if (EOK != ret) {
KPrintf("Stm32HwUsartInit usart3 error ret %u\n", ret);
return ERROR;
}
@ -806,14 +802,14 @@ int Stm32HwUsartInit(void)
NVIC_Configuration(serial_hw_cfg_4.irq);
ret = BoardSerialBusInit(&serial_4.SerialBus, &serial_driver_4, SERIAL_BUS_NAME_4, SERIAL_DRV_NAME_4);
if(EOK != ret){
ret = BoardSerialBusInit(&serial_4.serial_bus, &serial_driver_4, SERIAL_BUS_NAME_4, SERIAL_DRV_NAME_4);
if (EOK != ret) {
KPrintf("Stm32HwUsartInit usart4 error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device_4, (void *)&serial_cfg_4, SERIAL_BUS_NAME_4, SERIAL_4_DEVICE_NAME_0);
if(EOK != ret) {
if (EOK != ret) {
KPrintf("Stm32HwUsartInit usart4 error ret %u\n", ret);
return ERROR;
}
@ -847,14 +843,14 @@ int Stm32HwUsartInit(void)
NVIC_Configuration(serial_hw_cfg_5.irq);
ret = BoardSerialBusInit(&serial_5.SerialBus, &serial_driver_5, SERIAL_BUS_NAME_5, SERIAL_DRV_NAME_5);
if(EOK != ret) {
ret = BoardSerialBusInit(&serial_5.serial_bus, &serial_driver_5, SERIAL_BUS_NAME_5, SERIAL_DRV_NAME_5);
if (EOK != ret) {
KPrintf("Stm32HwUsartInit usart5 error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device_5, (void *)&serial_cfg_5, SERIAL_BUS_NAME_5, SERIAL_5_DEVICE_NAME_0);
if(EOK != ret){
if (EOK != ret) {
KPrintf("Stm32HwUsartInit usart5 error ret %u\n", ret);
return ERROR;
}

13
board/aiit-arm32-board/third_party_driver/usb/connect_usb.c
View File

@ -37,11 +37,11 @@ static uint32 UdiskCloseNewApi(void *dev)
/*manage the usb device operations*/
static const struct UsbDevDone dev_done =
{
.open = UdiskOpenNewApi,
.close = UdiskCloseNewApi,
.write = UdiskWirte_new_api,
.read = UdiskRead_new_api,
{
.open = UdiskOpenNewApi,
.close = UdiskCloseNewApi,
.write = UdiskWirte_new_api,
.read = UdiskRead_new_api,
};
/*Init usb bus*/
@ -107,7 +107,6 @@ int Stm32HwUsbInit(void)
static struct UsbDriver usb_driver;
memset(&usb_driver, 0, sizeof(struct UsbDriver));
ret = BoardUsbBusInit(&usb_bus, &usb_driver);
if (EOK != ret) {
KPrintf("board_usb_Init error ret %u\n", ret);
@ -115,7 +114,7 @@ int Stm32HwUsbInit(void)
}
ret = BoardUsbDevBend();
if (EOK != ret){
if (EOK != ret) {
KPrintf("board_usb_Init error ret %u\n", ret);
return ERROR;
}

18
board/aiit-arm32-board/third_party_driver/watchdog/connect_wdg.c
View File

@ -65,16 +65,16 @@ static uint32 WdtConfigure(void *drv, struct BusConfigureInfo *args)
{
switch (args->configure_cmd)
{
case OPER_WDT_SET_TIMEOUT:
if (WdgSet((uint16_t)*(int *)args->private_data) != 0) {
case OPER_WDT_SET_TIMEOUT:
if (WdgSet((uint16_t)*(int *)args->private_data) != 0) {
return ERROR;
}
break;
case OPER_WDT_KEEPALIVE:
IWDG_ReloadCounter();
break;
default:
return ERROR;
}
break;
case OPER_WDT_KEEPALIVE:
IWDG_ReloadCounter();
break;
default:
return ERROR;
}
return EOK;
}

6
board/aiit-riscv64-board/third_party_driver/ch376/connect_ch376.c
View File

@ -49,7 +49,7 @@ static uint32 Ch376Configure(void *drv, struct BusConfigureInfo *configure_info)
static int HwCh376RxInd(void *dev, x_size_t length)
{
sdio.MsgLen += length;
sdio.msg_len += length;
KSemaphoreAbandon(sdio.sem);
return EOK;
@ -115,9 +115,9 @@ static uint32 Ch376Read(void *dev, struct BusBlockReadParam *read_param)
{
if (KSemaphoreObtain(sdio.sem, WAITING_FOREVER) == EOK) {
while(KSemaphoreObtain(sdio.sem, TICK_PER_SECOND) != -ETIMEOUT);
read_param->size = sdio.MsgLen;
read_param->size = sdio.msg_len;
BusDevReadData(sdio.dev, read_param);
sdio.MsgLen = 0;
sdio.msg_len = 0;
}
return read_param->read_length;

210
board/aiit-riscv64-board/third_party_driver/ch438/connect_ch438.c
View File

@ -23,29 +23,29 @@
#include <gpiohs.h>
#include <sleep.h>
static uint8 offsetadd[] = {0x00,0x10,0x20,0x30,0x08,0x18,0x28,0x38,}; /* Offset address of serial port number */
static uint8 Interruptnum[8] = {0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80,};
static uint8 offset_addr[] = {0x00,0x10,0x20,0x30,0x08,0x18,0x28,0x38,}; /* Offset address of serial port number */
static uint8 interrupt_num[8] = {0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80,};
static BusType ch438_pin;
static int Ch438Sem = NONE;
static int ch438_sem = NONE;
static plic_irq_callback_t Ch438Irq(void *parameter)
{
KSemaphoreAbandon(Ch438Sem);
KSemaphoreAbandon(ch438_sem);
}
static void CH438SetOutput(void)
{
struct PinParam PinCfg;
struct PinParam pin_cfg;
int ret = 0;
struct BusConfigureInfo configure_info;
configure_info.configure_cmd = OPE_CFG;
configure_info.private_data = (void *)&PinCfg;
configure_info.private_data = (void *)&pin_cfg;
PinCfg.cmd = GPIO_CONFIG_MODE;
PinCfg.pin = BSP_CH438_D0_PIN;
PinCfg.mode = GPIO_CFG_OUTPUT;
pin_cfg.cmd = GPIO_CONFIG_MODE;
pin_cfg.pin = BSP_CH438_D0_PIN;
pin_cfg.mode = GPIO_CFG_OUTPUT;
ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
if (ret != EOK) {
@ -53,49 +53,49 @@ static void CH438SetOutput(void)
return ;
}
PinCfg.pin = BSP_CH438_D1_PIN;
pin_cfg.pin = BSP_CH438_D1_PIN;
ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
if (ret != EOK) {
KPrintf("config CH438_D1_PIN pin %d failed!\n", BSP_CH438_D1_PIN);
return ;
}
PinCfg.pin = BSP_CH438_D2_PIN;
pin_cfg.pin = BSP_CH438_D2_PIN;
ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
if (ret != EOK) {
KPrintf("config CH438_D2_PIN pin %d failed!\n", BSP_CH438_D2_PIN);
return ;
}
PinCfg.pin = BSP_CH438_D3_PIN;
pin_cfg.pin = BSP_CH438_D3_PIN;
ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
if (ret != EOK) {
KPrintf("config CH438_D3_PIN pin %d failed!\n", BSP_CH438_D3_PIN);
return ;
}
PinCfg.pin = BSP_CH438_D4_PIN;
pin_cfg.pin = BSP_CH438_D4_PIN;
ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
if (ret != EOK) {
KPrintf("config CH438_D4_PIN pin %d failed!\n", BSP_CH438_D4_PIN);
return ;
}
PinCfg.pin = BSP_CH438_D5_PIN;
pin_cfg.pin = BSP_CH438_D5_PIN;
ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
if (ret != EOK) {
KPrintf("config CH438_D5_PIN pin %d failed!\n", BSP_CH438_D5_PIN);
return ;
}
PinCfg.pin = BSP_CH438_D6_PIN;
pin_cfg.pin = BSP_CH438_D6_PIN;
ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
if (ret != EOK) {
KPrintf("config CH438_D6_PIN pin %d failed!\n", BSP_CH438_D6_PIN);
return ;
}
PinCfg.pin = BSP_CH438_D7_PIN;
pin_cfg.pin = BSP_CH438_D7_PIN;
ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
if (ret != EOK) {
KPrintf("config CH438_D7_PIN pin %d failed!\n", BSP_CH438_D7_PIN);
@ -105,65 +105,65 @@ static void CH438SetOutput(void)
static void CH438SetInput(void)
{
struct PinParam PinCfg;
struct PinParam pin_cfg;
int ret = 0;
struct BusConfigureInfo configure_info;
configure_info.configure_cmd = OPE_CFG;
configure_info.private_data = (void *)&PinCfg;
configure_info.private_data = (void *)&pin_cfg;
PinCfg.cmd = GPIO_CONFIG_MODE;
PinCfg.pin = BSP_CH438_D0_PIN;
PinCfg.mode = GPIO_CFG_INPUT_PULLUP;
pin_cfg.cmd = GPIO_CONFIG_MODE;
pin_cfg.pin = BSP_CH438_D0_PIN;
pin_cfg.mode = GPIO_CFG_INPUT_PULLUP;
ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
if (ret != EOK) {
KPrintf("config CH438_D0_PIN pin %d INPUT_PULLUP failed!\n", BSP_CH438_D0_PIN);
return ;
}
PinCfg.pin = BSP_CH438_D1_PIN;
pin_cfg.pin = BSP_CH438_D1_PIN;
ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
if (ret != EOK) {
KPrintf("config CH438_D1_PIN pin %d INPUT_PULLUP failed!\n", BSP_CH438_D1_PIN);
return ;
}
PinCfg.pin = BSP_CH438_D2_PIN;
pin_cfg.pin = BSP_CH438_D2_PIN;
ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
if (ret != EOK) {
KPrintf("config CH438_D2_PIN pin %d INPUT_PULLUP failed!\n", BSP_CH438_D2_PIN);
return ;
}
PinCfg.pin = BSP_CH438_D3_PIN;
pin_cfg.pin = BSP_CH438_D3_PIN;
ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
if (ret != EOK) {
KPrintf("config CH438_D3_PIN pin %d INPUT_PULLUP failed!\n", BSP_CH438_D3_PIN);
return ;
}
PinCfg.pin = BSP_CH438_D4_PIN;
pin_cfg.pin = BSP_CH438_D4_PIN;
ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
if (ret != EOK) {
KPrintf("config CH438_D4_PIN pin %d INPUT_PULLUP failed!\n", BSP_CH438_D4_PIN);
return ;
}
PinCfg.pin = BSP_CH438_D5_PIN;
pin_cfg.pin = BSP_CH438_D5_PIN;
ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
if (ret != EOK) {
KPrintf("config CH438_D5_PIN pin %d INPUT_PULLUP failed!\n", BSP_CH438_D5_PIN);
return ;
}
PinCfg.pin = BSP_CH438_D6_PIN;
pin_cfg.pin = BSP_CH438_D6_PIN;
ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
if (ret != EOK) {
KPrintf("config CH438_D6_PIN pin %d INPUT_PULLUP failed!\n", BSP_CH438_D6_PIN);
return ;
}
PinCfg.pin = BSP_CH438_D7_PIN;
pin_cfg.pin = BSP_CH438_D7_PIN;
ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
if (ret != EOK) {
KPrintf("config CH438_D7_PIN pin %d INPUT_PULLUP failed!\n", BSP_CH438_D7_PIN);
@ -586,8 +586,8 @@ void CH438UartSend( uint8 ext_uart_no,uint8 *Data, uint8 Num )
{
uint8 REG_LSR_ADDR,REG_THR_ADDR;
REG_LSR_ADDR = offsetadd[ext_uart_no] | REG_LSR0_ADDR;
REG_THR_ADDR = offsetadd[ext_uart_no] | REG_THR0_ADDR;
REG_LSR_ADDR = offset_addr[ext_uart_no] | REG_LSR0_ADDR;
REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR;
while (1)
{
@ -612,8 +612,8 @@ uint8 CH438UARTRcv(uint8 ext_uart_no, uint8 *buf, x_size_t size )
uint8 *read_buffer;
x_size_t buffer_index = 0;
REG_LSR_ADDR = offsetadd[ext_uart_no] | REG_LSR0_ADDR;
REG_RBR_ADDR = offsetadd[ext_uart_no] | REG_RBR0_ADDR;
REG_LSR_ADDR = offset_addr[ext_uart_no] | REG_LSR0_ADDR;
REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR;
read_buffer = buf;
@ -653,15 +653,15 @@ void CH438_PORT_INIT( uint8 ext_uart_no,uint32 BaudRate )
uint8 REG_THR_ADDR;
uint8 REG_IIR_ADDR;
REG_LCR_ADDR = offsetadd[ext_uart_no] | REG_LCR0_ADDR;
REG_DLL_ADDR = offsetadd[ext_uart_no] | REG_DLL0_ADDR;
REG_DLM_ADDR = offsetadd[ext_uart_no] | REG_DLM0_ADDR;
REG_IER_ADDR = offsetadd[ext_uart_no] | REG_IER0_ADDR;
REG_MCR_ADDR = offsetadd[ext_uart_no] | REG_MCR0_ADDR;
REG_FCR_ADDR = offsetadd[ext_uart_no] | REG_FCR0_ADDR;
REG_RBR_ADDR = offsetadd[ext_uart_no] | REG_RBR0_ADDR;
REG_THR_ADDR = offsetadd[ext_uart_no] | REG_THR0_ADDR;
REG_IIR_ADDR = offsetadd[ext_uart_no] | REG_IIR0_ADDR;
REG_LCR_ADDR = offset_addr[ext_uart_no] | REG_LCR0_ADDR;
REG_DLL_ADDR = offset_addr[ext_uart_no] | REG_DLL0_ADDR;
REG_DLM_ADDR = offset_addr[ext_uart_no] | REG_DLM0_ADDR;
REG_IER_ADDR = offset_addr[ext_uart_no] | REG_IER0_ADDR;
REG_MCR_ADDR = offset_addr[ext_uart_no] | REG_MCR0_ADDR;
REG_FCR_ADDR = offset_addr[ext_uart_no] | REG_FCR0_ADDR;
REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR;
REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR;
REG_IIR_ADDR = offset_addr[ext_uart_no] | REG_IIR0_ADDR;
WriteCH438Data(REG_IER_ADDR, BIT_IER_RESET); /* Reset the serial port */
MdelayKTask(50);
@ -704,15 +704,15 @@ void CH438PortInitParityCheck(uint8 ext_uart_no,uint32 BaudRate)
uint8 REG_THR_ADDR;
uint8 REG_IIR_ADDR;
REG_LCR_ADDR = offsetadd[ext_uart_no] | REG_LCR0_ADDR;
REG_DLL_ADDR = offsetadd[ext_uart_no] | REG_DLL0_ADDR;
REG_DLM_ADDR = offsetadd[ext_uart_no] | REG_DLM0_ADDR;
REG_IER_ADDR = offsetadd[ext_uart_no] | REG_IER0_ADDR;
REG_MCR_ADDR = offsetadd[ext_uart_no] | REG_MCR0_ADDR;
REG_FCR_ADDR = offsetadd[ext_uart_no] | REG_FCR0_ADDR;
REG_RBR_ADDR = offsetadd[ext_uart_no] | REG_RBR0_ADDR;
REG_THR_ADDR = offsetadd[ext_uart_no] | REG_THR0_ADDR;
REG_IIR_ADDR = offsetadd[ext_uart_no] | REG_IIR0_ADDR;
REG_LCR_ADDR = offset_addr[ext_uart_no] | REG_LCR0_ADDR;
REG_DLL_ADDR = offset_addr[ext_uart_no] | REG_DLL0_ADDR;
REG_DLM_ADDR = offset_addr[ext_uart_no] | REG_DLM0_ADDR;
REG_IER_ADDR = offset_addr[ext_uart_no] | REG_IER0_ADDR;
REG_MCR_ADDR = offset_addr[ext_uart_no] | REG_MCR0_ADDR;
REG_FCR_ADDR = offset_addr[ext_uart_no] | REG_FCR0_ADDR;
REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR;
REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR;
REG_IIR_ADDR = offset_addr[ext_uart_no] | REG_IIR0_ADDR;
WriteCH438Data(REG_IER_ADDR, BIT_IER_RESET);/* Reset the serial port */
MdelayKTask(50);
@ -755,15 +755,15 @@ void CH438_PORT_DISABLE(uint8 ext_uart_no, uint32 BaudRate)
uint8 REG_THR_ADDR;
uint8 REG_IIR_ADDR;
REG_LCR_ADDR = offsetadd[ext_uart_no] | REG_LCR0_ADDR;
REG_DLL_ADDR = offsetadd[ext_uart_no] | REG_DLL0_ADDR;
REG_DLM_ADDR = offsetadd[ext_uart_no] | REG_DLM0_ADDR;
REG_IER_ADDR = offsetadd[ext_uart_no] | REG_IER0_ADDR;
REG_MCR_ADDR = offsetadd[ext_uart_no] | REG_MCR0_ADDR;
REG_FCR_ADDR = offsetadd[ext_uart_no] | REG_FCR0_ADDR;
REG_RBR_ADDR = offsetadd[ext_uart_no] | REG_RBR0_ADDR;
REG_THR_ADDR = offsetadd[ext_uart_no] | REG_THR0_ADDR;
REG_IIR_ADDR = offsetadd[ext_uart_no] | REG_IIR0_ADDR;
REG_LCR_ADDR = offset_addr[ext_uart_no] | REG_LCR0_ADDR;
REG_DLL_ADDR = offset_addr[ext_uart_no] | REG_DLL0_ADDR;
REG_DLM_ADDR = offset_addr[ext_uart_no] | REG_DLM0_ADDR;
REG_IER_ADDR = offset_addr[ext_uart_no] | REG_IER0_ADDR;
REG_MCR_ADDR = offset_addr[ext_uart_no] | REG_MCR0_ADDR;
REG_FCR_ADDR = offset_addr[ext_uart_no] | REG_FCR0_ADDR;
REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR;
REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR;
REG_IIR_ADDR = offset_addr[ext_uart_no] | REG_IIR0_ADDR;
WriteCH438Data(REG_IER_ADDR, BIT_IER_RESET); /* Reset the serial port */
MdelayKTask(50);
@ -806,15 +806,15 @@ void CH438_PORT6_INIT(uint8 ext_uart_no, uint32 BaudRate)
uint8 REG_THR_ADDR;
uint8 REG_IIR_ADDR;
REG_LCR_ADDR = offsetadd[ext_uart_no] | REG_LCR0_ADDR;
REG_DLL_ADDR = offsetadd[ext_uart_no] | REG_DLL0_ADDR;
REG_DLM_ADDR = offsetadd[ext_uart_no] | REG_DLM0_ADDR;
REG_IER_ADDR = offsetadd[ext_uart_no] | REG_IER0_ADDR;
REG_MCR_ADDR = offsetadd[ext_uart_no] | REG_MCR0_ADDR;
REG_FCR_ADDR = offsetadd[ext_uart_no] | REG_FCR0_ADDR;
REG_RBR_ADDR = offsetadd[ext_uart_no] | REG_RBR0_ADDR;
REG_THR_ADDR = offsetadd[ext_uart_no] | REG_THR0_ADDR;
REG_IIR_ADDR = offsetadd[ext_uart_no] | REG_IIR0_ADDR;
REG_LCR_ADDR = offset_addr[ext_uart_no] | REG_LCR0_ADDR;
REG_DLL_ADDR = offset_addr[ext_uart_no] | REG_DLL0_ADDR;
REG_DLM_ADDR = offset_addr[ext_uart_no] | REG_DLM0_ADDR;
REG_IER_ADDR = offset_addr[ext_uart_no] | REG_IER0_ADDR;
REG_MCR_ADDR = offset_addr[ext_uart_no] | REG_MCR0_ADDR;
REG_FCR_ADDR = offset_addr[ext_uart_no] | REG_FCR0_ADDR;
REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR;
REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR;
REG_IIR_ADDR = offset_addr[ext_uart_no] | REG_IIR0_ADDR;
WriteCH438Data(REG_IER_ADDR, BIT_IER_RESET);/* Reset the serial port */
MdelayKTask(50);
@ -875,13 +875,13 @@ static uint32 Ch438Init(struct SerialDriver *serial_drv, struct SerialCfgParam *
{
NULL_PARAM_CHECK(serial_drv);
struct PinParam PinCfg;
struct PinParam pin_cfg;
struct PinStat pin_stat;
int ret = 0;
struct BusConfigureInfo configure_info;
configure_info.configure_cmd = OPE_CFG;
configure_info.private_data = (void *)&PinCfg;
configure_info.private_data = (void *)&pin_cfg;
struct BusBlockWriteParam write_param;
write_param.buffer = (void *)&pin_stat;
@ -891,9 +891,9 @@ static uint32 Ch438Init(struct SerialDriver *serial_drv, struct SerialCfgParam *
CH438SetOutput();
/* config NWR pin as output*/
PinCfg.cmd = GPIO_CONFIG_MODE;
PinCfg.pin = BSP_CH438_NWR_PIN;
PinCfg.mode = GPIO_CFG_OUTPUT;
pin_cfg.cmd = GPIO_CONFIG_MODE;
pin_cfg.pin = BSP_CH438_NWR_PIN;
pin_cfg.mode = GPIO_CFG_OUTPUT;
ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
if (ret != EOK) {
@ -902,7 +902,7 @@ static uint32 Ch438Init(struct SerialDriver *serial_drv, struct SerialCfgParam *
}
/* config NRD pin as output*/
PinCfg.pin = BSP_CH438_NRD_PIN;
pin_cfg.pin = BSP_CH438_NRD_PIN;
ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
if (ret != EOK) {
KPrintf("config NRD pin %d failed!\n", BSP_CH438_NRD_PIN);
@ -910,7 +910,7 @@ static uint32 Ch438Init(struct SerialDriver *serial_drv, struct SerialCfgParam *
}
/* config ALE pin as output*/
PinCfg.pin = BSP_CH438_ALE_PIN;
pin_cfg.pin = BSP_CH438_ALE_PIN;
ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
if (ret != EOK) {
KPrintf("config ALE pin %d failed!\n", BSP_CH438_ALE_PIN);
@ -918,7 +918,7 @@ static uint32 Ch438Init(struct SerialDriver *serial_drv, struct SerialCfgParam *
}
/* config ALE pin as output*/
PinCfg.pin = BSP_485_dir;
pin_cfg.pin = BSP_485_dir;
ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
if (ret != EOK) {
KPrintf("config ALE pin %d failed!\n", BSP_485_dir);
@ -926,8 +926,8 @@ static uint32 Ch438Init(struct SerialDriver *serial_drv, struct SerialCfgParam *
}
/* config ALE pin as input pullup*/
PinCfg.pin = BSP_CH438_INT_PIN;
PinCfg.mode = GPIO_CFG_INPUT_PULLUP;
pin_cfg.pin = BSP_CH438_INT_PIN;
pin_cfg.mode = GPIO_CFG_INPUT_PULLUP;
ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
if (ret != EOK) {
KPrintf("config INIT pin %d failed!\n", BSP_CH438_INT_PIN);
@ -1012,7 +1012,7 @@ static uint32 Ch438ReadData(void *dev, struct BusBlockReadParam *read_param)
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)dev;
struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
result = KSemaphoreObtain(Ch438Sem, WAITING_FOREVER);
result = KSemaphoreObtain(ch438_sem, WAITING_FOREVER);
if (EOK == result) {
gInterruptStatus = ReadCH438Data(REG_SSR_ADDR);
@ -1027,18 +1027,18 @@ static uint32 Ch438ReadData(void *dev, struct BusBlockReadParam *read_param)
dat = ReadCH438Data(REG_IIR0_ADDR);
dat = dat;
} else {
if ( gInterruptStatus & Interruptnum[dev_param->ext_uart_no]) { /* Detect which serial port is interrupted */
REG_LCR_ADDR = offsetadd[dev_param->ext_uart_no] | REG_LCR0_ADDR;
REG_DLL_ADDR = offsetadd[dev_param->ext_uart_no] | REG_DLL0_ADDR;
REG_DLM_ADDR = offsetadd[dev_param->ext_uart_no] | REG_DLM0_ADDR;
REG_IER_ADDR = offsetadd[dev_param->ext_uart_no] | REG_IER0_ADDR;
REG_MCR_ADDR = offsetadd[dev_param->ext_uart_no] | REG_MCR0_ADDR;
REG_FCR_ADDR = offsetadd[dev_param->ext_uart_no] | REG_FCR0_ADDR;
REG_RBR_ADDR = offsetadd[dev_param->ext_uart_no] | REG_RBR0_ADDR;
REG_THR_ADDR = offsetadd[dev_param->ext_uart_no] | REG_THR0_ADDR;
REG_IIR_ADDR = offsetadd[dev_param->ext_uart_no] | REG_IIR0_ADDR;
REG_LSR_ADDR = offsetadd[dev_param->ext_uart_no] | REG_LSR0_ADDR;
REG_MSR_ADDR = offsetadd[dev_param->ext_uart_no] | REG_MSR0_ADDR;
if ( gInterruptStatus & interrupt_num[dev_param->ext_uart_no]) { /* Detect which serial port is interrupted */
REG_LCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_LCR0_ADDR;
REG_DLL_ADDR = offset_addr[dev_param->ext_uart_no] | REG_DLL0_ADDR;
REG_DLM_ADDR = offset_addr[dev_param->ext_uart_no] | REG_DLM0_ADDR;
REG_IER_ADDR = offset_addr[dev_param->ext_uart_no] | REG_IER0_ADDR;
REG_MCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_MCR0_ADDR;
REG_FCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_FCR0_ADDR;
REG_RBR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_RBR0_ADDR;
REG_THR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_THR0_ADDR;
REG_IIR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_IIR0_ADDR;
REG_LSR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_LSR0_ADDR;
REG_MSR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_MSR0_ADDR;
/* The interrupted state of a read serial port */
InterruptStatus = ReadCH438Data(REG_IIR_ADDR) & 0x0f;
@ -1079,45 +1079,45 @@ static const struct SerialDevDone dev_done =
static void Ch438InitDefault(struct SerialDriver *serial_drv)
{
struct PinParam PinCfg;
struct PinParam pin_cfg;
BusType ch438_pin;
struct BusConfigureInfo configure_info;
int ret = 0;
configure_info.configure_cmd = OPE_CFG;
configure_info.private_data = (void *)&PinCfg;
configure_info.private_data = (void *)&pin_cfg;
Ch438Sem = KSemaphoreCreate(0);
if (Ch438Sem < 0) {
ch438_sem = KSemaphoreCreate(0);
if (ch438_sem < 0) {
KPrintf("Ch438InitDefault create sem failed .\n");
return ;
}
ch438_pin = PinBusInitGet();
PinCfg.cmd = GPIO_CONFIG_MODE;
PinCfg.pin = BSP_CH438_INT_PIN;
PinCfg.mode = GPIO_CFG_INPUT_PULLUP;
pin_cfg.cmd = GPIO_CONFIG_MODE;
pin_cfg.pin = BSP_CH438_INT_PIN;
pin_cfg.mode = GPIO_CFG_INPUT_PULLUP;
ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
if (ret != EOK) {
KPrintf("config BSP_CH438_INT_PIN pin %d failed!\n", BSP_CH438_INT_PIN);
return;
}
PinCfg.cmd = GPIO_IRQ_REGISTER;
PinCfg.pin = BSP_CH438_INT_PIN;
PinCfg.irq_set.irq_mode = GPIO_IRQ_EDGE_FALLING;
PinCfg.irq_set.hdr = (void *)Ch438Irq;
PinCfg.irq_set.args = NONE;
pin_cfg.cmd = GPIO_IRQ_REGISTER;
pin_cfg.pin = BSP_CH438_INT_PIN;
pin_cfg.irq_set.irq_mode = GPIO_IRQ_EDGE_FALLING;
pin_cfg.irq_set.hdr = (void *)Ch438Irq;
pin_cfg.irq_set.args = NONE;
ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
if (ret != EOK) {
KPrintf("config BSP_CH438_INT_PIN %d failed!\n", BSP_CH438_INT_PIN);
return;
}
PinCfg.cmd = GPIO_IRQ_ENABLE;
PinCfg.pin = BSP_CH438_INT_PIN;
pin_cfg.cmd = GPIO_IRQ_ENABLE;
pin_cfg.pin = BSP_CH438_INT_PIN;
ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
if (ret != EOK) {
KPrintf("config BSP_CH438_INT_PIN %d failed!\n", BSP_CH438_INT_PIN);

10
board/aiit-riscv64-board/third_party_driver/i2c/connect_i2c.c
View File

@ -52,11 +52,11 @@ static I2cBusParam i2c_bus_param =
#define SET_SDA(done, val) done->SetSdaState(done->data, val)
#define SET_SCL(done, val) done->SetSclState(done->data, val)
#define GET_SDA(done) done->GetSdaState(done->data)
#define GET_SCL(done) done->GetSclState(done->data)
#define SdaLow(done) SET_SDA(done, 0)
#define SdaHigh(done) SET_SDA(done, 1)
#define SclLow(done) SET_SCL(done, 0)
#define GET_SDA(done) done->GetSdaState(done->data)
#define GET_SCL(done) done->GetSclState(done->data)
#define SdaLow(done) SET_SDA(done, 0)
#define SdaHigh(done) SET_SDA(done, 1)
#define SclLow(done) SET_SCL(done, 0)
void I2cGpioInit(const I2cBusParam *bus_param)
{

2
board/aiit-riscv64-board/third_party_driver/include/connect_ch376.h
View File

@ -26,7 +26,7 @@
struct HwCh376
{
HardwareDevType dev;
x_size_t MsgLen;
x_size_t msg_len;
int sem;
KTaskDescriptorType task;
};

144
board/aiit-riscv64-board/third_party_driver/include/connect_ch438.h
View File

@ -31,47 +31,47 @@
#define REG_RBR0_ADDR 0x00 /* serial port0receive buffer register address */
#define REG_THR0_ADDR 0x00 /* serial port0send hold register address */
#define REG_IER0_ADDR 0x01 /* serial port0interrupt enable register address */
#define REG_IIR0_ADDR 0x02 /* serial port0interrupt identifies register address */
#define REG_IER0_ADDR 0x01 /* serial port0interrupt enable register address */
#define REG_IIR0_ADDR 0x02 /* serial port0interrupt identifies register address */
#define REG_FCR0_ADDR 0x02 /* serial port0FIFO controls register address */
#define REG_LCR0_ADDR 0x03 /* serial port0circuit control register address */
#define REG_MCR0_ADDR 0x04 /* serial port0MODEM controls register address */
#define REG_LSR0_ADDR 0x05 /* serial port0line status register address */
#define REG_MSR0_ADDR 0x06 /* serial port0address of MODEM status register */
#define REG_MCR0_ADDR 0x04 /* serial port0MODEM controls register address */
#define REG_LSR0_ADDR 0x05 /* serial port0line status register address */
#define REG_MSR0_ADDR 0x06 /* serial port0address of MODEM status register */
#define REG_SCR0_ADDR 0x07 /* serial port0the user can define the register address */
#define REG_DLL0_ADDR 0x00 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM0_ADDR 0x01 /* Baud rate divisor latch high 8-bit byte address */
#define REG_DLM0_ADDR 0x01 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port1 register address */
#define REG_RBR1_ADDR 0x10 /* serial port1receive buffer register address */
#define REG_THR1_ADDR 0x10 /* serial port1send hold register address */
#define REG_IER1_ADDR 0x11 /* serial port1interrupt enable register address */
#define REG_IIR1_ADDR 0x12 /* serial port1interrupt identifies register address */
#define REG_IER1_ADDR 0x11 /* serial port1interrupt enable register address */
#define REG_IIR1_ADDR 0x12 /* serial port1interrupt identifies register address */
#define REG_FCR1_ADDR 0x12 /* serial port1FIFO controls register address */
#define REG_LCR1_ADDR 0x13 /* serial port1circuit control register address */
#define REG_MCR1_ADDR 0x14 /* serial port1MODEM controls register address */
#define REG_MCR1_ADDR 0x14 /* serial port1MODEM controls register address */
#define REG_LSR1_ADDR 0x15 /* serial port1line status register address */
#define REG_MSR1_ADDR 0x16 /* serial port1address of MODEM status register */
#define REG_MSR1_ADDR 0x16 /* serial port1address of MODEM status register */
#define REG_SCR1_ADDR 0x17 /* serial port1the user can define the register address */
#define REG_DLL1_ADDR 0x10 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM1_ADDR 0x11 /* Baud rate divisor latch high 8-bit byte address */
#define REG_DLM1_ADDR 0x11 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port2 register address */
#define REG_RBR2_ADDR 0x20 /* serial port2receive buffer register address */
#define REG_THR2_ADDR 0x20 /* serial port2send hold register address */
#define REG_IER2_ADDR 0x21 /* serial port2interrupt enable register address */
#define REG_IIR2_ADDR 0x22 /* serial port2interrupt identifies register address */
#define REG_IER2_ADDR 0x21 /* serial port2interrupt enable register address */
#define REG_IIR2_ADDR 0x22 /* serial port2interrupt identifies register address */
#define REG_FCR2_ADDR 0x22 /* serial port2FIFO controls register address */
#define REG_LCR2_ADDR 0x23 /* serial port2circuit control register address */
#define REG_MCR2_ADDR 0x24 /* serial port2MODEM controls register address */
#define REG_MCR2_ADDR 0x24 /* serial port2MODEM controls register address */
#define REG_LSR2_ADDR 0x25 /* serial port2line status register address */
#define REG_MSR2_ADDR 0x26 /* serial port2address of MODEM status register */
#define REG_MSR2_ADDR 0x26 /* serial port2address of MODEM status register */
#define REG_SCR2_ADDR 0x27 /* serial port2the user can define the register address */
#define REG_DLL2_ADDR 0x20 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM2_ADDR 0x21 /* Baud rate divisor latch high 8-bit byte address */
#define REG_DLM2_ADDR 0x21 /* Baud rate divisor latch high 8-bit byte address */
@ -79,32 +79,32 @@
#define REG_RBR3_ADDR 0x30 /* serial port3receive buffer register address */
#define REG_THR3_ADDR 0x30 /* serial port3send hold register address */
#define REG_IER3_ADDR 0x31 /* serial port3interrupt enable register address */
#define REG_IIR3_ADDR 0x32 /* serial port3interrupt identifies register address */
#define REG_IER3_ADDR 0x31 /* serial port3interrupt enable register address */
#define REG_IIR3_ADDR 0x32 /* serial port3interrupt identifies register address */
#define REG_FCR3_ADDR 0x32 /* serial port3FIFO controls register address */
#define REG_LCR3_ADDR 0x33 /* serial port3circuit control register address */
#define REG_MCR3_ADDR 0x34 /* serial port3MODEM controls register address */
#define REG_MCR3_ADDR 0x34 /* serial port3MODEM controls register address */
#define REG_LSR3_ADDR 0x35 /* serial port3line status register address */
#define REG_MSR3_ADDR 0x36 /* serial port3address of MODEM status register */
#define REG_MSR3_ADDR 0x36 /* serial port3address of MODEM status register */
#define REG_SCR3_ADDR 0x37 /* serial port3the user can define the register address */
#define REG_DLL3_ADDR 0x30 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM3_ADDR 0x31 /* Baud rate divisor latch high 8-bit byte address */
#define REG_DLM3_ADDR 0x31 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port4 register address */
#define REG_RBR4_ADDR 0x08 /* serial port4receive buffer register address */
#define REG_THR4_ADDR 0x08 /* serial port4send hold register address */
#define REG_IER4_ADDR 0x09 /* serial port4interrupt enable register address */
#define REG_IIR4_ADDR 0x0A /* serial port4interrupt identifies register address */
#define REG_IER4_ADDR 0x09 /* serial port4interrupt enable register address */
#define REG_IIR4_ADDR 0x0A /* serial port4interrupt identifies register address */
#define REG_FCR4_ADDR 0x0A /* serial port4FIFO controls register address */
#define REG_LCR4_ADDR 0x0B /* serial port4circuit control register address */
#define REG_MCR4_ADDR 0x0C /* serial port4MODEM controls register address */
#define REG_MCR4_ADDR 0x0C /* serial port4MODEM controls register address */
#define REG_LSR4_ADDR 0x0D /* serial port4line status register address */
#define REG_MSR4_ADDR 0x0E /* serial port4address of MODEM status register */
#define REG_MSR4_ADDR 0x0E /* serial port4address of MODEM status register */
#define REG_SCR4_ADDR 0x0F /* serial port4the user can define the register address */
#define REG_DLL4_ADDR 0x08 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM4_ADDR 0x09 /* Baud rate divisor latch high 8-bit byte address */
#define REG_DLM4_ADDR 0x09 /* Baud rate divisor latch high 8-bit byte address */
@ -112,48 +112,48 @@
#define REG_RBR5_ADDR 0x18 /* serial port5receive buffer register address */
#define REG_THR5_ADDR 0x18 /* serial port5send hold register address */
#define REG_IER5_ADDR 0x19 /* serial port5interrupt enable register address */
#define REG_IIR5_ADDR 0x1A /* serial port5interrupt identifies register address */
#define REG_IER5_ADDR 0x19 /* serial port5interrupt enable register address */
#define REG_IIR5_ADDR 0x1A /* serial port5interrupt identifies register address */
#define REG_FCR5_ADDR 0x1A /* serial port5FIFO controls register address */
#define REG_LCR5_ADDR 0x1B /* serial port5circuit control register address */
#define REG_MCR5_ADDR 0x1C /* serial port5MODEM controls register address */
#define REG_MCR5_ADDR 0x1C /* serial port5MODEM controls register address */
#define REG_LSR5_ADDR 0x1D /* serial port5line status register address */
#define REG_MSR5_ADDR 0x1E /* serial port5address of MODEM status register */
#define REG_MSR5_ADDR 0x1E /* serial port5address of MODEM status register */
#define REG_SCR5_ADDR 0x1F /* serial port5the user can define the register address */
#define REG_DLL5_ADDR 0x18 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM5_ADDR 0x19 /* Baud rate divisor latch high 8-bit byte address */
#define REG_DLM5_ADDR 0x19 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port6 register address */
#define REG_RBR6_ADDR 0x28 /* serial port6receive buffer register address */
#define REG_THR6_ADDR 0x28 /* serial port6send hold register address */
#define REG_IER6_ADDR 0x29 /* serial port6interrupt enable register address */
#define REG_IIR6_ADDR 0x2A /* serial port6interrupt identifies register address */
#define REG_IER6_ADDR 0x29 /* serial port6interrupt enable register address */
#define REG_IIR6_ADDR 0x2A /* serial port6interrupt identifies register address */
#define REG_FCR6_ADDR 0x2A /* serial port6FIFO controls register address */
#define REG_LCR6_ADDR 0x2B /* serial port6circuit control register address */
#define REG_MCR6_ADDR 0x2C /* serial port6MODEM controls register address */
#define REG_MCR6_ADDR 0x2C /* serial port6MODEM controls register address */
#define REG_LSR6_ADDR 0x2D /* serial port6line status register address */
#define REG_MSR6_ADDR 0x2E /* serial port6address of MODEM status register */
#define REG_MSR6_ADDR 0x2E /* serial port6address of MODEM status register */
#define REG_SCR6_ADDR 0x2F /* serial port6the user can define the register address */
#define REG_DLL6_ADDR 0x28 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM6_ADDR 0x29 /* Baud rate divisor latch high 8-bit byte address */
#define REG_DLM6_ADDR 0x29 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port7 register address */
#define REG_RBR7_ADDR 0x38 /* serial port7receive buffer register address */
#define REG_THR7_ADDR 0x38 /* serial port7send hold register address */
#define REG_IER7_ADDR 0x39 /* serial port7interrupt enable register address */
#define REG_IIR7_ADDR 0x3A /* serial port7interrupt identifies register address */
#define REG_IER7_ADDR 0x39 /* serial port7interrupt enable register address */
#define REG_IIR7_ADDR 0x3A /* serial port7interrupt identifies register address */
#define REG_FCR7_ADDR 0x3A /* serial port7FIFO controls register address */
#define REG_LCR7_ADDR 0x3B /* serial port7circuit control register address */
#define REG_MCR7_ADDR 0x3C /* serial port7MODEM controls register address */
#define REG_MCR7_ADDR 0x3C /* serial port7MODEM controls register address */
#define REG_LSR7_ADDR 0x3D /* serial port7line status register address */
#define REG_MSR7_ADDR 0x3E /* serial port7address of MODEM status register */
#define REG_MSR7_ADDR 0x3E /* serial port7address of MODEM status register */
#define REG_SCR7_ADDR 0x3F /* serial port7the user can define the register address */
#define REG_DLL7_ADDR 0x38 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM7_ADDR 0x39 /* Baud rate divisor latch high 8-bit byte address */
#define REG_DLM7_ADDR 0x39 /* Baud rate divisor latch high 8-bit byte address */
#define REG_SSR_ADDR 0x4F /* pecial status register address */
@ -161,14 +161,14 @@
/* IER register bit */
#define BIT_IER_RESET 0x80 /* The bit is 1 soft reset serial port */
#define BIT_IER_RESET 0x80 /* The bit is 1 soft reset serial port */
#define BIT_IER_LOWPOWER 0x40 /* The bit is 1 close serial port internal reference clock */
#define BIT_IER_SLP 0x20 /* serial port0 is SLP, 1 close clock vibrator */
#define BIT_IER1_CK2X 0x20 /* serial port1 is CK2X, 1 force the external clock signal after 2 times as internal reference clock */
#define BIT_IER_IEMODEM 0x08 /* The bit is 1 allows MODEM input status to interrupt */
#define BIT_IER_IELINES 0x04 /* The bit is 1 allow receiving line status to be interrupted */
#define BIT_IER_IETHRE 0x02 /* The bit is 1 allows the send hold register to break in mid-air */
#define BIT_IER_IERECV 0x01 /* The bit is 1 allows receiving data interrupts */
#define BIT_IER_SLP 0x20 /* serial port0 is SLP, 1 close clock vibrator */
#define BIT_IER1_CK2X 0x20 /* serial port1 is CK2X, 1 force the external clock signal after 2 times as internal reference clock */
#define BIT_IER_IEMODEM 0x08 /* The bit is 1 allows MODEM input status to interrupt */
#define BIT_IER_IELINES 0x04 /* The bit is 1 allow receiving line status to be interrupted */
#define BIT_IER_IETHRE 0x02 /* The bit is 1 allows the send hold register to break in mid-air */
#define BIT_IER_IERECV 0x01 /* The bit is 1 allows receiving data interrupts */
/* IIR register bit */
@ -180,7 +180,7 @@
#define BIT_IIR_IID3 0x08
#define BIT_IIR_IID2 0x04
#define BIT_IIR_IID1 0x02
#define BIT_IIR_NOINT 0x01
#define BIT_IIR_NOINT 0x01
/* FCR register bit */
@ -190,18 +190,18 @@
#define BIT_FCR_TFIFORST 0x04 /* The bit is 1 empty the data sent in FIFO */
#define BIT_FCR_RFIFORST 0x02 /* The bit is 1 empty the data sent in FIFO */
#define BIT_FCR_FIFOEN 0x01 /* The bit is 1 use FIFO, 0 disable FIFO */
#define BIT_FCR_FIFOEN 0x01 /* The bit is 1 use FIFO, 0 disable FIFO */
/* LCR register bit */
#define BIT_LCR_DLAB 0x80 /* To access DLL, DLM, 0 to access RBR/THR/IER */
#define BIT_LCR_DLAB 0x80 /* To access DLL, DLM, 0 to access RBR/THR/IER */
#define BIT_LCR_BREAKEN 0x40 /* 1 forces a BREAK line interval*/
/* Set the check format: when PAREN is 1, 00 odd check, 01 even check, 10 MARK (set 1), 11 blank (SPACE, clear 0) */
#define BIT_LCR_PARMODE1 0x20 /* Sets the parity bit format */
#define BIT_LCR_PARMODE0 0x10 /* Sets the parity bit format */
#define BIT_LCR_PAREN 0x08 /* A value of 1 allows you to generate and receive parity bits when sending */
#define BIT_LCR_PAREN 0x08 /* A value of 1 allows you to generate and receive parity bits when sending */
#define BIT_LCR_STOPBIT 0x04 /* If is 1, then two stop bits, is 0, a stop bit */
/* Set word length: 00 for 5 data bits, 01 for 6 data bits, 10 for 7 data bits and 11 for 8 data bits */
@ -210,48 +210,48 @@
/* MCR register bit */
#define BIT_MCR_AFE 0x20 /* For 1 allows automatic flow control of CTS and RTS hardware */
#define BIT_MCR_AFE 0x20 /* For 1 allows automatic flow control of CTS and RTS hardware */
#define BIT_MCR_LOOP 0x10 /* Is the test mode of 1 enabling internal loop */
#define BIT_MCR_OUT2 0x08 /* 1 Allows an interrupt request for the serial port output */
#define BIT_MCR_OUT1 0x04 /* The MODEM control bit defined for the user */
#define BIT_MCR_RTS 0x02 /* The bit is 1 RTS pin output effective */
#define BIT_MCR_DTR 0x01 /* The bit is 1 DTR pin output effective */
#define BIT_MCR_RTS 0x02 /* The bit is 1 RTS pin output effective */
#define BIT_MCR_DTR 0x01 /* The bit is 1 DTR pin output effective */
/* LSR register bit */
#define BIT_LSR_RFIFOERR 0x80 /* 1 said There is at least one error in receiving FIFO */
#define BIT_LSR_TEMT 0x40 /* 1 said THR and TSR are empty */
#define BIT_LSR_THRE 0x20 /* 1 said THR is empty*/
#define BIT_LSR_TEMT 0x40 /* 1 said THR and TSR are empty */
#define BIT_LSR_THRE 0x20 /* 1 said THR is empty*/
#define BIT_LSR_BREAKINT 0x10 /* The bit is 1 said the BREAK line interval was detected*/
#define BIT_LSR_FRAMEERR 0x08 /* The bit is 1 said error reading data frame */
#define BIT_LSR_PARERR 0x04 /* The bit is 1 said parity error */
#define BIT_LSR_OVERR 0x02 /* 1 said receive FIFO buffer overflow */
#define BIT_LSR_DATARDY 0x01 /* The bit is 1 said receive data received in FIFO */
#define BIT_LSR_FRAMEERR 0x08 /* The bit is 1 said error reading data frame */
#define BIT_LSR_PARERR 0x04 /* The bit is 1 said parity error */
#define BIT_LSR_OVERR 0x02 /* 1 said receive FIFO buffer overflow */
#define BIT_LSR_DATARDY 0x01 /* The bit is 1 said receive data received in FIFO */
/* MSR register bit */
#define BIT_MSR_DCD 0x80 /* The bit is 1 said DCD pin effective */
#define BIT_MSR_RI 0x40 /* The bit is 1 said RI pin effective */
#define BIT_MSR_RI 0x40 /* The bit is 1 said RI pin effective */
#define BIT_MSR_DSR 0x20 /* The bit is 1 said DSR pin effective */
#define BIT_MSR_CTS 0x10 /* The bit is 1 said CTS pin effective */
#define BIT_MSR_DDCD 0x08 /* The bit is 1 said DCD pin The input state has changed */
#define BIT_MSR_CTS 0x10 /* The bit is 1 said CTS pin effective */
#define BIT_MSR_DDCD 0x08 /* The bit is 1 said DCD pin The input state has changed */
#define BIT_MSR_TERI 0x04 /* The bit is 1 said RI pin The input state has changed */
#define BIT_MSR_DDSR 0x02 /* The bit is 1 said DSR pin The input state has changed */
#define BIT_MSR_DCTS 0x01 /* The bit is 1 said CTS pin The input state has changed */
#define BIT_MSR_DDSR 0x02 /* The bit is 1 said DSR pin The input state has changed */
#define BIT_MSR_DCTS 0x01 /* The bit is 1 said CTS pin The input state has changed */
/* Interrupt status code */
#define INT_NOINT 0x01 /* There is no interruption */
#define INT_THR_EMPTY 0x02 /* THR empty interruption */
#define INT_RCV_OVERTIME 0x0C /* Receive timeout interrupt */
#define INT_RCV_SUCCESS 0x04 /* Interrupts are available to receive data */
#define INT_RCV_LINES 0x06 /* Receiving line status interrupted */
#define INT_NOINT 0x01 /* There is no interruption */
#define INT_THR_EMPTY 0x02 /* THR empty interruption */
#define INT_RCV_OVERTIME 0x0C /* Receive timeout interrupt */
#define INT_RCV_SUCCESS 0x04 /* Interrupts are available to receive data */
#define INT_RCV_LINES 0x06 /* Receiving line status interrupted */
#define INT_MODEM_CHANGE 0x00 /* MODEM input changes interrupt */
#define CH438_IIR_FIFOS_ENABLED 0xC0 /* use FIFO */
#define Fpclk 1843200 /* Define the internal clock frequency */
#define Fpclk 1843200 /* Define the internal clock frequency */
void Set485Input(uint8 ch_no);
void Set485Output(uint8 ch_no);

13
board/aiit-riscv64-board/third_party_driver/include/connect_lcd.h
View File

@ -40,16 +40,13 @@ Modification:
#include <sysctl.h>
#ifdef BSP_USING_TOUCH
#include "connect_touch.h"
#include "connect_touch.h"
#endif
void drv_lcd_clear(uint16_t color);
void LCD_DrawLine(uint16 x1, uint16 y1, uint16 x2, uint16 y2,uint16 color);
void LCD_DrawRectangle(uint16 x1, uint16 y1, uint16 x2, uint16 y2,uint16 color);
void LCD_Draw_Circle(uint16 x0,uint16 y0,uint8 r,uint16 color);
void DrvLcdClear(uint16_t color);
void LcdDrawLine(uint16 x1, uint16 y1, uint16 x2, uint16 y2,uint16 color);
void LcdDrawRectangle(uint16 x1, uint16 y1, uint16 x2, uint16 y2,uint16 color);
void LcdDrawCircle(uint16 x0,uint16 y0,uint8 r,uint16 color);
void LCD_ShowChar(uint16 x,uint16 y,uint8 num,uint8 size,uint16 color,uint16 back_color);
void LCD_ShowString(uint16 x,uint16 y,uint16 width,uint16 height,uint8 size,uint8 *p,uint16 color,uint16 back_color);
void Clear_handwriting (void);
int HwLcdInit(void);
#endif

16
board/aiit-riscv64-board/third_party_driver/include/connect_touch.h
View File

@ -26,15 +26,14 @@
#include "gpio.h"
#include <sleep.h>
#define TP_CLK 0
#define TP_CS 1
#define TP_MISO 2
#define TP_PEN 3
#define TP_MOSI 4
#define TP_CLK 0
#define TP_CS 1
#define TP_MISO 2
#define TP_PEN 3
#define TP_MOSI 4
#define TP_PRES_DOWN 0x80
#define TP_CATH_PRES 0x40
#define TP_CATH_PRES 0x40
//touch screen control struct
typedef struct
@ -52,7 +51,8 @@ typedef struct
extern touch_device_info tp_dev;
//save data struct
typedef struct {
typedef struct
{
int ty_xfac;
int ty_yfac;
short x_pos;

4
board/aiit-riscv64-board/third_party_driver/include/connect_uart.h
View File

@ -27,8 +27,8 @@
extern "C" {
#endif
#define KERNEL_CONSOLE_BUS_NAME SERIAL_BUS_NAME_0
#define KERNEL_CONSOLE_DRV_NAME SERIAL_DRV_NAME_0
#define KERNEL_CONSOLE_BUS_NAME SERIAL_BUS_NAME_0
#define KERNEL_CONSOLE_DRV_NAME SERIAL_DRV_NAME_0
#define KERNEL_CONSOLE_DEVICE_NAME SERIAL_0_DEVICE_NAME_0
int HwUartInit(void);

524
board/aiit-riscv64-board/third_party_driver/lcd/connect_lcd.c
View File

@ -41,82 +41,82 @@ Modification:
#include <gpiohs.h>
#include <graphic.h>
#define NO_OPERATION 0x00
#define SOFTWARE_RESET 0x01
#define READ_ID 0x04
#define READ_STATUS 0x09
#define READ_POWER_MODE 0x0A
#define READ_MADCTL 0x0B
#define READ_PIXEL_FORMAT 0x0C
#define READ_IMAGE_FORMAT 0x0D
#define READ_SIGNAL_MODE 0x0E
#define READ_SELT_DIAG_RESULT 0x0F
#define SLEEP_ON 0x10
#define SLEEP_OFF 0x11
#define PARTIAL_DISPALY_ON 0x12
#define NORMAL_DISPALY_ON 0x13
#define NO_OPERATION 0x00
#define SOFTWARE_RESET 0x01
#define READ_ID 0x04
#define READ_STATUS 0x09
#define READ_POWER_MODE 0x0A
#define READ_MADCTL 0x0B
#define READ_PIXEL_FORMAT 0x0C
#define READ_IMAGE_FORMAT 0x0D
#define READ_SIGNAL_MODE 0x0E
#define READ_SELT_DIAG_RESULT 0x0F
#define SLEEP_ON 0x10
#define SLEEP_OFF 0x11
#define PARTIAL_DISPALY_ON 0x12
#define NORMAL_DISPALY_ON 0x13
#define INVERSION_DISPALY_OFF 0x20
#define INVERSION_DISPALY_ON 0x21
#define GAMMA_SET 0x26
#define DISPALY_OFF 0x28
#define DISPALY_ON 0x29
#define HORIZONTAL_ADDRESS_SET 0x2A
#define VERTICAL_ADDRESS_SET 0x2B
#define MEMORY_WRITE 0x2C
#define COLOR_SET 0x2D
#define MEMORY_READ 0x2E
#define PARTIAL_AREA 0x30
#define VERTICAL_SCROL_DEFINE 0x33
#define TEAR_EFFECT_LINE_OFF 0x34
#define TEAR_EFFECT_LINE_ON 0x35
#define MEMORY_ACCESS_CTL 0x36
#define VERTICAL_SCROL_S_ADD 0x37
#define IDLE_MODE_OFF 0x38
#define IDLE_MODE_ON 0x39
#define PIXEL_FORMAT_SET 0x3A
#define WRITE_MEMORY_CONTINUE 0x3C
#define READ_MEMORY_CONTINUE 0x3E
#define SET_TEAR_SCANLINE 0x44
#define GET_SCANLINE 0x45
#define WRITE_BRIGHTNESS 0x51
#define READ_BRIGHTNESS 0x52
#define WRITE_CTRL_DISPALY 0x53
#define READ_CTRL_DISPALY 0x54
#define WRITE_BRIGHTNESS_CTL 0x55
#define READ_BRIGHTNESS_CTL 0x56
#define WRITE_MIN_BRIGHTNESS 0x5E
#define READ_MIN_BRIGHTNESS 0x5F
#define READ_ID1 0xDA
#define READ_ID2 0xDB
#define READ_ID3 0xDC
#define RGB_IF_SIGNAL_CTL 0xB0
#define NORMAL_FRAME_CTL 0xB1
#define IDLE_FRAME_CTL 0xB2
#define PARTIAL_FRAME_CTL 0xB3
#define INVERSION_CTL 0xB4
#define BLANK_PORCH_CTL 0xB5
#define DISPALY_FUNCTION_CTL 0xB6
#define ENTRY_MODE_SET 0xB7
#define BACKLIGHT_CTL1 0xB8
#define BACKLIGHT_CTL2 0xB9
#define BACKLIGHT_CTL3 0xBA
#define BACKLIGHT_CTL4 0xBB
#define BACKLIGHT_CTL5 0xBC
#define BACKLIGHT_CTL7 0xBE
#define BACKLIGHT_CTL8 0xBF
#define POWER_CTL1 0xC0
#define POWER_CTL2 0xC1
#define VCOM_CTL1 0xC5
#define VCOM_CTL2 0xC7
#define NV_MEMORY_WRITE 0xD0
#define NV_MEMORY_PROTECT_KEY 0xD1
#define NV_MEMORY_STATUS_READ 0xD2
#define READ_ID4 0xD3
#define POSITIVE_GAMMA_CORRECT 0xE0
#define NEGATIVE_GAMMA_CORRECT 0xE1
#define DIGITAL_GAMMA_CTL1 0xE2
#define DIGITAL_GAMMA_CTL2 0xE3
#define INTERFACE_CTL 0xF6
#define INVERSION_DISPALY_ON 0x21
#define GAMMA_SET 0x26
#define DISPALY_OFF 0x28
#define DISPALY_ON 0x29
#define HORIZONTAL_ADDRESS_SET 0x2A
#define VERTICAL_ADDRESS_SET 0x2B
#define MEMORY_WRITE 0x2C
#define COLOR_SET 0x2D
#define MEMORY_READ 0x2E
#define PARTIAL_AREA 0x30
#define VERTICAL_SCROL_DEFINE 0x33
#define TEAR_EFFECT_LINE_OFF 0x34
#define TEAR_EFFECT_LINE_ON 0x35
#define MEMORY_ACCESS_CTL 0x36
#define VERTICAL_SCROL_S_ADD 0x37
#define IDLE_MODE_OFF 0x38
#define IDLE_MODE_ON 0x39
#define PIXEL_FORMAT_SET 0x3A
#define WRITE_MEMORY_CONTINUE 0x3C
#define READ_MEMORY_CONTINUE 0x3E
#define SET_TEAR_SCANLINE 0x44
#define GET_SCANLINE 0x45
#define WRITE_BRIGHTNESS 0x51
#define READ_BRIGHTNESS 0x52
#define WRITE_CTRL_DISPALY 0x53
#define READ_CTRL_DISPALY 0x54
#define WRITE_BRIGHTNESS_CTL 0x55
#define READ_BRIGHTNESS_CTL 0x56
#define WRITE_MIN_BRIGHTNESS 0x5E
#define READ_MIN_BRIGHTNESS 0x5F
#define READ_ID1 0xDA
#define READ_ID2 0xDB
#define READ_ID3 0xDC
#define RGB_IF_SIGNAL_CTL 0xB0
#define NORMAL_FRAME_CTL 0xB1
#define IDLE_FRAME_CTL 0xB2
#define PARTIAL_FRAME_CTL 0xB3
#define INVERSION_CTL 0xB4
#define BLANK_PORCH_CTL 0xB5
#define DISPALY_FUNCTION_CTL 0xB6
#define ENTRY_MODE_SET 0xB7
#define BACKLIGHT_CTL1 0xB8
#define BACKLIGHT_CTL2 0xB9
#define BACKLIGHT_CTL3 0xBA
#define BACKLIGHT_CTL4 0xBB
#define BACKLIGHT_CTL5 0xBC
#define BACKLIGHT_CTL7 0xBE
#define BACKLIGHT_CTL8 0xBF
#define POWER_CTL1 0xC0
#define POWER_CTL2 0xC1
#define VCOM_CTL1 0xC5
#define VCOM_CTL2 0xC7
#define NV_MEMORY_WRITE 0xD0
#define NV_MEMORY_PROTECT_KEY 0xD1
#define NV_MEMORY_STATUS_READ 0xD2
#define READ_ID4 0xD3
#define POSITIVE_GAMMA_CORRECT 0xE0
#define NEGATIVE_GAMMA_CORRECT 0xE1
#define DIGITAL_GAMMA_CTL1 0xE2
#define DIGITAL_GAMMA_CTL2 0xE3
#define INTERFACE_CTL 0xF6
typedef enum _lcd_dir
{
@ -132,10 +132,10 @@ typedef enum _lcd_dir
DIR_MASK = 0xE0,
} lcd_dir_t;
#define LCD_SPI_CHANNEL SPI_DEVICE_0
#define LCD_SPI_CHANNEL SPI_DEVICE_0
#define LCD_SPI_CHIP_SELECT SPI_CHIP_SELECT_0
typedef struct lcd_8080_device
typedef struct Lcd8080Device
{
struct LcdBus lcd_bus;
struct DeviceLcdInfo lcd_info;
@ -143,11 +143,11 @@ typedef struct lcd_8080_device
int cs;
int dc_pin;
int dma_channel;
} * lcd_8080_device_t;
} * Lcd8080DeviceType;
lcd_8080_device_t lcd ;
Lcd8080DeviceType lcd ;
static void drv_lcd_cmd(uint8 cmd)
static void DrvLcdCmd(uint8 cmd)
{
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_LOW);
spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 8, 0);
@ -156,7 +156,7 @@ static void drv_lcd_cmd(uint8 cmd)
spi_send_data_normal_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, &cmd, 1, SPI_TRANS_CHAR);
}
static void drv_lcd_data_byte(uint8 *data_buf, uint32 length)
static void DrvLcdDataByte(uint8 *data_buf, uint32 length)
{
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH);
spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 8, 0);
@ -165,7 +165,7 @@ static void drv_lcd_data_byte(uint8 *data_buf, uint32 length)
spi_send_data_normal_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, data_buf, length, SPI_TRANS_CHAR);
}
static void drv_lcd_data_half_word(uint16 *data_buf, uint32 length)
static void DrvLcdDataHalfWord(uint16 *data_buf, uint32 length)
{
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH);
spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 16, 0);
@ -174,7 +174,7 @@ static void drv_lcd_data_half_word(uint16 *data_buf, uint32 length)
spi_send_data_normal_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, data_buf, length, SPI_TRANS_SHORT);
}
static void drv_lcd_data_word(uint32 *data_buf, uint32 length)
static void DrvLcdDataWord(uint32 *data_buf, uint32 length)
{
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH);
/*spi num Polarity and phase mode Multi-line mode Data bit width little endian */
@ -187,7 +187,7 @@ static void drv_lcd_data_word(uint32 *data_buf, uint32 length)
spi_send_data_normal_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, data_buf, length, SPI_TRANS_INT);
}
static void drv_lcd_hw_init(lcd_8080_device_t lcd)
static void DrvLcdHwInit(Lcd8080DeviceType lcd)
{
gpiohs_set_drive_mode(lcd->dc_pin, GPIO_DM_OUTPUT);
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH);
@ -195,27 +195,24 @@ static void drv_lcd_hw_init(lcd_8080_device_t lcd)
spi_set_clk_rate(lcd->spi_channel, 25000000);
}
static void drv_lcd_set_direction(lcd_dir_t dir)
static void DrvLcdSetDirection(lcd_dir_t dir)
{
#if !BOARD_LICHEEDAN
dir |= 0x08;
#endif
if (dir & DIR_XY_MASK)
{
lcd->lcd_info.width = 320;
lcd->lcd_info.height = 240;
}
else
{
lcd->lcd_info.width = 240;
lcd->lcd_info.height = 320;
if (dir & DIR_XY_MASK) {
lcd->lcd_info.width = 320;
lcd->lcd_info.height = 240;
} else {
lcd->lcd_info.width = 240;
lcd->lcd_info.height = 320;
}
drv_lcd_cmd(MEMORY_ACCESS_CTL);
drv_lcd_data_byte((uint8 *)&dir, 1);
DrvLcdCmd(MEMORY_ACCESS_CTL);
DrvLcdDataByte((uint8 *)&dir, 1);
}
static void drv_lcd_set_area(uint16 x1, uint16 y1, uint16 x2, uint16 y2)
static void DrvLcdSetArea(uint16 x1, uint16 y1, uint16 x2, uint16 y2)
{
uint8 data[4] = {0};
@ -223,23 +220,23 @@ static void drv_lcd_set_area(uint16 x1, uint16 y1, uint16 x2, uint16 y2)
data[1] = (uint8)(x1);
data[2] = (uint8)(x2 >> 8);
data[3] = (uint8)(x2);
drv_lcd_cmd(HORIZONTAL_ADDRESS_SET);
drv_lcd_data_byte(data, 4);
DrvLcdCmd(HORIZONTAL_ADDRESS_SET);
DrvLcdDataByte(data, 4);
data[0] = (uint8)(y1 >> 8);
data[1] = (uint8)(y1);
data[2] = (uint8)(y2 >> 8);
data[3] = (uint8)(y2);
drv_lcd_cmd(VERTICAL_ADDRESS_SET);
drv_lcd_data_byte(data, 4);
DrvLcdCmd(VERTICAL_ADDRESS_SET);
DrvLcdDataByte(data, 4);
drv_lcd_cmd(MEMORY_WRITE);
DrvLcdCmd(MEMORY_WRITE);
}
static void drv_lcd_set_pixel(uint16_t x, uint16_t y, uint16_t color)
static void DrvLcdSetPixel(uint16_t x, uint16_t y, uint16_t color)
{
drv_lcd_set_area(x, y, x, y);
drv_lcd_data_half_word(&color, 1);
DrvLcdSetArea(x, y, x, y);
DrvLcdDataHalfWord(&color, 1);
}
void LcdShowChar(uint16 x,uint16 y,uint8 num,uint8 size,uint16 color,uint16 back_color)
@ -248,31 +245,33 @@ void LcdShowChar(uint16 x,uint16 y,uint8 num,uint8 size,uint16 color,uint16 back
uint16 y0=y;
uint8 csize=(size/8+((size%8)?1:0))*(size/2);
num=num-' ';
for(t=0;t<csize;t++)
{
if(size==12)temp=asc2_1206[num][t]; //1206
else if(size==16)temp=asc2_1608[num][t]; //1608
else if(size==24)temp=asc2_2412[num][t]; //2412
else if(size==32)temp=asc2_3216[num][t]; //3216
else return;
for(t1=0;t1<8;t1++)
{
if(temp&0x80)
drv_lcd_set_pixel(x,y,color);
for (t = 0;t < csize;t ++) {
if (size==12)
temp=asc2_1206[num][t]; //1206
else if (size==16)
temp=asc2_1608[num][t]; //1608
else if (size==24)
temp=asc2_2412[num][t]; //2412
else if (size==32)
temp=asc2_3216[num][t]; //3216
else
return;
for(t1 = 0;t1 < 8;t1 ++) {
if (temp&0x80)
DrvLcdSetPixel(x,y,color);
else
{
drv_lcd_set_pixel(x,y,back_color);
}
DrvLcdSetPixel(x,y,back_color);
temp<<=1;
y++;
if(y>=lcd->lcd_info.height)return;
if((y-y0)==size)
{
if(y>=lcd->lcd_info.height)
return;
if ((y-y0) == size) {
y=y0;
x++;
if(x>=lcd->lcd_info.width)return;
if(x>=lcd->lcd_info.width)
return;
break;
}
}
@ -281,15 +280,18 @@ void LcdShowChar(uint16 x,uint16 y,uint8 num,uint8 size,uint16 color,uint16 back
void LcdShowString(uint16_t x,uint16_t y,uint16_t width,uint16_t height,uint8 size,uint8 *p,uint16_t color,uint16_t back_color)
{
uint16_t x0=x;
width+=x;
height+=y;
while((*p<='~')&&(*p>=' '))
{
if(x>=width){x=x0;y+=size;}
if(y>=height)break;
uint16_t x0 = x;
width += x;
height += y;
while ((*p<='~')&&(*p>=' ')) {
if (x>=width) {
x=x0;
y+=size;
}
if(y>=height)
break;
LcdShowChar(x,y,*p,size,color,back_color);
x+=size/2;
x += size/2;
p++;
}
}
@ -299,11 +301,11 @@ void LcdShowString(uint16_t x,uint16_t y,uint16_t width,uint16_t height,uint8 si
* para color
* return none
*/
void drv_lcd_clear(uint16 color)
void DrvLcdClear(uint16 color)
{
uint32 data = ((uint32)color << 16) | (uint32)color;
drv_lcd_set_area(0, 0, lcd->lcd_info.width - 1, lcd->lcd_info.height - 1);
DrvLcdSetArea(0, 0, lcd->lcd_info.width - 1, lcd->lcd_info.height - 1);
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH);
spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 32, 0);
spi_init_non_standard(lcd->spi_channel,
@ -314,69 +316,63 @@ void drv_lcd_clear(uint16 color)
spi_fill_data_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, (const uint32_t *)&data, lcd->lcd_info.width * lcd->lcd_info.height / 2);
}
static void drv_lcd_rect_update(uint16_t x1, uint16_t y1, uint16_t width, uint16_t height)
static void DrvLcdRectUpdate(uint16_t x1, uint16_t y1, uint16_t width, uint16_t height)
{
static uint16 * rect_buffer = NONE;
if(!rect_buffer)
{
if (!rect_buffer) {
rect_buffer = x_malloc(lcd->lcd_info.height * lcd->lcd_info.width * (lcd->lcd_info.bits_per_pixel / 8));
if(!rect_buffer)
{
if (!rect_buffer) {
return;
}
}
if(x1 == 0 && y1 == 0 && width == lcd->lcd_info.width && height == lcd->lcd_info.height)
{
drv_lcd_set_area(x1, y1, x1 + width - 1, y1 + height - 1);
drv_lcd_data_word((uint32 *)lcd->lcd_info.framebuffer, width * height / (lcd->lcd_info.bits_per_pixel / 8));
}
else
{
drv_lcd_set_area(x1, y1, x1 + width - 1, y1 + height - 1);
drv_lcd_data_word((uint32 *)rect_buffer, width * height / 2);
if (x1 == 0 && y1 == 0 && width == lcd->lcd_info.width && height == lcd->lcd_info.height) {
DrvLcdSetArea(x1, y1, x1 + width - 1, y1 + height - 1);
DrvLcdDataWord((uint32 *)lcd->lcd_info.framebuffer, width * height / (lcd->lcd_info.bits_per_pixel / 8));
} else {
DrvLcdSetArea(x1, y1, x1 + width - 1, y1 + height - 1);
DrvLcdDataWord((uint32 *)rect_buffer, width * height / 2);
}
}
x_err_t drv_lcd_init(lcd_8080_device_t dev)
x_err_t DrvLcdInit(Lcd8080DeviceType dev)
{
x_err_t ret = EOK;
lcd = (lcd_8080_device_t)dev;
lcd = (Lcd8080DeviceType)dev;
uint8 data = 0;
if(!lcd)
{
if (!lcd) {
return ERROR;
}
drv_lcd_hw_init(lcd);
DrvLcdHwInit(lcd);
/* reset LCD */
drv_lcd_cmd(SOFTWARE_RESET);
DrvLcdCmd(SOFTWARE_RESET);
MdelayKTask(100);
/* Enter normal status */
drv_lcd_cmd(SLEEP_OFF);
DrvLcdCmd(SLEEP_OFF);
MdelayKTask(100);
/* pixel format rgb565 */
drv_lcd_cmd(PIXEL_FORMAT_SET);
DrvLcdCmd(PIXEL_FORMAT_SET);
data = 0x55;
drv_lcd_data_byte(&data, 1);
DrvLcdDataByte(&data, 1);
/* set direction */
drv_lcd_set_direction(DIR_YX_RLUD);
DrvLcdSetDirection(DIR_YX_RLUD);
lcd->lcd_info.framebuffer = x_malloc(lcd->lcd_info.height * lcd->lcd_info.width * (lcd->lcd_info.bits_per_pixel / 8));
CHECK(lcd->lcd_info.framebuffer);
/*display on*/
drv_lcd_cmd(DISPALY_ON);
DrvLcdCmd(DISPALY_ON);
return ret;
}
static x_err_t drv_lcd_control(lcd_8080_device_t dev, int cmd, void *args)
static x_err_t drv_lcd_control(Lcd8080DeviceType dev, int cmd, void *args)
{
x_err_t ret = EOK;
lcd_8080_device_t lcd = (lcd_8080_device_t)dev;
Lcd8080DeviceType lcd = (Lcd8080DeviceType)dev;
x_base level;
struct DeviceRectInfo* rect_info = (struct DeviceRectInfo*)args;
@ -384,38 +380,38 @@ static x_err_t drv_lcd_control(lcd_8080_device_t dev, int cmd, void *args)
switch (cmd)
{
case GRAPHIC_CTRL_RECT_UPDATE:
if(!rect_info)
{
SYS_ERR("GRAPHIC_CTRL_RECT_UPDATE error args");
return -ERROR;
}
drv_lcd_rect_update(rect_info->x, rect_info->y, rect_info->width, rect_info->height);
break;
case GRAPHIC_CTRL_RECT_UPDATE:
if(!rect_info)
{
SYS_ERR("GRAPHIC_CTRL_RECT_UPDATE error args");
return -ERROR;
}
DrvLcdRectUpdate(rect_info->x, rect_info->y, rect_info->width, rect_info->height);
break;
case GRAPHIC_CTRL_POWERON:
/* Todo: power on */
ret = -ENONESYS;
break;
case GRAPHIC_CTRL_POWERON:
/* Todo: power on */
ret = -ENONESYS;
break;
case GRAPHIC_CTRL_POWEROFF:
/* Todo: power off */
ret = -ENONESYS;
break;
case GRAPHIC_CTRL_POWEROFF:
/* Todo: power off */
ret = -ENONESYS;
break;
case GRAPHIC_CTRL_GET_INFO:
*(struct DeviceLcdInfo *)args = lcd->lcd_info;
break;
case GRAPHIC_CTRL_GET_INFO:
*(struct DeviceLcdInfo *)args = lcd->lcd_info;
break;
case GRAPHIC_CTRL_SET_MODE:
ret = -ENONESYS;
break;
case GRAPHIC_CTRL_GET_EXT:
ret = -ENONESYS;
break;
default:
SYS_ERR("drv_lcd_control cmd: %d", cmd);
break;
case GRAPHIC_CTRL_SET_MODE:
ret = -ENONESYS;
break;
case GRAPHIC_CTRL_GET_EXT:
ret = -ENONESYS;
break;
default:
SYS_ERR("drv_lcd_control cmd: %d", cmd);
break;
}
return ret;
@ -424,7 +420,7 @@ static x_err_t drv_lcd_control(lcd_8080_device_t dev, int cmd, void *args)
void ClearHandwriting (void)
{
//clear the lcd
drv_lcd_clear(WHITE);
DrvLcdClear(WHITE);
LcdShowString(10, 10, 100, 24, 24, "RST ", RED, WHITE);
}
@ -433,7 +429,7 @@ void ClearHandwriting (void)
void HandTest(unsigned short *x_pos, unsigned short *y_pos)
{
float x1,y1;
TP_Read_XY(x_pos,y_pos); //address
TpReadXy(x_pos,y_pos); //address
float a = 12.1875,b = 16.25;
x1 = 320 - (*x_pos)/a +10;
y1 = (* y_pos)/b;
@ -441,23 +437,23 @@ void HandTest(unsigned short *x_pos, unsigned short *y_pos)
if ((*x_pos> 500)&&(*y_pos<500)) {
ClearHandwriting();
} else {
drv_lcd_set_pixel(x1, y1, RED);
drv_lcd_set_pixel(x1+1, y1, RED);
drv_lcd_set_pixel(x1-1, y1, RED);
DrvLcdSetPixel(x1, y1, RED);
DrvLcdSetPixel(x1+1, y1, RED);
DrvLcdSetPixel(x1-1, y1, RED);
drv_lcd_set_pixel(x1, y1+1, RED);
drv_lcd_set_pixel(x1, y1-1, RED);
DrvLcdSetPixel(x1, y1+1, RED);
DrvLcdSetPixel(x1, y1-1, RED);
drv_lcd_set_pixel(x1+1, y1+1, RED);
drv_lcd_set_pixel(x1-1, y1-1, RED);
DrvLcdSetPixel(x1+1, y1+1, RED);
DrvLcdSetPixel(x1-1, y1-1, RED);
drv_lcd_set_pixel(x1+1, y1-1, RED);
drv_lcd_set_pixel(x1-1, y1+1, RED);
DrvLcdSetPixel(x1+1, y1-1, RED);
DrvLcdSetPixel(x1-1, y1+1, RED);
}
}
#endif
static uint32 Lcd_Write(void *dev, struct BusBlockWriteParam *write_param)
static uint32 LcdWrite(void *dev, struct BusBlockWriteParam *write_param)
{
if (write_param == NONE) {
return ERROR;
@ -469,26 +465,26 @@ static uint32 Lcd_Write(void *dev, struct BusBlockWriteParam *write_param)
LcdShowString(show->x_pos,show->y_pos,show->width,show->height,show->font_size,show->addr,show->font_color,show->back_color);
return EOK;
} else if (1==write_param->pos) { //output dot
drv_lcd_set_pixel(show->x_pos, show->y_pos, show->font_color);
DrvLcdSetPixel(show->x_pos, show->y_pos, show->font_color);
return EOK;
} else {
return ERROR;
}
}
uint32 drv_lcd_clear_done(void * dev, struct BusConfigureInfo *configure_info)
uint32 DrvLcdClearDone(void * dev, struct BusConfigureInfo *configure_info)
{
uint16 color = 0;
color =(uint16)(configure_info->configure_cmd |0x0000ffff );
drv_lcd_clear( color);
return 0;
uint16 color = 0;
color =(uint16)(configure_info->configure_cmd |0x0000ffff );
DrvLcdClear( color);
return 0;
}
const struct LcdDevDone lcd_dev_done =
{
.open = NONE,
.close = NONE,
.write = Lcd_Write,
.write = LcdWrite,
.read = NONE
};
@ -503,7 +499,7 @@ static int BoardLcdBusInit(struct LcdBus * lcd_bus, struct LcdDriver * lcd_drive
return ERROR;
}
lcd_driver->configure = drv_lcd_clear_done;
lcd_driver->configure = DrvLcdClearDone;
/*Init the lcd driver*/
ret = LcdDriverInit( lcd_driver, LCD_DRV_NAME_1);
if (EOK != ret) {
@ -553,10 +549,10 @@ int HwLcdInit(void)
static struct LcdDriver lcd_driver;
memset(&lcd_driver, 0, sizeof(struct LcdDriver));
lcd_8080_device_t lcd_dev = (lcd_8080_device_t )malloc(sizeof( struct lcd_8080_device));
memset(lcd_dev, 0, sizeof(struct lcd_8080_device));
Lcd8080DeviceType lcd_dev = (Lcd8080DeviceType )malloc(sizeof( struct Lcd8080Device));
memset(lcd_dev, 0, sizeof(struct Lcd8080Device));
if (!lcd_dev){
if (!lcd_dev) {
return -1;
}
@ -591,81 +587,91 @@ int HwLcdInit(void)
gpiohs_set_drive_mode(10, GPIO_DM_OUTPUT);
gpiohs_set_pin(10, GPIO_PV_HIGH);
KPrintf("LCD driver inited ...\r\n");
drv_lcd_init(lcd_dev);
DrvLcdInit(lcd_dev);
return ret;
}
//x1,y1:start
//x2,y2:end
void LCD_DrawLine(uint16 x1, uint16 y1, uint16 x2, uint16 y2,uint16 color)
void LcdDrawLine(uint16 x1, uint16 y1, uint16 x2, uint16 y2,uint16 color)
{
uint16 t;
int xerr=0,yerr=0,delta_x,delta_y,distance;
int xerr = 0, yerr = 0, delta_x, delta_y, distance;
int incx,incy,uRow,uCol;
delta_x=x2-x1;
delta_y=y2-y1;
uRow=x1;
uCol=y1;
delta_x = x2 - x1;
delta_y = y2 - y1;
uRow = x1;
uCol = y1;
if(delta_x>0)incx=1;
else if(delta_x==0)incx=0;
else {incx=-1;delta_x=-delta_x;}
if(delta_x>0)
incx = 1;
else if(delta_x==0)
incx = 0;
else {
incx = -1;
delta_x = -delta_x;
}
if(delta_y>0)incy=1;
else if(delta_y==0)incy=0;
else{incy=-1;delta_y=-delta_y;}
if(delta_y>0)
incy = 1;
else if(delta_y==0)
incy = 0;
else {
incy= -1;
delta_y = -delta_y;
}
if( delta_x>delta_y)distance=delta_x;
else distance=delta_y;
if (delta_x>delta_y)
distance=delta_x;
else
distance=delta_y;
for(t=0;t<=distance+1;t++ )
{
drv_lcd_set_pixel(uRow,uCol,color);
xerr+=delta_x ;
yerr+=delta_y ;
if(xerr>distance)
{
for(t = 0;t <= distance+1;t ++ ) {
DrvLcdSetPixel(uRow,uCol,color);
xerr += delta_x ;
yerr += delta_y ;
if (xerr>distance) {
xerr-=distance;
uRow+=incx;
}
if(yerr>distance)
{
if (yerr>distance) {
yerr-=distance;
uCol+=incy;
}
}
}
void LCD_DrawRectangle(uint16 x1, uint16 y1, uint16 x2, uint16 y2,uint16 color)
void LcdDrawRectangle(uint16 x1, uint16 y1, uint16 x2, uint16 y2,uint16 color)
{
LCD_DrawLine(x1,y1,x2,y1,color);
LCD_DrawLine(x1,y1,x1,y2,color);
LCD_DrawLine(x1,y2,x2,y2,color);
LCD_DrawLine(x2,y1,x2,y2,color);
LcdDrawLine(x1,y1,x2,y1,color);
LcdDrawLine(x1,y1,x1,y2,color);
LcdDrawLine(x1,y2,x2,y2,color);
LcdDrawLine(x2,y1,x2,y2,color);
}
void LCD_Draw_Circle(uint16 x0,uint16 y0,uint8 r,uint16 color)
void LcdDrawCircle(uint16 x0,uint16 y0,uint8 r,uint16 color)
{
int a,b;
int di;
a=0;b=r;
di=3-(r<<1);
while(a<=b)
{
drv_lcd_set_pixel(x0+a,y0-b,color); //5
drv_lcd_set_pixel(x0+b,y0-a,color); //0
drv_lcd_set_pixel(x0+b,y0+a,color); //4
drv_lcd_set_pixel(x0+a,y0+b,color); //6
drv_lcd_set_pixel(x0-a,y0+b,color); //1
drv_lcd_set_pixel(x0-b,y0+a,color);
drv_lcd_set_pixel(x0-a,y0-b,color); //2
drv_lcd_set_pixel(x0-b,y0-a,color); //7
a = 0;
b = r;
di = 3-(r<<1);
while(a <= b) {
DrvLcdSetPixel(x0+a,y0-b,color); //5
DrvLcdSetPixel(x0+b,y0-a,color); //0
DrvLcdSetPixel(x0+b,y0+a,color); //4
DrvLcdSetPixel(x0+a,y0+b,color); //6
DrvLcdSetPixel(x0-a,y0+b,color); //1
DrvLcdSetPixel(x0-b,y0+a,color);
DrvLcdSetPixel(x0-a,y0-b,color); //2
DrvLcdSetPixel(x0-b,y0-a,color); //7
a++;
//Bresenham
if(di<0)di +=4*a+6;
else
{
di+=10+4*(a-b);
if(di<0)
di += 4*a+6;
else {
di += 10+4*(a-b);
b--;
}
}

2
board/aiit-riscv64-board/third_party_driver/rtc/connect_rtc.c
View File

@ -83,7 +83,7 @@ static uint32 RtcConfigure(void *drv, struct BusConfigureInfo *configure_info)
rtc_timer_set_clock_count_value(1);
rtc_timer_set_mode(RTC_TIMER_RUNNING);
if(rtc_timer_set(tm_new.tm_year+1900,tm_new.tm_mon+1,tm_new.tm_mday,
if (rtc_timer_set(tm_new.tm_year+1900,tm_new.tm_mon+1,tm_new.tm_mday,
tm_new.tm_hour,tm_new.tm_min,tm_new.tm_sec)==-1)
return ERROR;
}

4
board/aiit-riscv64-board/third_party_driver/timer/connect_hwtimer.c
View File

@ -31,8 +31,8 @@ static struct HwtimerCallBackInfo *ptim2_cb_info = NULL;
int timer_callback(void *ctx)
{
if (ptim2_cb_info) {
if (ptim2_cb_info->TimeoutCb) {
ptim2_cb_info->TimeoutCb(ptim2_cb_info->param);
if (ptim2_cb_info->timeout_callback) {
ptim2_cb_info->timeout_callback(ptim2_cb_info->param);
}
}
return 0;

42
board/aiit-riscv64-board/third_party_driver/touch/connect_touch.c
View File

@ -32,8 +32,8 @@ touch_device_info tp_dev =
0,
};
unsigned char CMD_RDX=0XD0;
unsigned char CMD_RDY=0X90;
unsigned char CMD_RDX = 0XD0;
unsigned char CMD_RDY = 0X90;
TP_modify_save modify_save =
{
@ -56,7 +56,7 @@ void TouchWriteByte(unsigned char num)
}
}
unsigned short TP_Read_AD(unsigned char CMD)
unsigned short TpReadAd(unsigned char CMD)
{
unsigned char count=0;
unsigned short Num=0;
@ -87,13 +87,15 @@ unsigned short TP_Read_AD(unsigned char CMD)
#define READ_TIMES 5
#define LOST_VAL 1
unsigned short TP_Read_XOY(unsigned char xy)
unsigned short TpReadXoy(unsigned char xy)
{
unsigned short i, j;
unsigned short buf[READ_TIMES];
unsigned short sum=0;
unsigned short temp;
for (i=0;i<READ_TIMES;i++)buf[i]=TP_Read_AD(xy);
for (i=0;i<READ_TIMES;i++)
buf[i]=TpReadAd(xy);
for (i=0;i<READ_TIMES-1; i++) {
for (j=i+1;j<READ_TIMES;j++) {
if (buf[i]>buf[j]) {
@ -104,16 +106,17 @@ unsigned short TP_Read_XOY(unsigned char xy)
}
}
sum=0;
for(i=LOST_VAL;i<READ_TIMES-LOST_VAL;i++)sum+=buf[i];
for(i=LOST_VAL;i<READ_TIMES-LOST_VAL;i++)
sum+=buf[i];
temp=sum/(READ_TIMES-2*LOST_VAL);
return temp;
}
unsigned char TP_Read_XY(unsigned short *x, unsigned short *y)
unsigned char TpReadXy(unsigned short *x, unsigned short *y)
{
unsigned short xtemp,ytemp;
xtemp=TP_Read_XOY(CMD_RDX);
ytemp=TP_Read_XOY(CMD_RDY);
xtemp=TpReadXoy(CMD_RDX);
ytemp=TpReadXoy(CMD_RDY);
*x=xtemp;
*y=ytemp;
@ -122,10 +125,10 @@ unsigned char TP_Read_XY(unsigned short *x, unsigned short *y)
uint32 TouchRead(void *dev, struct BusBlockReadParam *read_param)
{
uint32 ret = EOK;
uint32 ret = EOK;
NULL_PARAM_CHECK(read_param);
struct TouchDataStandard * data = ( struct TouchDataStandard*)read_param->buffer;
TP_Read_XY(&data->x,&data->y);
struct TouchDataStandard *data = ( struct TouchDataStandard*)read_param->buffer;
TpReadXy(&data->x,&data->y);
return ret;
}
@ -138,10 +141,10 @@ unsigned char TP_Read_XY_TWICE(unsigned short *x, unsigned short *y)
{
unsigned short fir_x, fir_y, sec_x, sec_y;
unsigned char flag;
flag = TP_Read_XY(&fir_x, &fir_y);
flag = TpReadXy(&fir_x, &fir_y);
if (flag == 0)
return(0);
flag = TP_Read_XY(&sec_x, &sec_y);
flag = TpReadXy(&sec_x, &sec_y);
if (flag == 0)
return(0);
if (((sec_x <= fir_x && fir_x < sec_x + band_error) || (fir_x <= sec_x && sec_x < fir_x + band_error))
@ -182,9 +185,8 @@ struct TouchDevDone touch_dev_done =
void TP_Init(void)
{
TouchConfigure(NONE,NONE);
while (1)
{
TP_Read_XY(&tp_dev.x, &tp_dev.y);
while (1) {
TpReadXy(&tp_dev.x, &tp_dev.y);
KPrintf("tp_dev.x = %8d *** tp_dev.y= %8d \r\n", tp_dev.x, tp_dev.y);
MdelayKTask(100);
}
@ -201,7 +203,7 @@ unsigned short my_abs(unsigned short x1, unsigned short x2)
struct RiscTouch
{
char *BusName;
struct TouchBus touchbus;
struct TouchBus touch_bus;
};
struct RiscTouch touch;
@ -211,7 +213,7 @@ static int BoardTouchBusInit(struct RiscTouch *risc_touch_bus, struct TouchDrive
x_err_t ret = EOK;
/*Init the touch bus */
ret = TouchBusInit(&risc_touch_bus->touchbus, risc_touch_bus->BusName);
ret = TouchBusInit(&risc_touch_bus->touch_bus, risc_touch_bus->BusName);
if (EOK != ret) {
KPrintf("Board_touch_init touchBusInit error %d\n", ret);
return ERROR;
@ -270,7 +272,7 @@ int HwTouchBusInit(void)
risc_touch = &touch;
risc_touch->BusName = TOUCH_BUS_NAME_1;
risc_touch->touchbus.private_data = &touch;
risc_touch->touch_bus.private_data = &touch;
TouchConfigure(NONE,NONE);

63
board/hifive1-emulator/third_party_driver/connect_usart.c
View File

@ -32,38 +32,31 @@ static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struc
struct SerialDataCfg *data_cfg_default = &serial_cfg_default->data_cfg;
struct SerialDataCfg *data_cfg_new = &serial_cfg_new->data_cfg;
if((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate))
{
if ((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) {
data_cfg_default->serial_baud_rate = data_cfg_new->serial_baud_rate;
}
if((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order))
{
if ((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order)) {
data_cfg_default->serial_bit_order = data_cfg_new->serial_bit_order;
}
if((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size))
{
if ((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)) {
data_cfg_default->serial_buffer_size = data_cfg_new->serial_buffer_size;
}
if((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits))
{
if ((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits)) {
data_cfg_default->serial_data_bits = data_cfg_new->serial_data_bits;
}
if((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode))
{
if ((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode)) {
data_cfg_default->serial_invert_mode = data_cfg_new->serial_invert_mode;
}
if((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode))
{
if ((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)) {
data_cfg_default->serial_parity_mode = data_cfg_new->serial_parity_mode;
}
if((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits))
{
if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
}
}
@ -81,8 +74,7 @@ static uint32 SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInf
NULL_PARAM_CHECK(serial_drv);
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
if(configure_info->private_data)
{
if (configure_info->private_data) {
struct SerialCfgParam *serial_cfg_new = (struct SerialCfgParam *)configure_info->private_data;
SerialCfgParamCheck(serial_cfg, serial_cfg_new);
}
@ -116,15 +108,15 @@ static uint32 SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_i
switch (configure_info->configure_cmd)
{
case OPE_INT:
ret = SerialInit(serial_drv, configure_info);
break;
case OPE_CFG:
serial_operation_cmd = *(int *)configure_info->private_data;
ret = SerialConfigure(serial_drv, serial_operation_cmd);
break;
default:
break;
case OPE_INT:
ret = SerialInit(serial_drv, configure_info);
break;
case OPE_CFG:
serial_operation_cmd = *(int *)configure_info->private_data;
ret = SerialConfigure(serial_drv, serial_operation_cmd);
break;
default:
break;
}
return ret;
@ -178,24 +170,21 @@ static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver
/*Init the serial bus */
ret = SerialBusInit(serial_bus, bus_name);
if(EOK != ret)
{
if (EOK != ret) {
KPrintf("InitHwUart SerialBusInit error %d\n", ret);
return ERROR;
}
/*Init the serial driver*/
ret = SerialDriverInit(serial_driver, drv_name);
if(EOK != ret)
{
if (EOK != ret) {
KPrintf("InitHwUart SerialDriverInit error %d\n", ret);
return ERROR;
}
/*Attach the serial driver to the serial bus*/
ret = SerialDriverAttachToBus(drv_name, bus_name);
if(EOK != ret)
{
if (EOK != ret) {
KPrintf("InitHwUart SerialDriverAttachToBus error %d\n", ret);
return ERROR;
}
@ -209,15 +198,13 @@ static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *
x_err_t ret = EOK;
ret = SerialDeviceRegister(serial_device, serial_param, dev_name);
if(EOK != ret)
{
if (EOK != ret) {
KPrintf("InitHwUart SerialDeviceInit device %s error %d\n", dev_name, ret);
return ERROR;
}
ret = SerialDeviceAttachToBus(dev_name, bus_name);
if(EOK != ret)
{
if (EOK != ret) {
KPrintf("InitHwUart SerialDeviceAttachToBus device %s error %d\n", dev_name, ret);
return ERROR;
}
@ -258,15 +245,13 @@ int InitHwUart(void)
serial_device.haldev.private_data = (void *)&serial_dev_param;
ret = BoardSerialBusInit(&serial_bus, &serial_driver, SERIAL_BUS_NAME, SERIAL_DRV_NAME);
if(EOK != ret)
{
if (EOK != ret) {
KPrintf("InitHwUart uarths error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device, (void *)&serial_cfg, SERIAL_BUS_NAME, SERIAL_DEVICE_NAME);
if(EOK != ret)
{
if (EOK != ret) {
KPrintf("InitHwUart uarths error ret %u\n", ret);
return ERROR;
}

63
board/hifive1-rev-B/third_party_driver/connect_usart.c
View File

@ -32,38 +32,31 @@ static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struc
struct SerialDataCfg *data_cfg_default = &serial_cfg_default->data_cfg;
struct SerialDataCfg *data_cfg_new = &serial_cfg_new->data_cfg;
if((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate))
{
if ((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) {
data_cfg_default->serial_baud_rate = data_cfg_new->serial_baud_rate;
}
if((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order))
{
if ((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order)) {
data_cfg_default->serial_bit_order = data_cfg_new->serial_bit_order;
}
if((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size))
{
if ((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)) {
data_cfg_default->serial_buffer_size = data_cfg_new->serial_buffer_size;
}
if((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits))
{
if ((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits)) {
data_cfg_default->serial_data_bits = data_cfg_new->serial_data_bits;
}
if((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode))
{
if ((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode)) {
data_cfg_default->serial_invert_mode = data_cfg_new->serial_invert_mode;
}
if((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode))
{
if ((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)) {
data_cfg_default->serial_parity_mode = data_cfg_new->serial_parity_mode;
}
if((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits))
{
if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
}
}
@ -81,8 +74,7 @@ static uint32 SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInf
NULL_PARAM_CHECK(serial_drv);
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
if(configure_info->private_data)
{
if (configure_info->private_data) {
struct SerialCfgParam *serial_cfg_new = (struct SerialCfgParam *)configure_info->private_data;
SerialCfgParamCheck(serial_cfg, serial_cfg_new);
}
@ -116,15 +108,15 @@ static uint32 SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_i
switch (configure_info->configure_cmd)
{
case OPE_INT:
ret = SerialInit(serial_drv, configure_info);
break;
case OPE_CFG:
serial_operation_cmd = *(int *)configure_info->private_data;
ret = SerialConfigure(serial_drv, serial_operation_cmd);
break;
default:
break;
case OPE_INT:
ret = SerialInit(serial_drv, configure_info);
break;
case OPE_CFG:
serial_operation_cmd = *(int *)configure_info->private_data;
ret = SerialConfigure(serial_drv, serial_operation_cmd);
break;
default:
break;
}
return ret;
@ -178,24 +170,21 @@ static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver
/*Init the serial bus */
ret = SerialBusInit(serial_bus, bus_name);
if(EOK != ret)
{
if (EOK != ret) {
KPrintf("InitHwUart SerialBusInit error %d\n", ret);
return ERROR;
}
/*Init the serial driver*/
ret = SerialDriverInit(serial_driver, drv_name);
if(EOK != ret)
{
if (EOK != ret) {
KPrintf("InitHwUart SerialDriverInit error %d\n", ret);
return ERROR;
}
/*Attach the serial driver to the serial bus*/
ret = SerialDriverAttachToBus(drv_name, bus_name);
if(EOK != ret)
{
if (EOK != ret) {
KPrintf("InitHwUart SerialDriverAttachToBus error %d\n", ret);
return ERROR;
}
@ -209,15 +198,13 @@ static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *
x_err_t ret = EOK;
ret = SerialDeviceRegister(serial_device, serial_param, dev_name);
if(EOK != ret)
{
if (EOK != ret) {
KPrintf("InitHwUart SerialDeviceInit device %s error %d\n", dev_name, ret);
return ERROR;
}
ret = SerialDeviceAttachToBus(dev_name, bus_name);
if(EOK != ret)
{
if (EOK != ret) {
KPrintf("InitHwUart SerialDeviceAttachToBus device %s error %d\n", dev_name, ret);
return ERROR;
}
@ -258,15 +245,13 @@ int InitHwUart(void)
serial_device.haldev.private_data = (void *)&serial_dev_param;
ret = BoardSerialBusInit(&serial_bus, &serial_driver, SERIAL_BUS_NAME, SERIAL_DRV_NAME);
if(EOK != ret)
{
if (EOK != ret) {
KPrintf("InitHwUart uarths error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device, (void *)&serial_cfg, SERIAL_BUS_NAME, SERIAL_DEVICE_NAME);
if(EOK != ret)
{
if (EOK != ret) {
KPrintf("InitHwUart uarths error ret %u\n", ret);
return ERROR;
}

28
board/kd233/third_party_driver/i2c/connect_i2c.c
View File

@ -52,11 +52,11 @@ static I2cBusParam i2c_bus_param =
#define SET_SDA(done, val) done->SetSdaState(done->data, val)
#define SET_SCL(done, val) done->SetSclState(done->data, val)
#define GET_SDA(done) done->GetSdaState(done->data)
#define GET_SCL(done) done->GetSclState(done->data)
#define SdaLow(done) SET_SDA(done, 0)
#define SdaHigh(done) SET_SDA(done, 1)
#define SclLow(done) SET_SCL(done, 0)
#define GET_SDA(done) done->GetSdaState(done->data)
#define GET_SCL(done) done->GetSclState(done->data)
#define SdaLow(done) SET_SDA(done, 0)
#define SdaHigh(done) SET_SDA(done, 1)
#define SclLow(done) SET_SCL(done, 0)
void I2cGpioInit(const I2cBusParam *bus_param)
{
@ -124,8 +124,7 @@ static x_err_t I2cBusReset(const I2cBusParam *bus_param)
int32 i = 0;
gpio_set_drive_mode(bus_param->i2c_sda_pin, GPIO_DM_INPUT_PULL_UP );
if (GPIO_LOW == gpio_get_pin(bus_param->i2c_sda_pin)) {
while (i++ < 9)
{
while (i++ < 9) {
gpio_set_drive_mode(bus_param->i2c_scl_pin, GPIO_DM_OUTPUT );
gpio_set_pin(bus_param->i2c_scl_pin , GPIO_PV_HIGH );
usleep(100);
@ -160,8 +159,7 @@ static x_err_t SclHigh(struct I2cHalDrvDone *done)
goto done;
start = CurrentTicksGain();
while (!GET_SCL(done))
{
while (!GET_SCL(done)) {
if ((CurrentTicksGain() - start) > done->timeout)
return -ETIMEOUT;
DelayKTask((done->timeout + 1) >> 1);
@ -282,8 +280,7 @@ static x_size_t I2cSendBytes(struct I2cBus *bus, struct I2cDataStandard *msg)
int32 count = msg->len;
uint16 ignore_nack = msg->flags & I2C_IGNORE_NACK;
while (count > 0)
{
while (count > 0) {
ret = I2cWriteb(bus, *ptr);
if ((ret > 0) || (ignore_nack && (ret == 0))) {
@ -327,8 +324,7 @@ static x_size_t I2cRecvBytes(struct I2cBus *bus, struct I2cDataStandard *msg)
int32 count = msg->len;
const uint32 flags = msg->flags;
while (count > 0)
{
while (count > 0) {
val = I2cReadb(bus);
if (val >= 0) {
*ptr = val;
@ -427,8 +423,7 @@ static uint32 I2cWriteData(struct I2cHardwareDevice *i2c_dev, struct I2cDataStan
uint16 ignore_nack;
I2cStart(done);
while (NONE != msg)
{
while (NONE != msg) {
ignore_nack = msg->flags & I2C_IGNORE_NACK;
if (!(msg->flags & I2C_NO_START)) {
if (i) {
@ -471,8 +466,7 @@ static uint32 I2cReadData(struct I2cHardwareDevice *i2c_dev, struct I2cDataStand
uint16 ignore_nack;
I2cStart(done);
while (NONE != msg)
{
while (NONE != msg) {
ignore_nack = msg->flags & I2C_IGNORE_NACK;
if (!(msg->flags & I2C_NO_START)) {
if (i) {

4
board/kd233/third_party_driver/include/connect_uart.h
View File

@ -27,8 +27,8 @@
extern "C" {
#endif
#define KERNEL_CONSOLE_BUS_NAME SERIAL_BUS_NAME_0
#define KERNEL_CONSOLE_DRV_NAME SERIAL_DRV_NAME_0
#define KERNEL_CONSOLE_BUS_NAME SERIAL_BUS_NAME_0
#define KERNEL_CONSOLE_DRV_NAME SERIAL_DRV_NAME_0
#define KERNEL_CONSOLE_DEVICE_NAME SERIAL_0_DEVICE_NAME_0
int HwUartInit(void);

6
board/kd233/third_party_driver/spi/connect_spi.c
View File

@ -159,8 +159,7 @@ static uint32 SpiWriteData(struct SpiHardwareDevice *spi_dev, struct SpiDataStan
uint8 device_master_id = dev_param->spi_dma_param->spi_master_id;
uint8 cs_gpio_pin = dev_param->spi_slave_param->spi_cs_gpio_pin;
while (NONE != spi_datacfg)
{
while (NONE != spi_datacfg) {
uint32_t * tx_buff = NONE;
int i;
x_ubase dummy = 0xFFFFFFFFU;
@ -227,8 +226,7 @@ static uint32 SpiReadData(struct SpiHardwareDevice *spi_dev, struct SpiDataStand
uint8 device_master_id = dev_param->spi_dma_param->spi_master_id;
uint8 cs_gpio_pin = dev_param->spi_slave_param->spi_cs_gpio_pin;
while (NONE != spi_datacfg)
{
while (NONE != spi_datacfg) {
uint32_t * rx_buff = NONE;
int i;
x_ubase dummy = 0xFFFFFFFFU;

4
board/kd233/third_party_driver/timer/connect_hwtimer.c
View File

@ -32,8 +32,8 @@ static struct HwtimerCallBackInfo *ptim2_cb_info = NULL;
int timer_callback(void *ctx)
{
if (ptim2_cb_info) {
if (ptim2_cb_info->TimeoutCb) {
ptim2_cb_info->TimeoutCb(ptim2_cb_info->param);
if (ptim2_cb_info->timeout_callback) {
ptim2_cb_info->timeout_callback(ptim2_cb_info->param);
}
}
return 0;

61
board/stm32f407-st-discovery/third_party_driver/can/connect_can.c
View File

@ -30,19 +30,16 @@ Modification:
#include "misc.h"
#include "hardware_rcc.h"
#include "hardware_gpio.h"
#include <xiuos.h>
#include <device.h>
static struct CanSendConfigure can_send_deconfig =
static struct CanSendConfigure can_send_deconfig =
{
.stdid = 0x55,
.exdid = 0x00,
.ide = 0 ,
.rtr = 0,
.data_lenth = 8
.stdid = 0x55,
.exdid = 0x00,
.ide = 0 ,
.rtr = 0,
.data_lenth = 8
};
static void CanGPIOInit(void)
{
CAN_FilterInitTypeDef can1_filter;
@ -65,14 +62,14 @@ static void CanGPIOInit(void)
static void Can1NvicConfig(void)
{
NVIC_InitTypeDef can_nvic_config;
NVIC_InitTypeDef can_nvic_config;
can_nvic_config.NVIC_IRQChannel = CAN1_RX0_IRQn;
can_nvic_config.NVIC_IRQChannelPreemptionPriority = 2;
can_nvic_config.NVIC_IRQChannelSubPriority = 2;
can_nvic_config.NVIC_IRQChannelCmd = ENABLE;
CAN_ITConfig(CAN1, CAN_IT_FMP0, ENABLE);
NVIC_Init(&can_nvic_config);
can_nvic_config.NVIC_IRQChannel = CAN1_RX0_IRQn;
can_nvic_config.NVIC_IRQChannelPreemptionPriority = 2;
can_nvic_config.NVIC_IRQChannelSubPriority = 2;
can_nvic_config.NVIC_IRQChannelCmd = ENABLE;
CAN_ITConfig(CAN1, CAN_IT_FMP0, ENABLE);
NVIC_Init(&can_nvic_config);
}
static uint32 CanModeInit(void *drv, struct BusConfigureInfo *configure_info)
@ -131,18 +128,17 @@ static uint32 CanSendMsg(void * dev , struct BusBlockWriteParam *write_param )
tx_data.RTR = 0;
tx_data.DLC = write_param->size;
for(i = 0;i<tx_data.DLC;i++)
{
for(i = 0;i<tx_data.DLC;i++) {
tx_data.Data[i] = data[i];
}
mbox = CAN_Transmit(CAN1,&tx_data);
while(CAN_TransmitStatus(CAN1,mbox)== CAN_TxStatus_Failed &&timer_count){
timer_count--;
while (CAN_TransmitStatus(CAN1,mbox)== CAN_TxStatus_Failed &&timer_count) {
timer_count--;
}
if(timer_count<=0){
if (timer_count<=0) {
return ERROR;
}
return EOK;
@ -164,7 +160,6 @@ static uint32 CanRecvMsg(void *dev , struct BusBlockReadParam *databuf)
return msg.DLC;
}
static struct CanDevDone dev_done =
{
.open = NONE,
@ -173,7 +168,6 @@ static struct CanDevDone dev_done =
.read = CanRecvMsg
};
static struct CanHardwareDevice dev;
#ifdef CAN_USING_INTERRUPT
@ -194,20 +188,20 @@ static int BoardCanBusInit(struct Stm32Can *stm32can_bus, struct CanDriver *can_
/*Init the can bus */
ret = CanBusInit(&stm32can_bus->can_bus, stm32can_bus->bus_name);
if(EOK != ret){
if (EOK != ret) {
KPrintf("Board_can_init canBusInit error %d\n", ret);
return ERROR;
}
/*Init the can driver*/
ret = CanDriverInit(can_driver, CAN_DRIVER_NAME);
if(EOK != ret){
if (EOK != ret) {
KPrintf("Board_can_init canDriverInit error %d\n", ret);
return ERROR;
}
/*Attach the can driver to the can bus*/
ret = CanDriverAttachToBus(CAN_DRIVER_NAME, stm32can_bus->bus_name);
if(EOK != ret){
if (EOK != ret) {
KPrintf("Board_can_init CanDriverAttachToBus error %d\n", ret);
return ERROR;
}
@ -215,8 +209,6 @@ static int BoardCanBusInit(struct Stm32Can *stm32can_bus, struct CanDriver *can_
return ret;
}
static x_err_t HwCanDeviceAttach(const char *bus_name, const char *device_name)
{
NULL_PARAM_CHECK(bus_name);
@ -232,13 +224,13 @@ static x_err_t HwCanDeviceAttach(const char *bus_name, const char *device_name)
can_device->dev_done = &dev_done;
result = CanDeviceRegister(can_device, NONE, device_name);
if(EOK != result){
if (EOK != result) {
KPrintf("board_can_init canDeviceInit device %s error %d\n", "can1", result);
return ERROR;
}
result = CanDeviceAttachToBus(device_name, bus_name);
if (result != EOK){
if (result != EOK) {
SYS_ERR("%s attach to %s faild, %d\n", device_name, bus_name, result);
}
@ -249,7 +241,6 @@ static x_err_t HwCanDeviceAttach(const char *bus_name, const char *device_name)
return result;
}
struct Stm32Can can1;
int Stm32HwCanBusInit(void)
@ -270,15 +261,15 @@ struct Stm32Can can1;
ret = BoardCanBusInit(stm32_can_bus, &can_driver);
if(EOK != ret){
if (EOK != ret) {
KPrintf(" can_bus_init %s error ret %u\n", stm32_can_bus->bus_name, ret);
return ERROR;
}
ret = HwCanDeviceAttach(CAN_BUS_NAME_1,CAN_1_DEVICE_NAME_1);
if(EOK != ret){
ret = HwCanDeviceAttach(CAN_BUS_NAME_1,CAN_1_DEVICE_NAME_1);
if (EOK != ret) {
KPrintf(" HwCanDeviceAttach %s error ret %u\n", stm32_can_bus->bus_name, ret);
return ERROR;
}
return EOK;
}
}

65
board/stm32f407-st-discovery/third_party_driver/gpio/connect_gpio.c
View File

@ -570,7 +570,7 @@ static int32 GpioIrqRegister(int32 pin, int32 mode, void (*hdr)(void *args), voi
int32 irqindex = -1;
irqindex = Bit2Bitnum(index->pin);
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab)){
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab)) {
return -ENONESYS;
}
@ -603,7 +603,7 @@ static uint32 GpioIrqFree(int32 pin)
int32 irqindex = -1;
irqindex = Bit2Bitnum(index->pin);
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab)){
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab)) {
return -ENONESYS;
}
@ -634,7 +634,7 @@ static int32 GpioIrqEnable(x_base pin)
return -ENONESYS;
}
x_base level = CriticalAreaLock();
if (pin_irq_hdr_tab[irqindex].pin == -1){
if (pin_irq_hdr_tab[irqindex].pin == -1) {
CriticalAreaUnLock(level);
return -ENONESYS;
}
@ -721,11 +721,11 @@ static uint32 Stm32PinConfigure(struct PinParam *param)
static uint32 Stm32PinInit(void)
{
static x_bool PinInitFlag = RET_FALSE;
static x_bool pin_init_flag = RET_FALSE;
if(!PinInitFlag){
if (!pin_init_flag) {
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
PinInitFlag = RET_TRUE;
pin_init_flag = RET_TRUE;
}
return EOK;
@ -741,15 +741,15 @@ static uint32 Stm32GpioDrvConfigure(void *drv, struct BusConfigureInfo *configur
switch (configure_info->configure_cmd)
{
case OPE_INT:
ret = Stm32PinInit();
break;
case OPE_CFG:
param = (struct PinParam *)configure_info->private_data;
ret = Stm32PinConfigure(param);
break;
default:
break;
case OPE_INT:
ret = Stm32PinInit();
break;
case OPE_CFG:
param = (struct PinParam *)configure_info->private_data;
ret = Stm32PinConfigure(param);
break;
default:
break;
}
return ret;
@ -763,10 +763,9 @@ uint32 Stm32PinWrite(void *dev, struct BusBlockWriteParam *write_param)
const struct PinIndex* index = GetPin(pinstat->pin);
NULL_PARAM_CHECK(index);
if (GPIO_LOW == pinstat->val){
if (GPIO_LOW == pinstat->val) {
GPIO_ResetBits(index->gpio, index->pin);
}
else{
} else {
GPIO_SetBits(index->gpio, index->pin);
}
return EOK;
@ -803,7 +802,7 @@ int Stm32HwGpioInit(void)
static struct PinBus pin;
ret = PinBusInit(&pin, PIN_BUS_NAME);
if(ret != EOK) {
if (ret != EOK) {
KPrintf("gpio bus init error %d\n", ret);
return ERROR;
}
@ -812,12 +811,12 @@ int Stm32HwGpioInit(void)
drv.configure = &Stm32GpioDrvConfigure;
ret = PinDriverInit(&drv, PIN_DRIVER_NAME, NONE);
if(ret != EOK){
if (ret != EOK) {
KPrintf("pin driver init error %d\n", ret);
return ERROR;
}
ret = PinDriverAttachToBus(PIN_DRIVER_NAME, PIN_BUS_NAME);
if(ret != EOK){
if (ret != EOK) {
KPrintf("pin driver attach error %d\n", ret);
return ERROR;
}
@ -826,12 +825,12 @@ int Stm32HwGpioInit(void)
dev.dev_done = &dev_done;
ret = PinDeviceRegister(&dev, NONE, PIN_DEVICE_NAME);
if(ret != EOK){
if (ret != EOK) {
KPrintf("pin device register error %d\n", ret);
return ERROR;
}
ret = PinDeviceAttachToBus(PIN_DEVICE_NAME, PIN_BUS_NAME);
if(ret != EOK) {
if (ret != EOK) {
KPrintf("pin device register error %d\n", ret);
return ERROR;
}
@ -879,19 +878,19 @@ DECLARE_HW_IRQ(EXTI4_IRQn, EXTI4_IRQHandler, NONE);
void EXTI9_5_IRQHandler(int irq_num, void *arg)
{
if (EXTI_GetITStatus(EXTI_Line5) != RESET){
if (EXTI_GetITStatus(EXTI_Line5) != RESET) {
PinIrqHdr(5);
}
if (EXTI_GetITStatus(EXTI_Line6) != RESET){
if (EXTI_GetITStatus(EXTI_Line6) != RESET) {
PinIrqHdr(6);
}
if (EXTI_GetITStatus(EXTI_Line7) != RESET){
if (EXTI_GetITStatus(EXTI_Line7) != RESET) {
PinIrqHdr(7);
}
if (EXTI_GetITStatus(EXTI_Line8) != RESET){
if (EXTI_GetITStatus(EXTI_Line8) != RESET) {
PinIrqHdr(8);
}
if (EXTI_GetITStatus(EXTI_Line9) != RESET){
if (EXTI_GetITStatus(EXTI_Line9) != RESET) {
PinIrqHdr(9);
}
}
@ -899,22 +898,22 @@ DECLARE_HW_IRQ(EXTI9_5_IRQn, EXTI9_5_IRQHandler, NONE);
void EXTI15_10_IRQHandler(int irq_num, void *arg)
{
if (EXTI_GetITStatus(EXTI_Line10) != RESET){
if (EXTI_GetITStatus(EXTI_Line10) != RESET) {
PinIrqHdr(10);
}
if (EXTI_GetITStatus(EXTI_Line11) != RESET){
if (EXTI_GetITStatus(EXTI_Line11) != RESET) {
PinIrqHdr(11);
}
if (EXTI_GetITStatus(EXTI_Line12) != RESET) {
PinIrqHdr(12);
}
if (EXTI_GetITStatus(EXTI_Line13) != RESET){
if (EXTI_GetITStatus(EXTI_Line13) != RESET) {
PinIrqHdr(13);
}
if (EXTI_GetITStatus(EXTI_Line14) != RESET){
if (EXTI_GetITStatus(EXTI_Line14) != RESET) {
PinIrqHdr(14);
}
if (EXTI_GetITStatus(EXTI_Line15) != RESET){
if (EXTI_GetITStatus(EXTI_Line15) != RESET) {
PinIrqHdr(15);
}
}

40
board/stm32f407-st-discovery/third_party_driver/i2c/connect_i2c.c
View File

@ -49,11 +49,11 @@ static BusType pin;
#define SET_SDA(done, val) done->SetSdaState(done->data, val)
#define SET_SCL(done, val) done->SetSclState(done->data, val)
#define GET_SDA(done) done->GetSdaState(done->data)
#define GET_SCL(done) done->GetSclState(done->data)
#define SdaLow(done) SET_SDA(done, 0)
#define GET_SDA(done) done->GetSdaState(done->data)
#define GET_SCL(done) done->GetSclState(done->data)
#define SdaLow(done) SET_SDA(done, 0)
#define SdaHigh(done) SET_SDA(done, 1)
#define SclLow(done) SET_SCL(done, 0)
#define SclLow(done) SET_SCL(done, 0)
static void I2cGpioInit(const I2cBusParam *bus_param)
{
@ -192,8 +192,7 @@ static uint8 GetSclState(void *data)
ticks = us * reload / (1000000 / TICK_PER_SECOND);
told = SysTick->VAL;
while (1)
{
while (1) {
tnow = SysTick->VAL;
if (tnow != told) {
if (tnow < told) {
@ -227,8 +226,7 @@ static x_err_t I2cBusReset(const I2cBusParam *bus_param)
int32 i = 0;
if (GPIO_LOW == GetSdaState((void *)bus_param)) {
while (i++ < 9)
{
while (i++ < 9) {
SetSclState((void *)bus_param,GPIO_HIGH);
Stm32Udelay(100);
SetSclState((void *)bus_param,GPIO_LOW);
@ -384,8 +382,7 @@ static x_size_t I2cSendBytes(struct I2cBus *bus, struct I2cDataStandard *msg)
int32 count = msg->len;
uint16 ignore_nack = msg->flags & I2C_IGNORE_NACK;
while (count > 0)
{
while (count > 0) {
ret = I2cWriteb(bus, *ptr);
if ((ret > 0) || (ignore_nack && (ret == 0))) {
@ -430,8 +427,7 @@ static x_size_t I2cRecvBytes(struct I2cBus *bus, struct I2cDataStandard *msg)
int32 count = msg->len;
const uint32 flags = msg->flags;
while (count > 0)
{
while (count > 0) {
val = I2cReadb(bus);
if (val >= 0) {
*ptr = val;
@ -529,8 +525,7 @@ static uint32 I2cWriteData(struct I2cHardwareDevice *i2c_dev, struct I2cDataStan
uint16 ignore_nack;
I2cStart(done);
while (NONE != msg)
{
while (NONE != msg) {
ignore_nack = msg->flags & I2C_IGNORE_NACK;
if (!(msg->flags & I2C_NO_START)) {
if (i) {
@ -573,8 +568,7 @@ static uint32 I2cReadData(struct I2cHardwareDevice *i2c_dev, struct I2cDataStand
uint16 ignore_nack;
I2cStart(done);
while (NONE != msg)
{
while (NONE != msg) {
ignore_nack = msg->flags & I2C_IGNORE_NACK;
if (!(msg->flags & I2C_NO_START)) {
if (i) {
@ -623,7 +617,7 @@ static int BoardI2cBusInit(struct I2cBus *i2c_bus, struct I2cDriver *i2c_driver)
/*Init the i2c bus */
i2c_bus->private_data = (void *)&i2c_hal_drv_done;
ret = I2cBusInit(i2c_bus, I2C_BUS_NAME_1);
if(EOK != ret){
if (EOK != ret) {
KPrintf("board_i2c_init I2cBusInit error %d\n", ret);
return ERROR;
}
@ -631,14 +625,14 @@ static int BoardI2cBusInit(struct I2cBus *i2c_bus, struct I2cDriver *i2c_driver)
/*Init the i2c driver*/
i2c_driver->private_data = (void *)&i2c_hal_drv_done;
ret = I2cDriverInit(i2c_driver, I2C_DRV_NAME_1);
if(EOK != ret) {
if (EOK != ret) {
KPrintf("board_i2c_init I2cDriverInit error %d\n", ret);
return ERROR;
}
/*Attach the i2c driver to the i2c bus*/
ret = I2cDriverAttachToBus(I2C_DRV_NAME_1, I2C_BUS_NAME_1);
if(EOK != ret){
if (EOK != ret) {
KPrintf("board_i2c_init I2cDriverAttachToBus error %d\n", ret);
return ERROR;
}
@ -656,13 +650,13 @@ static int BoardI2cDevBend(void)
i2c_device0.i2c_dev_done = &i2c_dev_done;
ret = I2cDeviceRegister(&i2c_device0, NONE, I2C_1_DEVICE_NAME_0);
if(EOK != ret){
if (EOK != ret) {
KPrintf("board_i2c_init I2cDeviceInit device %s error %d\n", I2C_1_DEVICE_NAME_0, ret);
return ERROR;
}
ret = I2cDeviceAttachToBus(I2C_1_DEVICE_NAME_0, I2C_BUS_NAME_1);
if(EOK != ret){
if (EOK != ret) {
KPrintf("board_i2c_init I2cDeviceAttachToBus device %s error %d\n", I2C_1_DEVICE_NAME_0, ret);
return ERROR;
}
@ -684,13 +678,13 @@ int Stm32HwI2cInit(void)
I2cGpioInit(&i2c_bus_param);
ret = BoardI2cBusInit(&i2c_bus, &i2c_driver);
if(EOK != ret){
if (EOK != ret) {
KPrintf("board_i2c_Init error ret %u\n", ret);
return ERROR;
}
ret = BoardI2cDevBend();
if(EOK != ret){
if (EOK != ret) {
KPrintf("board_i2c_Init error ret %u\n", ret);
return ERROR;
}

1
board/stm32f407-st-discovery/third_party_driver/include/connect_can.h
View File

@ -21,6 +21,7 @@
#ifndef CONNECT_CAN_H
#define CONNECT_CAN_H
#include <device.h>
#include "hardware_can.h"
#ifdef __cplusplus

6
board/stm32f407-st-discovery/third_party_driver/include/connect_spi.h
View File

@ -56,7 +56,7 @@ struct Stm32Spi
{
SPI_TypeDef *instance;
char *BusName;
char *bus_name;
SPI_InitTypeDef init;
@ -67,11 +67,11 @@ struct Stm32Spi
}dma;
uint8 spi_dma_flag;
struct SpiBus SpiBus;
struct SpiBus spi_bus;
};
int Stm32HwSpiInit(void);
x_err_t HwSpiDeviceAttach(const char *BusName, const char *device_name, GPIO_TypeDef *cs_gpiox, uint16_t cs_gpio_pin);
x_err_t HwSpiDeviceAttach(const char *bus_name, const char *device_name, GPIO_TypeDef *cs_gpiox, uint16_t cs_gpio_pin);
#ifdef __cplusplus
}

6
board/stm32f407-st-discovery/third_party_driver/include/connect_usart.h
View File

@ -29,8 +29,8 @@
extern "C" {
#endif
#define KERNEL_CONSOLE_BUS_NAME SERIAL_BUS_NAME_1
#define KERNEL_CONSOLE_DRV_NAME SERIAL_DRV_NAME_1
#define KERNEL_CONSOLE_BUS_NAME SERIAL_BUS_NAME_1
#define KERNEL_CONSOLE_DRV_NAME SERIAL_DRV_NAME_1
#define KERNEL_CONSOLE_DEVICE_NAME SERIAL_1_DEVICE_NAME_0
struct UsartHwCfg
@ -51,7 +51,7 @@ struct Stm32Usart
x_size_t LastRecvIndex;
} dma;
struct SerialBus SerialBus;
struct SerialBus serial_bus;
};
int Stm32HwUsartInit(void);

2
board/stm32f407-st-discovery/third_party_driver/rtc/connect_rtc.c
View File

@ -29,7 +29,7 @@
static int GetWeekDay(int year, int month, int day)
{
if (month==1||month==2){
if (month==1||month==2) {
year -=1;
month +=12;
}

48
board/stm32f407-st-discovery/third_party_driver/sdio/connect_sdio.c
View File

@ -41,8 +41,7 @@ static uint32 SdioConfigure(void *drv, struct BusConfigureInfo *configure_info)
NULL_PARAM_CHECK(drv);
NULL_PARAM_CHECK(configure_info);
if(configure_info->configure_cmd == OPER_BLK_GETGEOME)
{
if (configure_info->configure_cmd == OPER_BLK_GETGEOME) {
NULL_PARAM_CHECK(configure_info->private_data);
struct DeviceBlockArrange *args = (struct DeviceBlockArrange *)configure_info->private_data;
SD_GetCardInfo(&SDCardInfo);
@ -91,16 +90,14 @@ static uint32 SdioRead(void *dev, struct BusBlockReadParam *read_param)
KSemaphoreObtain(sd_lock, WAITING_FOREVER);
if(((uint32)read_param->buffer & 0x03) != 0)
{
if (((uint32)read_param->buffer & 0x03) != 0) {
uint64_t sector;
uint8_t* temp;
sector = (uint64_t)read_param->pos * SDCARD_SECTOR_SIZE;
temp = (uint8_t*)read_param->buffer;
for (uint8 i = 0; i < read_param->size; i++)
{
for (uint8 i = 0; i < read_param->size; i++) {
ret = SD_ReadBlock((uint8_t *)SDBuffer, sector, 1);
if(ret != SD_OK) {
KPrintf("read failed: %d, buffer 0x%08x\n", ret, temp);
@ -108,8 +105,7 @@ static uint32 SdioRead(void *dev, struct BusBlockReadParam *read_param)
}
#if defined (SD_DMA_MODE)
ret = SD_WaitReadOperation();
if(ret != SD_OK)
{
if (ret != SD_OK) {
KPrintf("read failed: %d, buffer 0x%08x\n", ret, temp);
return 0;
}
@ -119,17 +115,15 @@ static uint32 SdioRead(void *dev, struct BusBlockReadParam *read_param)
sector += SDCARD_SECTOR_SIZE;
temp += SDCARD_SECTOR_SIZE;
}
}
else
{
} else {
ret = SD_ReadBlock((uint8_t *)read_param->buffer, (uint64_t)read_param->pos * SDCARD_SECTOR_SIZE, read_param->size);
if(ret != SD_OK){
if (ret != SD_OK) {
KPrintf("read failed: %d, buffer 0x%08x\n", ret, (uint8_t *)read_param->buffer);
return 0;
}
#if defined (SD_DMA_MODE)
ret = SD_WaitReadOperation();
if(ret != SD_OK){
if (ret != SD_OK) {
KPrintf("read failed: %d, buffer 0x%08x\n", ret, (uint8_t *)read_param->buffer);
return 0;
}
@ -147,16 +141,14 @@ static uint32 SdioWrite(void *dev, struct BusBlockWriteParam *write_param)
KSemaphoreObtain(sd_lock, WAITING_FOREVER);
if(((uint32)write_param->buffer & 0x03) != 0)
{
if (((uint32)write_param->buffer & 0x03) != 0) {
uint64_t sector;
uint8_t* temp;
sector = (uint64_t)write_param->pos * SDCARD_SECTOR_SIZE;
temp = (uint8_t*)write_param->buffer;
for (uint8 i = 0; i < write_param->size; i++)
{
for (uint8 i = 0; i < write_param->size; i++) {
memcpy(SDBuffer, temp, SDCARD_SECTOR_SIZE);
ret = SD_WriteBlock((uint8_t *)SDBuffer, sector, 1);
@ -166,7 +158,7 @@ static uint32 SdioWrite(void *dev, struct BusBlockWriteParam *write_param)
}
#if defined (SD_DMA_MODE)
ret = SD_WaitWriteOperation();
if(ret != SD_OK){
if (ret != SD_OK) {
KPrintf("write failed: %d, buffer 0x%08x\n", ret, temp);
return 0;
}
@ -174,17 +166,15 @@ static uint32 SdioWrite(void *dev, struct BusBlockWriteParam *write_param)
sector += SDCARD_SECTOR_SIZE;
temp += SDCARD_SECTOR_SIZE;
}
}
else
{
} else {
ret = SD_WriteBlock((uint8_t *)write_param->buffer, (uint64_t)write_param->pos * SDCARD_SECTOR_SIZE, write_param->size);
if(ret != SD_OK) {
if (ret != SD_OK) {
KPrintf("write failed: %d, buffer 0x%08x\n", ret, (uint8_t *)write_param->buffer);
return 0;
}
#if defined (SD_DMA_MODE)
ret = SD_WaitWriteOperation();
if(ret != SD_OK){
if (ret != SD_OK){
KPrintf("write failed: %d, buffer 0x%08x\n", ret, (uint8_t *)write_param->buffer);
return 0;
}
@ -212,36 +202,36 @@ int HwSdioInit(void)
x_err_t ret = EOK;
ret = SD_Init();
if(ret != SD_OK){
if (ret != SD_OK) {
KPrintf("SD init failed!");
return ERROR;
}
ret = SdioBusInit(&bus, SDIO_BUS_NAME);
if(ret != EOK){
if (ret != EOK) {
KPrintf("Sdio bus init error %d\n", ret);
return ERROR;
}
ret = SdioDriverInit(&drv, SDIO_DRIVER_NAME);
if(ret != EOK){
if (ret != EOK) {
KPrintf("Sdio driver init error %d\n", ret);
return ERROR;
}
ret = SdioDriverAttachToBus(SDIO_DRIVER_NAME, SDIO_BUS_NAME);
if(ret != EOK){
if (ret != EOK) {
KPrintf("Sdio driver attach error %d\n", ret);
return ERROR;
}
dev.dev_done = &dev_done;
ret = SdioDeviceRegister(&dev, SDIO_DEVICE_NAME);
if(ret != EOK) {
if (ret != EOK) {
KPrintf("Sdio device register error %d\n", ret);
return ERROR;
}
ret = SdioDeviceAttachToBus(SDIO_DEVICE_NAME, SDIO_BUS_NAME);
if(ret != EOK){
if (ret != EOK) {
KPrintf("Sdio device register error %d\n", ret);
return ERROR;
}

4
board/stm32f407-st-discovery/third_party_driver/spi/connect_flash_spi.c
View File

@ -42,11 +42,11 @@ int FlashW25qxxSpiDeviceInit(void)
tmpreg = RCC->AHB1ENR & RCC_AHB1ENR_GPIOBEN;
(void)tmpreg;
if(EOK != HwSpiDeviceAttach(SPI_BUS_NAME_1, "spi1_dev0", GPIOB, GPIO_Pin_0)){
if (EOK != HwSpiDeviceAttach(SPI_BUS_NAME_1, "spi1_dev0", GPIOB, GPIO_Pin_0)) {
return ERROR;
}
if(NONE == SpiFlashInit(SPI_BUS_NAME_1, "spi1_dev0", SPI_1_DRV_NAME, "W25Q64")){
if (NONE == SpiFlashInit(SPI_BUS_NAME_1, "spi1_dev0", SPI_1_DRV_NAME, "W25Q64")) {
return ERROR;
}

187
board/stm32f407-st-discovery/third_party_driver/spi/connect_spi.c
View File

@ -227,9 +227,9 @@ static x_err_t Stm32SpiInit(struct Stm32Spi *spi_drv, struct SpiMasterParam *cfg
return EOK;
}
static void DmaSpiConfig(struct SpiBus *SpiBus, uint32_t setting_len, void *rx_base_addr, void *tx_base_addr)
static void DmaSpiConfig(struct SpiBus *spi_bus, uint32_t setting_len, void *rx_base_addr, void *tx_base_addr)
{
struct Stm32Spi *spi = (struct Stm32Spi *)SpiBus->private_data;
struct Stm32Spi *spi = (struct Stm32Spi *)spi_bus->private_data;
uint32 tmpreg = 0x00U;
NVIC_InitTypeDef NVIC_InitStructure;
@ -314,9 +314,9 @@ static void DmaSpiConfig(struct SpiBus *SpiBus, uint32_t setting_len, void *rx_b
}
static void DmaRxDoneIsr(struct SpiBus *SpiBus)
static void DmaRxDoneIsr(struct SpiBus *spi_bus)
{
struct Stm32Spi *spi = (struct Stm32Spi *) SpiBus->bus.private_data;
struct Stm32Spi *spi = (struct Stm32Spi *) spi_bus->bus.private_data;
x_size_t recv_len;
x_base level;
@ -332,9 +332,9 @@ static void DmaRxDoneIsr(struct SpiBus *SpiBus)
}
static void DmaTxDoneIsr(struct SpiBus *SpiBus)
static void DmaTxDoneIsr(struct SpiBus *spi_bus)
{
struct Stm32Spi *spi = (struct Stm32Spi *) SpiBus->bus.private_data;
struct Stm32Spi *spi = (struct Stm32Spi *) spi_bus->bus.private_data;
x_size_t send_len;
x_base level;
@ -1062,26 +1062,23 @@ static uint32 Stm32SpiWriteData(struct SpiHardwareDevice *spi_dev, struct SpiDat
NULL_PARAM_CHECK(spi_dev);
NULL_PARAM_CHECK(spi_datacfg);
struct Stm32Spi *StmSpi = CONTAINER_OF(spi_dev->haldev.owner_bus, struct Stm32Spi, SpiBus);
struct Stm32Spi *StmSpi = CONTAINER_OF(spi_dev->haldev.owner_bus, struct Stm32Spi, spi_bus);
SPI_TypeDef *spi_instance = StmSpi->instance;
SPI_InitTypeDef *spi_init = &StmSpi->init;
struct Stm32HwSpiCs *cs = (struct Stm32HwSpiCs *)spi_dev->haldev.private_data;
struct Stm32HwSpiCs *cs = (struct Stm32HwSpiCs *)spi_dev->private_data;
while(NONE != spi_datacfg)
{
while(NONE != spi_datacfg) {
if(spi_datacfg->spi_chip_select) {
GPIO_WriteBit(cs->GPIOx, cs->GPIO_Pin, Bit_RESET);
}
message_length = spi_datacfg->length;
WriteBuf = spi_datacfg->tx_buff;
while (message_length)
{
while (message_length) {
if (message_length > 65535){
send_length = 65535;
message_length = message_length - 65535;
}
else{
} else {
send_length = message_length;
message_length = 0;
}
@ -1091,23 +1088,21 @@ static uint32 Stm32SpiWriteData(struct SpiHardwareDevice *spi_dev, struct SpiDat
WriteBuf = (uint8 *)spi_datacfg->tx_buff + already_send_length;
/* start once data exchange in DMA mode */
if (spi_datacfg->tx_buff)
{
if (spi_datacfg->tx_buff) {
if (StmSpi->spi_dma_flag & SPI_USING_TX_DMA_FLAG) {
state = SpiTransmitDma(*spi_init, spi_instance, StmSpi->dma.dma_tx.init, StmSpi->dma.dma_tx.instance, (uint8_t *)WriteBuf, send_length);
}
else {
} else {
state = SpiTransmit(*spi_init, spi_instance, (uint8_t *)WriteBuf, send_length, 1000);
}
}
if (state != 0){
if (state != 0) {
KPrintf("spi transfer error : %d\n", state);
spi_datacfg->length = 0;
}
}
if (spi_datacfg->spi_cs_release){
if (spi_datacfg->spi_cs_release) {
GPIO_WriteBit(cs->GPIOx, cs->GPIO_Pin, Bit_SET);
}
@ -1136,26 +1131,23 @@ static uint32 Stm32SpiReadData(struct SpiHardwareDevice *spi_dev, struct SpiData
NULL_PARAM_CHECK(spi_dev);
NULL_PARAM_CHECK(spi_datacfg);
struct Stm32Spi *StmSpi = CONTAINER_OF(spi_dev->haldev.owner_bus, struct Stm32Spi, SpiBus);
struct Stm32Spi *StmSpi = CONTAINER_OF(spi_dev->haldev.owner_bus, struct Stm32Spi, spi_bus);
SPI_TypeDef *spi_instance = StmSpi->instance;
SPI_InitTypeDef *spi_init = &StmSpi->init;
struct Stm32HwSpiCs *cs = (struct Stm32HwSpiCs *)spi_dev->haldev.private_data;
struct Stm32HwSpiCs *cs = (struct Stm32HwSpiCs *)spi_dev->private_data;
while(NONE != spi_datacfg)
{
if(spi_datacfg->spi_chip_select){
while (NONE != spi_datacfg) {
if (spi_datacfg->spi_chip_select) {
GPIO_WriteBit(cs->GPIOx, cs->GPIO_Pin, Bit_RESET);
}
message_length = spi_datacfg->length;
ReadBuf = spi_datacfg->rx_buff;
while (message_length)
{
while (message_length) {
if (message_length > 65535) {
send_length = 65535;
message_length = message_length - 65535;
}
else{
} else {
send_length = message_length;
message_length = 0;
}
@ -1165,12 +1157,11 @@ static uint32 Stm32SpiReadData(struct SpiHardwareDevice *spi_dev, struct SpiData
ReadBuf = (uint8 *)spi_datacfg->rx_buff + already_send_length;
/* start once data exchange in DMA mode */
if (spi_datacfg->rx_buff){
if (spi_datacfg->rx_buff) {
memset((uint8_t *)ReadBuf, 0xff, send_length);
if (StmSpi->spi_dma_flag & SPI_USING_RX_DMA_FLAG) {
state = SpiReceiveDma(*spi_init, spi_instance, StmSpi->dma.dma_rx.init, StmSpi->dma.dma_rx.instance, StmSpi->dma.dma_tx.init, StmSpi->dma.dma_tx.instance, (uint8_t *)ReadBuf, send_length);
}
else {
} else {
state = SpiReceive(*spi_init, spi_instance, (uint8_t *)ReadBuf, send_length, 1000);
}
}
@ -1181,7 +1172,7 @@ static uint32 Stm32SpiReadData(struct SpiHardwareDevice *spi_dev, struct SpiData
}
}
if (spi_datacfg->spi_cs_release){
if (spi_datacfg->spi_cs_release) {
GPIO_WriteBit(cs->GPIOx, cs->GPIO_Pin, Bit_SET);
}
@ -1204,7 +1195,7 @@ static uint32 SpiDrvInit(struct SpiDriver *spi_drv)
SpiDeviceParam *dev_param = (SpiDeviceParam *)(spi_drv->driver.private_data);
struct Stm32Spi *StmSpi = CONTAINER_OF(spi_drv->driver.owner_bus, struct Stm32Spi, SpiBus);
struct Stm32Spi *StmSpi = CONTAINER_OF(spi_drv->driver.owner_bus, struct Stm32Spi, spi_bus);
return Stm32SpiInit(StmSpi, dev_param->spi_master_param);
}
@ -1243,15 +1234,15 @@ static uint32 Stm32SpiDrvConfigure(void *drv, struct BusConfigureInfo *configure
switch (configure_info->configure_cmd)
{
case OPE_INT:
ret = SpiDrvInit(spi_drv);
break;
case OPE_CFG:
spi_param = (struct SpiMasterParam *)configure_info->private_data;
ret = SpiDrvConfigure(spi_drv, spi_param);
break;
default:
break;
case OPE_INT:
ret = SpiDrvInit(spi_drv);
break;
case OPE_CFG:
spi_param = (struct SpiMasterParam *)configure_info->private_data;
ret = SpiDrvConfigure(spi_drv, spi_param);
break;
default:
break;
}
return ret;
@ -1260,10 +1251,10 @@ static uint32 Stm32SpiDrvConfigure(void *drv, struct BusConfigureInfo *configure
/*manage the spi device operations*/
static const struct SpiDevDone spi_dev_done =
{
.open = NONE,
.close = NONE,
.write = Stm32SpiWriteData,
.read = Stm32SpiReadData,
.open = NONE,
.close = NONE,
.write = Stm32SpiWriteData,
.read = Stm32SpiReadData,
};
#if defined(BSP_USING_SPI1)
@ -1271,7 +1262,7 @@ struct Stm32Spi spi1;
#if defined(BSP_SPI1_TX_USING_DMA)
void DMA2_Stream3_IRQHandler(int irq_num, void *arg)
{
DmaTxDoneIsr(&spi1.SpiBus);
DmaTxDoneIsr(&spi1.spi_bus);
}
DECLARE_HW_IRQ(DMA2_Stream3_IRQn, DMA2_Stream3_IRQHandler, NONE);
#endif
@ -1279,7 +1270,7 @@ DECLARE_HW_IRQ(DMA2_Stream3_IRQn, DMA2_Stream3_IRQHandler, NONE);
#if defined(BSP_SPI1_RX_USING_DMA)
void DMA2_Stream0_IRQHandler(int irq_num, void *arg)
{
DmaRxDoneIsr(&spi1.SpiBus);
DmaRxDoneIsr(&spi1.spi_bus);
}
DECLARE_HW_IRQ(DMA2_Stream0_IRQn, DMA2_Stream0_IRQHandler, NONE);
#endif
@ -1290,7 +1281,7 @@ struct Stm32Spi spi2;
#if defined(BSP_SPI2_TX_USING_DMA)
void DMA1_Stream4_IRQHandler(int irq_num, void *arg)
{
DmaTxDoneIsr(&spi2.SpiBus);
DmaTxDoneIsr(&spi2.spi_bus);
}
DECLARE_HW_IRQ(DMA1_Stream4_IRQn, DMA1_Stream4_IRQHandler, NONE);
#endif
@ -1298,7 +1289,7 @@ DECLARE_HW_IRQ(DMA1_Stream4_IRQn, DMA1_Stream4_IRQHandler, NONE);
#if defined(BSP_SPI2_RX_USING_DMA)
void DMA1_Stream3_IRQHandler(int irq_num, void *arg)
{
DmaTxDoneIsr(&spi2.SpiBus);
DmaTxDoneIsr(&spi2.spi_bus);
}
DECLARE_HW_IRQ(DMA1_Stream3_IRQn, DMA1_Stream3_IRQHandler, NONE);
#endif
@ -1309,7 +1300,7 @@ struct Stm32Spi spi3;
#if defined(BSP_SPI3_TX_USING_DMA)
void DMA1_Stream7_IRQHandler(int irq_num, void *arg)
{
DmaTxDoneIsr(&spi3.SpiBus);
DmaTxDoneIsr(&spi3.spi_bus);
}
DECLARE_HW_IRQ(DMA1_Stream7_IRQn, DMA1_Stream7_IRQHandler, NONE);
#endif
@ -1322,11 +1313,12 @@ DECLARE_HW_IRQ(DMA1_Stream7_IRQn, DMA1_Stream7_IRQHandler, NONE);
*/
void DMA1_Stream2_IRQHandler(int irq_num, void *arg)
{
DmaRxDoneIsr(&spi3.SpiBus);
DmaRxDoneIsr(&spi3.spi_bus);
}
DECLARE_HW_IRQ(DMA1_Stream2_IRQn, DMA1_Stream2_IRQHandler, NONE);
#endif
#endif
/**
* This function RCC clock configuration function
*
@ -1409,7 +1401,6 @@ static void GPIOConfiguration(void)
#endif
}
/**
* This function Init the spi bus 、spi driver and attach to the bus
*
@ -1424,22 +1415,22 @@ static int BoardSpiBusInit(struct Stm32Spi *stm32spi_bus, struct SpiDriver *spi_
x_err_t ret = EOK;
/*Init the spi bus */
ret = SpiBusInit(&stm32spi_bus->SpiBus, stm32spi_bus->BusName);
if(EOK != ret){
ret = SpiBusInit(&stm32spi_bus->spi_bus, stm32spi_bus->bus_name);
if (EOK != ret) {
KPrintf("Board_Spi_init SpiBusInit error %d\n", ret);
return ERROR;
}
/*Init the spi driver*/
ret = SpiDriverInit(spi_driver, drv_name);
if(EOK != ret){
if (EOK != ret) {
KPrintf("Board_Spi_init SpiDriverInit error %d\n", ret);
return ERROR;
}
/*Attach the spi driver to the spi bus*/
ret = SpiDriverAttachToBus(drv_name, stm32spi_bus->BusName);
if(EOK != ret){
ret = SpiDriverAttachToBus(drv_name, stm32spi_bus->bus_name);
if (EOK != ret) {
KPrintf("Board_Spi_init SpiDriverAttachToBus error %d\n", ret);
return ERROR;
}
@ -1464,9 +1455,9 @@ static int Stm32HwSpiBusInit(void)
#ifdef BSP_USING_SPI1
StmSpiBus = &spi1;
StmSpiBus->instance = SPI1;
StmSpiBus->BusName = SPI_BUS_NAME_1;
StmSpiBus->SpiBus.private_data = &spi1;
DmaSpiConfig(&StmSpiBus->SpiBus, 0, NONE, NONE);
StmSpiBus->bus_name = SPI_BUS_NAME_1;
StmSpiBus->spi_bus.private_data = &spi1;
DmaSpiConfig(&StmSpiBus->spi_bus, 0, NONE, NONE);
static struct SpiDriver spi_driver_1;
memset(&spi_driver_1, 0, sizeof(struct SpiDriver));
@ -1474,9 +1465,8 @@ static int Stm32HwSpiBusInit(void)
spi_driver_1.configure = &(Stm32SpiDrvConfigure);
ret = BoardSpiBusInit(StmSpiBus, &spi_driver_1, SPI_1_DRV_NAME);
if(EOK != ret)
{
KPrintf("Board_Spi_Init spi_bus_init %s error ret %u\n", StmSpiBus->BusName, ret);
if (EOK != ret) {
KPrintf("Board_Spi_Init spi_bus_init %s error ret %u\n", StmSpiBus->bus_name, ret);
return ERROR;
}
#endif
@ -1484,9 +1474,9 @@ static int Stm32HwSpiBusInit(void)
#ifdef BSP_USING_SPI2
StmSpiBus = &spi2;
StmSpiBus->instance = SPI2;
StmSpiBus->BusName = SPI_BUS_NAME_2;
StmSpiBus->SpiBus.private_data = &spi2;
DmaSpiConfig(&StmSpiBus->SpiBus, 0, NONE, NONE);
StmSpiBus->bus_name = SPI_BUS_NAME_2;
StmSpiBus->spi_bus.private_data = &spi2;
DmaSpiConfig(&StmSpiBus->spi_bus, 0, NONE, NONE);
static struct SpiDriver spi_driver_2;
memset(&spi_driver_2, 0, sizeof(struct SpiDriver));
@ -1494,9 +1484,8 @@ static int Stm32HwSpiBusInit(void)
spi_driver_2.configure = &(Stm32SpiDrvConfigure);
ret = BoardSpiBusInit(StmSpiBus, &spi_driver_2, SPI_2_DRV_NAME);
if(EOK != ret)
{
KPrintf("Board_Spi_Init spi_bus_init %s error ret %u\n", StmSpiBus->BusName, ret);
if (EOK != ret) {
KPrintf("Board_Spi_Init spi_bus_init %s error ret %u\n", StmSpiBus->bus_name, ret);
return ERROR;
}
#endif
@ -1504,9 +1493,9 @@ static int Stm32HwSpiBusInit(void)
#ifdef BSP_USING_SPI3
StmSpiBus = &spi3;
StmSpiBus->instance = SPI3;
StmSpiBus->BusName = SPI_BUS_NAME_3;
StmSpiBus->SpiBus.private_data = &spi3;
DmaSpiConfig(&StmSpiBus->SpiBus, 0, NONE, NONE);
StmSpiBus->bus_name = SPI_BUS_NAME_3;
StmSpiBus->spi_bus.private_data = &spi3;
DmaSpiConfig(&StmSpiBus->spi_bus, 0, NONE, NONE);
static struct SpiDriver spi_driver_3;
memset(&spi_driver_3, 0, sizeof(struct SpiDriver));
@ -1514,9 +1503,8 @@ static int Stm32HwSpiBusInit(void)
spi_driver_3.configure = &(Stm32SpiDrvConfigure);
ret = BoardSpiBusInit(StmSpiBus, &spi_driver_3, SPI_3_DRV_NAME);
if(EOK != ret)
{
KPrintf("Board_Spi_Init spi_bus_init %s error ret %u\n", StmSpiBus->BusName, ret);
if (EOK != ret) {
KPrintf("Board_Spi_Init spi_bus_init %s error ret %u\n", StmSpiBus->bus_name, ret);
return ERROR;
}
#endif
@ -1526,7 +1514,7 @@ static int Stm32HwSpiBusInit(void)
/**
* This function Mount the spi device to the bus
*
* @param BusName Bus Name
* @param bus_name Bus Name
*
* @param device_name spi device name
*
@ -1536,15 +1524,17 @@ static int Stm32HwSpiBusInit(void)
*
* @return EOK
*/
x_err_t HwSpiDeviceAttach(const char *BusName, const char *device_name, GPIO_TypeDef *cs_gpiox, uint16_t cs_gpio_pin)
x_err_t HwSpiDeviceAttach(const char *bus_name, const char *device_name, GPIO_TypeDef *cs_gpiox, uint16_t cs_gpio_pin)
{
NULL_PARAM_CHECK(BusName);
NULL_PARAM_CHECK(bus_name);
NULL_PARAM_CHECK(device_name);
x_err_t result;
struct SpiHardwareDevice *SpiDevice;
struct Stm32HwSpiCs *CsPin;
struct SpiHardwareDevice *spi_device;
struct Stm32HwSpiCs *cs_pin_param;
static SpiDeviceParam spi_dev_param;
memset(&spi_dev_param, 0, sizeof(SpiDeviceParam));
/* initialize the cs pin && select the slave*/
GPIO_InitTypeDef GPIO_Initure;
@ -1556,31 +1546,33 @@ x_err_t HwSpiDeviceAttach(const char *BusName, const char *device_name, GPIO_Typ
GPIO_WriteBit(cs_gpiox, cs_gpio_pin, Bit_SET);
/* attach the device to spi bus*/
SpiDevice = (struct SpiHardwareDevice *)x_malloc(sizeof(struct SpiHardwareDevice));
CHECK(SpiDevice);
memset(SpiDevice, 0, sizeof(struct SpiHardwareDevice));
CsPin = (struct Stm32HwSpiCs *)x_malloc(sizeof(struct Stm32HwSpiCs));
CHECK(CsPin);
memset(CsPin, 0, sizeof(struct Stm32HwSpiCs));
CsPin->GPIOx = cs_gpiox;
CsPin->GPIO_Pin = cs_gpio_pin;
spi_device = (struct SpiHardwareDevice *)x_malloc(sizeof(struct SpiHardwareDevice));
CHECK(spi_device);
memset(spi_device, 0, sizeof(struct SpiHardwareDevice));
cs_pin_param = (struct Stm32HwSpiCs *)x_malloc(sizeof(struct Stm32HwSpiCs));
CHECK(cs_pin_param);
memset(cs_pin_param, 0, sizeof(struct Stm32HwSpiCs));
cs_pin_param->GPIOx = cs_gpiox;
cs_pin_param->GPIO_Pin = cs_gpio_pin;
SpiDevice->spi_dev_done = &spi_dev_done;
spi_device->spi_dev_done = &spi_dev_done;
spi_device->private_data = (void *)cs_pin_param;
result = SpiDeviceRegister(SpiDevice, (void *)CsPin, device_name);
if (result != EOK){
SYS_ERR("%s device %p register faild, %d\n", device_name, SpiDevice, result);
result = SpiDeviceRegister(spi_device, (void *)&spi_dev_param, device_name);
if (result != EOK) {
SYS_ERR("%s device %p register faild, %d\n", device_name, spi_device, result);
}
result = SpiDeviceAttachToBus(device_name, BusName);
if (result != EOK){
SYS_ERR("%s attach to %s faild, %d\n", device_name, BusName, result);
result = SpiDeviceAttachToBus(device_name, bus_name);
if (result != EOK) {
SYS_ERR("%s attach to %s faild, %d\n", device_name, bus_name, result);
}
CHECK(result == EOK);
return result;
}
/**
* This function Get DMA information
*
@ -1633,6 +1625,7 @@ static void Stm32GetDmaInfo(void)
spi3.dma.dma_tx.dma_irq = DMA1_Stream7_IRQn; /*Enable DMA interrupt line*/
#endif
}
/**
* This function hardware spi initialization
*

29
board/stm32f407-st-discovery/third_party_driver/timer/connect_hwtimer.c
View File

@ -47,11 +47,9 @@ void TIM2_IRQHandler(int irq_num, void *arg)
TIM_ClearITPendingBit(TIM2, TIM_IT_Update);
KPrintf("hwtimer 2 ... come ...\n");
if (ptim2_cb_info)
{
if (ptim2_cb_info->TimeoutCb)
{
ptim2_cb_info->TimeoutCb(ptim2_cb_info->param);
if (ptim2_cb_info) {
if (ptim2_cb_info->timeout_callback) {
ptim2_cb_info->timeout_callback(ptim2_cb_info->param);
}
}
}
@ -98,10 +96,10 @@ uint32 HwtimerClose(void *dev)
/*manage the hwtimer device operations*/
static const struct HwtimerDevDone dev_done =
{
.open = HwtimerOpen,
.close = HwtimerClose,
.write = NONE,
.read = NONE,
.open = HwtimerOpen,
.close = HwtimerClose,
.write = NONE,
.read = NONE,
};
/*Init hwtimer bus*/
@ -120,14 +118,14 @@ static int BoardHwtimerBusInit(struct HwtimerBus *hwtimer_bus, struct HwtimerDri
/*Init the hwtimer driver*/
hwtimer_driver->configure = NONE;
ret = HwtimerDriverInit(hwtimer_driver, HWTIMER_DRIVER_NAME_2);
if (EOK != ret){
if (EOK != ret) {
KPrintf("board_hwtimer_init HwtimerDriverInit error %d\n", ret);
return ERROR;
}
/*Attach the hwtimer driver to the hwtimer bus*/
ret = HwtimerDriverAttachToBus(HWTIMER_DRIVER_NAME_2, HWTIMER_BUS_NAME_2);
if (EOK != ret){
if (EOK != ret) {
KPrintf("board_hwtimer_init USEDriverAttachToBus error %d\n", ret);
return ERROR;
}
@ -147,13 +145,13 @@ static int BoardHwtimerDevBend(void)
hwtimer_device_2.dev_done = &dev_done;
ret = HwtimerDeviceRegister(&hwtimer_device_2, NONE, HWTIMER_2_DEVICE_NAME_2);
if (EOK != ret){
if (EOK != ret) {
KPrintf("board_hwtimer_init HWTIMERDeviceInit device %s error %d\n", HWTIMER_2_DEVICE_NAME_2, ret);
return ERROR;
}
ret = HwtimerDeviceAttachToBus(HWTIMER_2_DEVICE_NAME_2, HWTIMER_BUS_NAME_2);
if (EOK != ret){
if (EOK != ret) {
KPrintf("board_hwtimer_init HwtimerDeviceAttachToBus device %s error %d\n", HWTIMER_2_DEVICE_NAME_2, ret);
return ERROR;
}
@ -172,15 +170,14 @@ int Stm32HwTimerInit(void)
static struct HwtimerDriver hwtimer_driver;
memset(&hwtimer_driver, 0, sizeof(struct HwtimerDriver));
ret = BoardHwtimerBusInit(&hwtimer_bus, &hwtimer_driver);
if (EOK != ret){
if (EOK != ret) {
KPrintf("board_hwtimer_Init error ret %u\n", ret);
return ERROR;
}
ret = BoardHwtimerDevBend();
if (EOK != ret){
if (EOK != ret) {
KPrintf("board_hwtimer_Init error ret %u\n", ret);
return ERROR;
}

95
board/stm32f407-st-discovery/third_party_driver/uart/connect_usart.c
View File

@ -199,7 +199,7 @@ static void DmaUartConfig(struct Stm32UsartDma *dma, USART_TypeDef *uart_device,
static void DMAConfiguration(struct SerialHardwareDevice *serial_dev, USART_TypeDef *uart_device)
{
struct Stm32Usart *serial = CONTAINER_OF(serial_dev->haldev.owner_bus, struct Stm32Usart, SerialBus);
struct Stm32Usart *serial = CONTAINER_OF(serial_dev->haldev.owner_bus, struct Stm32Usart, serial_bus);
struct Stm32UsartDma *dma = &serial->dma;
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
@ -229,7 +229,7 @@ static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struc
struct SerialDataCfg *data_cfg_default = &serial_cfg_default->data_cfg;
struct SerialDataCfg *data_cfg_new = &serial_cfg_new->data_cfg;
if((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)){
if((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) {
data_cfg_default->serial_baud_rate = data_cfg_new->serial_baud_rate;
}
@ -237,7 +237,7 @@ static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struc
data_cfg_default->serial_bit_order = data_cfg_new->serial_bit_order;
}
if((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)){
if((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)) {
data_cfg_default->serial_buffer_size = data_cfg_new->serial_buffer_size;
}
@ -249,7 +249,7 @@ static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struc
data_cfg_default->serial_invert_mode = data_cfg_new->serial_invert_mode;
}
if((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)){
if((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)) {
data_cfg_default->serial_parity_mode = data_cfg_new->serial_parity_mode;
}
@ -265,7 +265,7 @@ static uint32 Stm32SerialInit(struct SerialDriver *serial_drv, struct BusConfigu
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
if(configure_info->private_data){
if (configure_info->private_data) {
struct SerialCfgParam *serial_cfg_new = (struct SerialCfgParam *)configure_info->private_data;
SerialCfgParamCheck(serial_cfg, serial_cfg_new);
}
@ -276,25 +276,21 @@ static uint32 Stm32SerialInit(struct SerialDriver *serial_drv, struct BusConfigu
if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_8) {
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
}
else if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_9) {
} else if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_9) {
USART_InitStructure.USART_WordLength = USART_WordLength_9b;
}
if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_1){
USART_InitStructure.USART_StopBits = USART_StopBits_1;
}
else if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_2){
} else if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_2) {
USART_InitStructure.USART_StopBits = USART_StopBits_2;
}
if (serial_cfg->data_cfg.serial_parity_mode == PARITY_NONE){
if (serial_cfg->data_cfg.serial_parity_mode == PARITY_NONE) {
USART_InitStructure.USART_Parity = USART_Parity_No;
}
else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_ODD){
} else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_ODD) {
USART_InitStructure.USART_Parity = USART_Parity_Odd;
}
else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_EVEN){
} else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_EVEN) {
USART_InitStructure.USART_Parity = USART_Parity_Even;
}
@ -352,7 +348,7 @@ static int Stm32SerialGetchar(struct SerialHardwareDevice *serial_dev)
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
int ch = -1;
if (serial_hw_cfg->uart_device->SR & USART_FLAG_RXNE) {
if (serial_hw_cfg->uart_device->SR & USART_FLAG_RXNE) {
ch = serial_hw_cfg->uart_device->DR & 0xff;
}
@ -379,8 +375,7 @@ static void DmaRxDoneIsr(struct Stm32Usart *serial, struct SerialDriver *serial_
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
if (DMA_GetFlagStatus(dma->RxStream, dma->RxFlag) != RESET)
{
if (DMA_GetFlagStatus(dma->RxStream, dma->RxFlag) != RESET) {
x_base level = CriticalAreaLock();
x_size_t recv_len = dma->SettingRecvLen - dma->LastRecvIndex;
@ -399,17 +394,17 @@ static void UartIsr(struct Stm32Usart *serial, struct SerialDriver *serial_drv,
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
if(USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_RXNE) != RESET){
if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_RXNE) != RESET) {
SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND);
USART_ClearITPendingBit(serial_hw_cfg->uart_device, USART_IT_RXNE);
}
if(USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_IDLE) != RESET){
if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_IDLE) != RESET) {
DmaUartRxIdleIsr(serial_dev, dma, serial_hw_cfg->uart_device);
}
if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_TC) != RESET){
if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_TC) != RESET) {
USART_ClearITPendingBit(serial_hw_cfg->uart_device, USART_IT_TC);
}
if (USART_GetFlagStatus(serial_hw_cfg->uart_device, USART_FLAG_ORE) == SET){
if (USART_GetFlagStatus(serial_hw_cfg->uart_device, USART_FLAG_ORE) == SET) {
USART_ReceiveData(serial_hw_cfg->uart_device);
}
}
@ -560,15 +555,15 @@ static uint32 Stm32SerialDrvConfigure(void *drv, struct BusConfigureInfo *config
switch (configure_info->configure_cmd)
{
case OPE_INT:
ret = Stm32SerialInit(serial_drv, configure_info);
break;
case OPE_CFG:
serial_operation_cmd = *(int *)configure_info->private_data;
ret = Stm32SerialConfigure(serial_drv, serial_operation_cmd);
break;
default:
break;
case OPE_INT:
ret = Stm32SerialInit(serial_drv, configure_info);
break;
case OPE_CFG:
serial_operation_cmd = *(int *)configure_info->private_data;
ret = Stm32SerialConfigure(serial_drv, serial_operation_cmd);
break;
default:
break;
}
return ret;
@ -605,21 +600,21 @@ static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver
/*Init the serial bus */
ret = SerialBusInit(serial_bus, bus_name);
if(EOK != ret){
if (EOK != ret) {
KPrintf("hw_serial_init SerialBusInit error %d\n", ret);
return ERROR;
}
/*Init the serial driver*/
ret = SerialDriverInit(serial_driver, drv_name);
if(EOK != ret){
if (EOK != ret) {
KPrintf("hw_serial_init SerialDriverInit error %d\n", ret);
return ERROR;
}
/*Attach the serial driver to the serial bus*/
ret = SerialDriverAttachToBus(drv_name, bus_name);
if(EOK != ret) {
if (EOK != ret) {
KPrintf("hw_serial_init SerialDriverAttachToBus error %d\n", ret);
return ERROR;
}
@ -633,13 +628,13 @@ static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *
x_err_t ret = EOK;
ret = SerialDeviceRegister(serial_device, serial_param, dev_name);
if(EOK != ret) {
if (EOK != ret) {
KPrintf("hw_serial_init SerialDeviceInit device %s error %d\n", dev_name, ret);
return ERROR;
}
ret = SerialDeviceAttachToBus(dev_name, bus_name);
if(EOK != ret) {
if (EOK != ret) {
KPrintf("hw_serial_init SerialDeviceAttachToBus device %s error %d\n", dev_name, ret);
return ERROR;
}
@ -682,14 +677,14 @@ int Stm32HwUsartInit(void)
NVIC_Configuration(serial_hw_cfg_1.irq);
ret = BoardSerialBusInit(&serial_1.SerialBus, &serial_driver_1, SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1);
if(EOK != ret){
ret = BoardSerialBusInit(&serial_1.serial_bus, &serial_driver_1, SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1);
if (EOK != ret) {
KPrintf("Stm32HwUsartInit usart1 error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device_1, (void *)&serial_cfg_1, SERIAL_BUS_NAME_1, SERIAL_1_DEVICE_NAME_0);
if(EOK != ret){
if (EOK != ret) {
KPrintf("Stm32HwUsartInit usart1 error ret %u\n", ret);
return ERROR;
}
@ -723,14 +718,14 @@ int Stm32HwUsartInit(void)
NVIC_Configuration(serial_hw_cfg_2.irq);
ret = BoardSerialBusInit(&serial_2.SerialBus, &serial_driver_2, SERIAL_BUS_NAME_2, SERIAL_DRV_NAME_2);
if(EOK != ret){
ret = BoardSerialBusInit(&serial_2.serial_bus, &serial_driver_2, SERIAL_BUS_NAME_2, SERIAL_DRV_NAME_2);
if (EOK != ret) {
KPrintf("Stm32HwUsartInit usart2 error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device_2, (void *)&serial_cfg_2, SERIAL_BUS_NAME_2, SERIAL_2_DEVICE_NAME_0);
if(EOK != ret){
if (EOK != ret) {
KPrintf("Stm32HwUsartInit usart2 error ret %u\n", ret);
return ERROR;
}
@ -764,14 +759,14 @@ int Stm32HwUsartInit(void)
NVIC_Configuration(serial_hw_cfg_3.irq);
ret = BoardSerialBusInit(&serial_3.SerialBus, &serial_driver_3, SERIAL_BUS_NAME_3, SERIAL_DRV_NAME_3);
if(EOK != ret){
ret = BoardSerialBusInit(&serial_3.serial_bus, &serial_driver_3, SERIAL_BUS_NAME_3, SERIAL_DRV_NAME_3);
if (EOK != ret) {
KPrintf("Stm32HwUsartInit usart3 error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device_3, (void *)&serial_cfg_3, SERIAL_BUS_NAME_3, SERIAL_3_DEVICE_NAME_0);
if(EOK != ret){
if (EOK != ret) {
KPrintf("Stm32HwUsartInit usart3 error ret %u\n", ret);
return ERROR;
}
@ -805,14 +800,14 @@ int Stm32HwUsartInit(void)
NVIC_Configuration(serial_hw_cfg_4.irq);
ret = BoardSerialBusInit(&serial_4.SerialBus, &serial_driver_4, SERIAL_BUS_NAME_4, SERIAL_DRV_NAME_4);
if(EOK != ret){
ret = BoardSerialBusInit(&serial_4.serial_bus, &serial_driver_4, SERIAL_BUS_NAME_4, SERIAL_DRV_NAME_4);
if (EOK != ret) {
KPrintf("Stm32HwUsartInit usart4 error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device_4, (void *)&serial_cfg_4, SERIAL_BUS_NAME_4, SERIAL_4_DEVICE_NAME_0);
if(EOK != ret) {
if (EOK != ret) {
KPrintf("Stm32HwUsartInit usart4 error ret %u\n", ret);
return ERROR;
}
@ -846,14 +841,14 @@ int Stm32HwUsartInit(void)
NVIC_Configuration(serial_hw_cfg_5.irq);
ret = BoardSerialBusInit(&serial_5.SerialBus, &serial_driver_5, SERIAL_BUS_NAME_5, SERIAL_DRV_NAME_5);
if(EOK != ret){
ret = BoardSerialBusInit(&serial_5.serial_bus, &serial_driver_5, SERIAL_BUS_NAME_5, SERIAL_DRV_NAME_5);
if (EOK != ret) {
KPrintf("Stm32HwUsartInit usart5 error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device_5, (void *)&serial_cfg_5, SERIAL_BUS_NAME_5, SERIAL_5_DEVICE_NAME_0);
if(EOK != ret){
if (EOK != ret) {
KPrintf("Stm32HwUsartInit usart5 error ret %u\n", ret);
return ERROR;
}

10
board/stm32f407-st-discovery/third_party_driver/usb/connect_usb.c
View File

@ -39,11 +39,11 @@ static uint32 UdiskCloseNewApi(void *dev)
/*manage the usb device operations*/
static const struct UsbDevDone dev_done =
{
.open = UdiskOpenNewApi,
.close = UdiskCloseNewApi,
.write = UdiskWirte_new_api,
.read = UdiskRead_new_api,
{
.open = UdiskOpenNewApi,
.close = UdiskCloseNewApi,
.write = UdiskWirte_new_api,
.read = UdiskRead_new_api,
};
/*Init usb bus*/

26
board/stm32f407-st-discovery/third_party_driver/watchdog/connect_wdg.c
View File

@ -64,16 +64,16 @@ static uint32 WdtConfigure(void *drv, struct BusConfigureInfo *args)
{
switch (args->configure_cmd)
{
case OPER_WDT_SET_TIMEOUT:
if (WdgSet((uint16_t)*(int *)args->private_data) != 0) {
case OPER_WDT_SET_TIMEOUT:
if (WdgSet((uint16_t)*(int *)args->private_data) != 0) {
return ERROR;
}
break;
case OPER_WDT_KEEPALIVE:
IWDG_ReloadCounter();
break;
default:
return ERROR;
}
break;
case OPER_WDT_KEEPALIVE:
IWDG_ReloadCounter();
break;
default:
return ERROR;
}
return EOK;
}
@ -107,12 +107,12 @@ int HwWdtInit(void)
drv.configure = WdtConfigure;
ret = WdtDriverInit(&drv, WDT_DRIVER_NAME);
if(ret != EOK){
if (ret != EOK) {
KPrintf("Watchdog driver init error %d\n", ret);
return ERROR;
}
ret = WdtDriverAttachToBus(WDT_DRIVER_NAME, WDT_BUS_NAME);
if(ret != EOK){
if (ret != EOK) {
KPrintf("Watchdog driver attach error %d\n", ret);
return ERROR;
}
@ -120,12 +120,12 @@ int HwWdtInit(void)
dev.dev_done = &dev_done;
ret = WdtDeviceRegister(&dev, WDT_DEVICE_NAME);
if(ret != EOK){
if (ret != EOK) {
KPrintf("Watchdog device register error %d\n", ret);
return ERROR;
}
ret = WdtDeviceAttachToBus(WDT_DEVICE_NAME, WDT_BUS_NAME);
if(ret != EOK){
if (ret != EOK) {
KPrintf("Watchdog device register error %d\n", ret);
return ERROR;
}

6
board/stm32f407zgt6/third_party_driver/include/connect_usart.h
View File

@ -28,8 +28,8 @@
extern "C" {
#endif
#define KERNEL_CONSOLE_BUS_NAME SERIAL_BUS_NAME_1
#define KERNEL_CONSOLE_DRV_NAME SERIAL_DRV_NAME_1
#define KERNEL_CONSOLE_BUS_NAME SERIAL_BUS_NAME_1
#define KERNEL_CONSOLE_DRV_NAME SERIAL_DRV_NAME_1
#define KERNEL_CONSOLE_DEVICE_NAME SERIAL_1_DEVICE_NAME_0
struct UsartHwCfg
@ -50,7 +50,7 @@ struct Stm32Usart
x_size_t LastRecvIndex;
} dma;
struct SerialBus SerialBus;
struct SerialBus serial_bus;
};
int Stm32HwUsartInit(void);

109
board/stm32f407zgt6/third_party_driver/uart/connect_usart.c
View File

@ -172,38 +172,36 @@ static void NVIC_Configuration(IRQn_Type irq)
NVIC_Init(&NVIC_InitStructure);
}
static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struct SerialCfgParam *serial_cfg_new)
{
struct SerialDataCfg *data_cfg_default = &serial_cfg_default->data_cfg;
struct SerialDataCfg *data_cfg_new = &serial_cfg_new->data_cfg;
if((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) {
if ((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) {
data_cfg_default->serial_baud_rate = data_cfg_new->serial_baud_rate;
}
if((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order)) {
if ((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order)) {
data_cfg_default->serial_bit_order = data_cfg_new->serial_bit_order;
}
if((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)){
if ((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)) {
data_cfg_default->serial_buffer_size = data_cfg_new->serial_buffer_size;
}
if((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits)) {
if ((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits)) {
data_cfg_default->serial_data_bits = data_cfg_new->serial_data_bits;
}
if((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode)){
if ((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode)) {
data_cfg_default->serial_invert_mode = data_cfg_new->serial_invert_mode;
}
if((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)){
if ((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)) {
data_cfg_default->serial_parity_mode = data_cfg_new->serial_parity_mode;
}
if((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)){
if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
}
}
@ -215,7 +213,7 @@ static uint32 Stm32SerialInit(struct SerialDriver *serial_drv, struct BusConfigu
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
if(configure_info->private_data){
if (configure_info->private_data) {
struct SerialCfgParam *serial_cfg_new = (struct SerialCfgParam *)configure_info->private_data;
SerialCfgParamCheck(serial_cfg, serial_cfg_new);
}
@ -226,25 +224,21 @@ static uint32 Stm32SerialInit(struct SerialDriver *serial_drv, struct BusConfigu
if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_8) {
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
}
else if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_9){
} else if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_9) {
USART_InitStructure.USART_WordLength = USART_WordLength_9b;
}
if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_1){
if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_1) {
USART_InitStructure.USART_StopBits = USART_StopBits_1;
}
else if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_2){
} else if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_2) {
USART_InitStructure.USART_StopBits = USART_StopBits_2;
}
if (serial_cfg->data_cfg.serial_parity_mode == PARITY_NONE){
if (serial_cfg->data_cfg.serial_parity_mode == PARITY_NONE) {
USART_InitStructure.USART_Parity = USART_Parity_No;
}
else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_ODD){
} else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_ODD) {
USART_InitStructure.USART_Parity = USART_Parity_Odd;
}
else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_EVEN){
} else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_EVEN) {
USART_InitStructure.USART_Parity = USART_Parity_Even;
}
@ -276,7 +270,6 @@ static uint32 Stm32SerialConfigure(struct SerialDriver *serial_drv, int serial_o
UART_ENABLE_IRQ(serial_hw_cfg->irq);
USART_ITConfig(serial_hw_cfg->uart_device, USART_IT_RXNE, ENABLE);
break;
}
return EOK;
@ -299,7 +292,7 @@ static int Stm32SerialGetchar(struct SerialHardwareDevice *serial_dev)
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
int ch = -1;
if (serial_hw_cfg->uart_device->SR & USART_FLAG_RXNE) {
if (serial_hw_cfg->uart_device->SR & USART_FLAG_RXNE) {
ch = serial_hw_cfg->uart_device->DR & 0xff;
}
@ -312,14 +305,14 @@ static void UartIsr(struct Stm32Usart *serial, struct SerialDriver *serial_drv,
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
if(USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_RXNE) != RESET) {
if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_RXNE) != RESET) {
SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND);
USART_ClearITPendingBit(serial_hw_cfg->uart_device, USART_IT_RXNE);
}
if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_TC) != RESET) {
USART_ClearITPendingBit(serial_hw_cfg->uart_device, USART_IT_TC);
}
if (USART_GetFlagStatus(serial_hw_cfg->uart_device, USART_FLAG_ORE) == SET){
if (USART_GetFlagStatus(serial_hw_cfg->uart_device, USART_FLAG_ORE) == SET) {
USART_ReceiveData(serial_hw_cfg->uart_device);
}
}
@ -329,15 +322,12 @@ struct Stm32Usart serial_1;
struct SerialDriver serial_driver_1;
struct SerialHardwareDevice serial_device_1;
void USART1_IRQHandler(int irq_num, void *arg)
{
UartIsr(&serial_1, &serial_driver_1, &serial_device_1);
}
DECLARE_HW_IRQ(USART1_IRQn, USART1_IRQHandler, NONE);
#endif
#ifdef BSP_USING_USART2
@ -345,15 +335,12 @@ struct Stm32Usart serial_2;
struct SerialDriver serial_driver_2;
struct SerialHardwareDevice serial_device_2;
void USART2_IRQHandler(int irq_num, void *arg)
{
UartIsr(&serial_2, &serial_driver_2, &serial_device_2);
}
DECLARE_HW_IRQ(USART2_IRQn, USART2_IRQHandler, NONE);
#endif
#ifdef BSP_USING_USART3
@ -361,18 +348,14 @@ struct Stm32Usart serial_3;
struct SerialDriver serial_driver_3;
struct SerialHardwareDevice serial_device_3;
void USART3_IRQHandler(int irq_num, void *arg)
{
UartIsr(&serial_3, &serial_driver_3, &serial_device_3);
}
DECLARE_HW_IRQ(USART3_IRQn, USART3_IRQHandler, NONE);
#endif
static uint32 Stm32SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
{
NULL_PARAM_CHECK(drv);
@ -384,15 +367,15 @@ static uint32 Stm32SerialDrvConfigure(void *drv, struct BusConfigureInfo *config
switch (configure_info->configure_cmd)
{
case OPE_INT:
ret = Stm32SerialInit(serial_drv, configure_info);
break;
case OPE_CFG:
serial_operation_cmd = *(int *)configure_info->private_data;
ret = Stm32SerialConfigure(serial_drv, serial_operation_cmd);
break;
default:
break;
case OPE_INT:
ret = Stm32SerialInit(serial_drv, configure_info);
break;
case OPE_CFG:
serial_operation_cmd = *(int *)configure_info->private_data;
ret = Stm32SerialConfigure(serial_drv, serial_operation_cmd);
break;
default:
break;
}
return ret;
@ -429,21 +412,21 @@ static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver
/*Init the serial bus */
ret = SerialBusInit(serial_bus, bus_name);
if(EOK != ret){
if (EOK != ret){
KPrintf("hw_serial_init SerialBusInit error %d\n", ret);
return ERROR;
}
/*Init the serial driver*/
ret = SerialDriverInit(serial_driver, drv_name);
if(EOK != ret){
if (EOK != ret){
KPrintf("hw_serial_init SerialDriverInit error %d\n", ret);
return ERROR;
}
/*Attach the serial driver to the serial bus*/
ret = SerialDriverAttachToBus(drv_name, bus_name);
if(EOK != ret){
if (EOK != ret){
KPrintf("hw_serial_init SerialDriverAttachToBus error %d\n", ret);
return ERROR;
}
@ -457,13 +440,13 @@ static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *
x_err_t ret = EOK;
ret = SerialDeviceRegister(serial_device, serial_param, dev_name);
if(EOK != ret){
if (EOK != ret){
KPrintf("hw_serial_init SerialDeviceInit device %s error %d\n", dev_name, ret);
return ERROR;
}
ret = SerialDeviceAttachToBus(dev_name, bus_name);
if(EOK != ret) {
if (EOK != ret) {
KPrintf("hw_serial_init SerialDeviceAttachToBus device %s error %d\n", dev_name, ret);
return ERROR;
}
@ -505,14 +488,14 @@ int Stm32HwUsartInit(void)
NVIC_Configuration(serial_hw_cfg_1.irq);
ret = BoardSerialBusInit(&serial_1.SerialBus, &serial_driver_1, SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1);
if(EOK != ret) {
ret = BoardSerialBusInit(&serial_1.serial_bus, &serial_driver_1, SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1);
if (EOK != ret) {
KPrintf("Stm32HwUsartInit usart1 error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device_1, (void *)&serial_cfg_1, SERIAL_BUS_NAME_1, SERIAL_1_DEVICE_NAME_0);
if(EOK != ret) {
if (EOK != ret) {
KPrintf("Stm32HwUsartInit usart1 error ret %u\n", ret);
return ERROR;
}
@ -545,14 +528,14 @@ int Stm32HwUsartInit(void)
NVIC_Configuration(serial_hw_cfg_2.irq);
ret = BoardSerialBusInit(&serial_2.SerialBus, &serial_driver_2, SERIAL_BUS_NAME_2, SERIAL_DRV_NAME_2);
if(EOK != ret){
ret = BoardSerialBusInit(&serial_2.serial_bus, &serial_driver_2, SERIAL_BUS_NAME_2, SERIAL_DRV_NAME_2);
if (EOK != ret) {
KPrintf("Stm32HwUsartInit usart2 error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device_2, (void *)&serial_cfg_2, SERIAL_BUS_NAME_2, SERIAL_2_DEVICE_NAME_0);
if(EOK != ret){
if (EOK != ret) {
KPrintf("Stm32HwUsartInit usart2 error ret %u\n", ret);
return ERROR;
}
@ -585,14 +568,14 @@ int Stm32HwUsartInit(void)
NVIC_Configuration(serial_hw_cfg_3.irq);
ret = BoardSerialBusInit(&serial_3.SerialBus, &serial_driver_3, SERIAL_BUS_NAME_3, SERIAL_DRV_NAME_3);
if(EOK != ret){
ret = BoardSerialBusInit(&serial_3.serial_bus, &serial_driver_3, SERIAL_BUS_NAME_3, SERIAL_DRV_NAME_3);
if (EOK != ret) {
KPrintf("Stm32HwUsartInit usart3 error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device_3, (void *)&serial_cfg_3, SERIAL_BUS_NAME_3, SERIAL_3_DEVICE_NAME_0);
if(EOK != ret){
if (EOK != ret) {
KPrintf("Stm32HwUsartInit usart3 error ret %u\n", ret);
return ERROR;
}
@ -626,14 +609,14 @@ int Stm32HwUsartInit(void)
NVIC_Configuration(serial_hw_cfg_4.irq);
ret = BoardSerialBusInit(&serial_4.SerialBus, &serial_driver_4, SERIAL_BUS_NAME_4, SERIAL_DRV_NAME_4);
if(EOK != ret){
ret = BoardSerialBusInit(&serial_4.serial_bus, &serial_driver_4, SERIAL_BUS_NAME_4, SERIAL_DRV_NAME_4);
if (EOK != ret) {
KPrintf("Stm32HwUsartInit usart4 error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device_4, (void *)&serial_cfg_4, SERIAL_BUS_NAME_4, SERIAL_4_DEVICE_NAME_0);
if(EOK != ret){
if (EOK != ret) {
KPrintf("Stm32HwUsartInit usart4 error ret %u\n", ret);
return ERROR;
}
@ -667,14 +650,14 @@ int Stm32HwUsartInit(void)
NVIC_Configuration(serial_hw_cfg_5.irq);
ret = BoardSerialBusInit(&serial_5.SerialBus, &serial_driver_5, SERIAL_BUS_NAME_5, SERIAL_DRV_NAME_5);
if(EOK != ret){
ret = BoardSerialBusInit(&serial_5.serial_bus, &serial_driver_5, SERIAL_BUS_NAME_5, SERIAL_DRV_NAME_5);
if (EOK != ret) {
KPrintf("Stm32HwUsartInit usart5 error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device_5, (void *)&serial_cfg_5, SERIAL_BUS_NAME_5, SERIAL_5_DEVICE_NAME_0);
if(EOK != ret){
if (EOK != ret) {
KPrintf("Stm32HwUsartInit usart5 error ret %u\n", ret);
return ERROR;
}

4
kernel/include/xs_assign.h
View File

@ -31,8 +31,8 @@
extern "C" {
#endif
#define MERGE_FLAG(src, flag) *(src) |= flag
#define CLEAR_FLAG(src, flag) *(src) &= ~flag
#define MERGE_FLAG(src, flag) (*(src) |= flag)
#define CLEAR_FLAG(src, flag) (*(src) &= ~flag)
extern struct Assign Assign;

5
kernel/include/xs_delay.h
View File

@ -30,13 +30,14 @@
#define TASK_DELAY_INACTIVE 0
#define TASK_DELAY_ACTIVE 1
struct Delay {
struct Delay
{
struct TaskDescriptor *task;
x_ticks_t ticks;
uint8 status;
DoubleLinklistType link;
};
typedef struct Delay *delay_t;
typedef struct Delay *DelayType;
x_err_t KTaskSetDelay(struct TaskDescriptor *task, x_ticks_t ticks);
x_err_t KTaskUnSetDelay(struct TaskDescriptor *task);

80
kernel/include/xs_kdevice.h
View File

@ -36,54 +36,54 @@
extern "C" {
#endif
#define OSIGN_OPER_CLOSE (0U << 0)
#define OSIGN_OPER_RDONLY (1U << 0)
#define OSIGN_OPER_WRONLY (1U << 1)
#define OSIGN_OPER_RDWR (OSIGN_OPER_WRONLY| OSIGN_OPER_RDONLY )
#define OSIGN_OPER_OPEN (1U << 3)
#define OSIGN_OPER_MASK 0xf0f
#define OSIGN_OPER_CLOSE (0U << 0)
#define OSIGN_OPER_RDONLY (1U << 0)
#define OSIGN_OPER_WRONLY (1U << 1)
#define OSIGN_OPER_RDWR (OSIGN_OPER_WRONLY| OSIGN_OPER_RDONLY )
#define OSIGN_OPER_OPEN (1U << 3)
#define OSIGN_OPER_MASK 0xf0f
#define SIGN_OPER_DEACTIVATE (0U << 0)
#define SIGN_OPER_RDONLY (1U << 0)
#define SIGN_OPER_WRONLY (1U << 1)
#define SIGN_OPER_RDWR (SIGN_OPER_RDONLY|SIGN_OPER_WRONLY)
#define SIGN_OPER_REMOVABLE (1U << 2)
#define SIGN_OPER_STANDALONE (1U << 3)
#define SIGN_OPER_ACTIVATED (1U << 4)
#define SIGN_OPER_SUSPENDED (1U << 5)
#define SIGN_OPER_STREAM (1U << 6)
#define SIGN_OPER_INT_RX (1U << 8)
#define SIGN_OPER_DMA_RX (1U << 9)
#define SIGN_OPER_INT_TX (1U << 10)
#define SIGN_OPER_DMA_TX (1U << 11)
#define SIGN_OPER_DEACTIVATE (0U << 0)
#define SIGN_OPER_RDONLY (1U << 0)
#define SIGN_OPER_WRONLY (1U << 1)
#define SIGN_OPER_RDWR (SIGN_OPER_RDONLY|SIGN_OPER_WRONLY)
#define SIGN_OPER_REMOVABLE (1U << 2)
#define SIGN_OPER_STANDALONE (1U << 3)
#define SIGN_OPER_ACTIVATED (1U << 4)
#define SIGN_OPER_SUSPENDED (1U << 5)
#define SIGN_OPER_STREAM (1U << 6)
#define SIGN_OPER_INT_RX (1U << 8)
#define SIGN_OPER_DMA_RX (1U << 9)
#define SIGN_OPER_INT_TX (1U << 10)
#define SIGN_OPER_DMA_TX (1U << 11)
enum SIGN_OPER
enum SIGN_OPER
{
OPER_RESUME = 0x01,
OPER_SUSPEND = 0x02,
OPER_CONFIG = 0x03,
OPER_SET_INT = 0x10,
OPER_CLR_INT = 0x11,
OPER_GET_INT = 0x12,
OPER_CHAR_STREAM = 0x10,
OPER_BLK_GETGEOME = 0x10,
OPER_BLK_SYNC = 0x11,
OPER_BLK_ERASE = 0x12,
OPER_BLK_AUTOREFRESH = 0x13,
OPER_NETIF_GETMAC = 0x10,
OPER_MTD_FORMAT = 0x10,
OPER_RTC_GET_TIME = 0x10,
OPER_RTC_SET_TIME = 0x11,
OPER_RTC_GET_ALARM = 0x12,
OPER_RTC_SET_ALARM = 0x13,
OPER_RESUME = 0x01,
OPER_SUSPEND = 0x02,
OPER_CONFIG = 0x03,
OPER_SET_INT = 0x10,
OPER_CLR_INT = 0x11,
OPER_GET_INT = 0x12,
OPER_CHAR_STREAM = 0x10,
OPER_BLK_GETGEOME = 0x10,
OPER_BLK_SYNC = 0x11,
OPER_BLK_ERASE = 0x12,
OPER_BLK_AUTOREFRESH = 0x13,
OPER_NETIF_GETMAC = 0x10,
OPER_MTD_FORMAT = 0x10,
OPER_RTC_GET_TIME = 0x10,
OPER_RTC_SET_TIME = 0x11,
OPER_RTC_GET_ALARM = 0x12,
OPER_RTC_SET_ALARM = 0x13,
};
struct DeviceBlockArrange
{
uint32 bank_num;
uint32 size_perbank;
uint32 block_size;
uint16 bank_start;
uint32 size_perbank;
uint32 block_size;
uint16 bank_start;
uint16 bank_end;
};

2
kernel/include/xs_ktask.h
View File

@ -86,7 +86,7 @@ struct TaskDyncSchedMember {
uint8 bitmap_row;
#endif
uint32 bitmap_column;
delay_t delay;
DelayType delay;
};
typedef struct TaskDyncSchedMember TaskDyncSchedMembeType;

6
kernel/include/xs_service.h
View File

@ -100,16 +100,16 @@ enum KernelService
KS_USER_END
};
#define SERVICETABLE ((struct Kernel_Service*)SERVICE_TABLE_ADDRESS)
#define SERVICETABLE ((struct KernelService*)SERVICE_TABLE_ADDRESS)
#endif
typedef uintptr_t (*kservice)(uint32_t knum,uintptr_t *param,uint8_t param_num);
struct Kernel_Service
struct KernelService
{
const kservice fun;
const uint8_t param_num;
};
extern struct Kernel_Service g_service_table[] ;
extern struct KernelService g_service_table[] ;
#endif

26
kernel/include/xs_spinlock.h
View File

@ -45,16 +45,16 @@ struct SpinLock
HwSpinlock lock;
};
struct Spin_Lockfileops
{ //定义自旋锁
struct SpinLock node_lock; //原有的自旋锁结构体
void (*SPinLock)(struct Spin_Lockfileops *spinlock);
void (*UnlockSpinLock)(struct Spin_Lockfileops *spinlock);
void (*UnlockSpinLockIrqRestore)(struct Spin_Lockfileops *spinlock, x_base level);
x_base (*SpinLockIrqSave)(struct Spin_Lockfileops *spinlock);
struct SpinLockfileOps
{ //define spin lock
struct SpinLock node_lock; //last spin lock node struct
void (*SPinLock)(struct SpinLockfileOps *spinlock);
void (*UnlockSpinLock)(struct SpinLockfileOps *spinlock);
void (*UnlockSpinLockIrqRestore)(struct SpinLockfileOps *spinlock, x_base level);
x_base (*SpinLockIrqSave)(struct SpinLockfileOps *spinlock);
};
extern struct Spin_Lockfileops spinlock;
extern struct SpinLockfileOps spinlock;
extern HwSpinlock _CriticalLock;
void InitHwSpinlock(HwSpinlock *lock);
@ -82,11 +82,11 @@ void ExecSecondaryCpuIdleKtask(void);
#ifdef ARCH_SMP
struct SpinLock;
void InitSpinLock(struct Spin_Lockfileops * spinlock);
void _SpinLock(struct Spin_Lockfileops * spinlock);
void _UnlockSpinLock(struct Spin_Lockfileops * spinlock);
x_base _SpinLockIrqSave(struct Spin_Lockfileops * spinlock);
void _UnlockSpinLockIrqRestore(struct Spin_Lockfileops * spinlock, x_base level);
void InitSpinLock(struct SpinLockfileOps * spinlock);
void _SpinLock(struct SpinLockfileOps * spinlock);
void _UnlockSpinLock(struct SpinLockfileOps * spinlock);
x_base _SpinLockIrqSave(struct SpinLockfileOps * spinlock);
void _UnlockSpinLockIrqRestore(struct SpinLockfileOps * spinlock, x_base level);
#else
#define InitSpinLock(lock) /* nothing */

2
kernel/kernel_service/xs_service.c
View File

@ -554,7 +554,7 @@ uintptr_t KsStatfs(uint32_t knum,uintptr_t *param, uint8_t num )
}
#endif
struct Kernel_Service g_service_table[256] __attribute__ ((section (".g_service_table"))) =
struct KernelService g_service_table[256] __attribute__ ((section (".g_service_table"))) =
{
[KS_USER_PRINT_INFO] = { KsPrintInfo, 1 },

10
kernel/kernel_test/test_gatherblock.c
View File

@ -30,9 +30,9 @@ static uint8 mempool[2048];
static struct MemGather gm;
static GatherMemType gm_d;
#define TASK_PRIORITY 25
#define TASK_STACK_SIZE 2048
#define TASK_TIMESLICE 5
#define TASK_PRIORITY 25
#define TASK_STACK_SIZE 2048
#define TASK_TIMESLICE 5
/* thread control pointer */
static int32 tid1;
@ -284,9 +284,9 @@ void GatherblockLimitTest(char *name, int count, int blocksize){
}
#ifdef ARCH_ARM
#define CACHE_COUNT 1024
#define CACHE_COUNT 1024
#else
#define CACHE_COUNT 8000
#define CACHE_COUNT 8000
#endif
struct MemGather *pools[CACHE_COUNT];

2
kernel/kernel_test/test_hwtimer.c
View File

@ -59,7 +59,7 @@ void TimeoutCb(void* param){
hwtimer_dev->hwtimer_param.repeat = 1;
hwtimer_dev->hwtimer_param.period_millisecond = 3000;
hwtimer_dev->hwtimer_param.cb_info.param = NULL;
hwtimer_dev->hwtimer_param.cb_info.TimeoutCb = TimeoutCb;
hwtimer_dev->hwtimer_param.cb_info.timeout_callback = timeout_callback;
BusDevOpen(dev);

8
kernel/kernel_test/test_i2c.c
View File

@ -29,10 +29,10 @@
* shell cmd param：i2c device name,if null means default i2c device name
*/
#define HS_I2C_BUS_NAME I2C_BUS_NAME_1 /* I2C bus name */
#define HS_I2C_DEV_NAME I2C_1_DEVICE_NAME_0/* I2C device name */
#define HS_I2C_DRV_NAME I2C_DRV_NAME_1 /* I2C driver name */
#define ADDR 0x44 /* slave address */
#define HS_I2C_BUS_NAME I2C_BUS_NAME_1 /* I2C bus name */
#define HS_I2C_DEV_NAME I2C_1_DEVICE_NAME_0/* I2C device name */
#define HS_I2C_DRV_NAME I2C_DRV_NAME_1 /* I2C driver name */
#define ADDR 0x44 /* slave address */
static struct Bus *i2c_bus = NONE; /* I2C bus handle */

4
kernel/thread/ktask.c
View File

@ -42,8 +42,8 @@ DoubleLinklistType xiaoshan_task_head ={&xiaoshan_task_head, &xiaoshan_task_head
#define BITMAP_CACULATE_COLUMN_OFFSET(offset,n) (offset = n / 8)
#endif
#define BITMAP_SETCOLUMN(column,offset) (column = 1 << offset)
#define BITMAP_SETROW(row,offset) (row = 1 << offset)
#define BITMAP_SETCOLUMN(column,offset) (column = (1 << offset))
#define BITMAP_SETROW(row,offset) (row = (1 << offset))
#define BITLOWMASK_3BIT (0x7)

12
kernel/thread/lock.c
View File

@ -24,7 +24,7 @@
#include <xs_assign.h>
#ifdef ARCH_SMP
struct Spin_Lockfileops spinlock;
struct SpinLockfileOps spinlock;
/*
* lock scheduler
*/
@ -50,7 +50,7 @@ static void EnablePreempt(void)
EnableLocalInterrupt(lock);
}
void InitSpinLock( struct Spin_Lockfileops * spinlock)
void InitSpinLock( struct SpinLockfileOps * spinlock)
{
InitHwSpinlock(&spinlock->node_lock.lock);
spinlock->SPinLock = _SpinLock;
@ -60,19 +60,19 @@ static void EnablePreempt(void)
}
void _SpinLock(struct Spin_Lockfileops * spinlock)
void _SpinLock(struct SpinLockfileOps * spinlock)
{
DisablePreempt();
HwLockSpinlock(&spinlock->node_lock.lock);
}
void _UnlockSpinLock(struct Spin_Lockfileops * spinlock)
void _UnlockSpinLock(struct SpinLockfileOps * spinlock)
{
HwUnlockSpinlock(&spinlock->node_lock.lock);
EnablePreempt();
}
x_base _SpinLockIrqSave(struct Spin_Lockfileops * spinlock)
x_base _SpinLockIrqSave(struct SpinLockfileOps * spinlock)
{
x_base lock = 0;
@ -84,7 +84,7 @@ x_base _SpinLockIrqSave(struct Spin_Lockfileops * spinlock)
return lock;
}
void _UnlockSpinLockIrqRestore(struct Spin_Lockfileops * spinlock, x_base lock)
void _UnlockSpinLockIrqRestore(struct SpinLockfileOps * spinlock, x_base lock)
{
HwUnlockSpinlock(&spinlock->node_lock.lock);
EnableLocalInterrupt(lock);

6
kernel/thread/msgqueue.c
View File

@ -25,9 +25,9 @@
DECLARE_ID_MANAGER(k_mq_id_manager, ID_NUM_MAX);
DoubleLinklistType k_mq_list = {&k_mq_list, &k_mq_list};
struct mq_message
struct MqMessage
{
struct mq_message *next;
struct MqMessage *next;
};
static struct MsgQueue *GetMsgQueueById(int32 id)
@ -195,7 +195,7 @@ static x_err_t _MsgQueueRecv(struct MsgQueue *mq,
x_ubase lock = 0;
uint32 tick_delta = 0;
int32 timeout = 0;
struct mq_message *msg = NONE;
struct MqMessage *msg = NONE;
struct TaskDescriptor *task = NONE;
NULL_PARAM_CHECK(mq);

1
resources/can/dev_can.c
View File

@ -39,7 +39,6 @@ HardwareDevType CanDeviceFind(const char *dev_name, enum DevType dev_type)
DoubleLinklistType *node = NONE;
DoubleLinklistType *head = &candev_linklist;
for (node = head->node_next; node != head; node = node->node_next) {
device = SYS_DOUBLE_LINKLIST_ENTRY(node, struct HardwareDev, dev_link);
if ((!strcmp(device->dev_name, dev_name)) && (dev_type == device->dev_type)) {
return device;

2
resources/include/dev_hwtimer.h
View File

@ -29,7 +29,7 @@ extern "C" {
struct HwtimerCallBackInfo
{
void (*TimeoutCb) (void* param);
void (*timeout_callback) (void* param);
void *param;
};

2
resources/include/dev_i2c.h
View File

@ -33,7 +33,7 @@ extern "C" {
#define I2C_ADDR_10BIT (1u << 2)
#define I2C_NO_START (1u << 4)
#define I2C_IGNORE_NACK (1u << 5)
#define I2C_NO_READ_ACK (1u << 6)
#define I2C_NO_READ_ACK (1u << 6)
struct I2cDataStandard
{

6
resources/spi/sd_card_spi/sd_spi.c
View File

@ -222,8 +222,7 @@ static uint32 SdHwInit(SpiSdDeviceType spi_sd_dev)
SpiDevConfigureCs(&spi_sd_dev->spi_dev->haldev, 0, 1);
SD_TIMEOUT(start_time, 3 * SPI_SD_TIMEOUT_NUM);
}
while(0x01 != g_sd_cmd_param.sd_respone_data[0]);
}while(0x01 != g_sd_cmd_param.sd_respone_data[0]);
return EOK;
}
@ -268,8 +267,7 @@ static uint32 SdConfirmType(SpiSdDeviceType spi_sd_dev)
}
SD_TIMEOUT(start_time, 3 * SPI_SD_TIMEOUT_NUM);
}
while(0xAA != g_sd_cmd_param.sd_respone_data[4]);
}while(0xAA != g_sd_cmd_param.sd_respone_data[4]);
return EOK;
}