303 lines
7.8 KiB
C
303 lines
7.8 KiB
C
/* Copyright 2018 Canaan Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file
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* @brief Universal Asynchronous Receiver/Transmitter (UART)
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*
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* The UART peripheral supports the following features:
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*
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* - 8-N-1 and 8-N-2 formats: 8 data bits, no parity bit, 1 start
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* bit, 1 or 2 stop bits
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*
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* - 8-entry transmit and receive FIFO buffers with programmable
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* watermark interrupts
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*
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* - 16× Rx oversampling with 2/3 majority voting per bit
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*
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* The UART peripheral does not support hardware flow control or
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* other modem control signals, or synchronous serial data
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* tranfesrs.
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*
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* @note UART RAM Layout
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*
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* | Address | Name | Description |
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* |-----------|----------|---------------------------------|
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* | 0x000 | txdata | Transmit data register |
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* | 0x004 | rxdata | Receive data register |
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* | 0x008 | txctrl | Transmit control register |
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* | 0x00C | rxctrl | Receive control register |
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* | 0x010 | ie | UART interrupt enable |
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* | 0x014 | ip | UART Interrupt pending |
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* | 0x018 | div | Baud rate divisor |
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*
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*/
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/**
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* @file hardware_uarths.h
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* @brief add from Canaan k210 SDK
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* https://canaan-creative.com/developer
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* @version 1.0
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* @author AIIT XUOS Lab
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* @date 2021-04-25
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*/
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#ifndef __HARDWARE_UARTHS_H__
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#define __HARDWARE_UARTHS_H__
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#include <platform.h>
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#include "plic.h"
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#include <stddef.h>
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* clang-format off */
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/* Register address offsets */
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#define UARTHS_REG_TXFIFO (0x00)
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#define UARTHS_REG_RXFIFO (0x04)
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#define UARTHS_REG_TXCTRL (0x08)
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#define UARTHS_REG_RXCTRL (0x0c)
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#define UARTHS_REG_IE (0x10)
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#define UARTHS_REG_IP (0x14)
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#define UARTHS_REG_DIV (0x18)
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/* TXCTRL register */
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#define UARTHS_TXEN (0x01)
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#define UARTHS_TXWM(x) (((x) & 0xffff) << 16)
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/* RXCTRL register */
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#define UARTHS_RXEN (0x01)
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#define UARTHS_RXWM(x) (((x) & 0xffff) << 16)
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/* IP register */
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#define UARTHS_IP_TXWM (0x01)
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#define UARTHS_IP_RXWM (0x02)
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/* clang-format on */
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typedef struct _uarths_txdata
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{
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/* Bits [7:0] is data */
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uint32_t data : 8;
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/* Bits [30:8] is 0 */
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uint32_t zero : 23;
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/* Bit 31 is full status */
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uint32_t full : 1;
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} __attribute__((packed, aligned(4))) uarths_txdata_t;
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typedef struct _uarths_rxdata
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{
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/* Bits [7:0] is data */
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uint32_t data : 8;
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/* Bits [30:8] is 0 */
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uint32_t zero : 23;
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/* Bit 31 is empty status */
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uint32_t empty : 1;
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} __attribute__((packed, aligned(4))) uarths_rxdata_t;
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typedef struct _uarths_txctrl
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{
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/* Bit 0 is txen, controls whether the Tx channel is active. */
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uint32_t txen : 1;
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/* Bit 1 is nstop, 0 for one stop bit and 1 for two stop bits */
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uint32_t nstop : 1;
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/* Bits [15:2] is reserved */
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uint32_t resv0 : 14;
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/* Bits [18:16] is threshold of interrupt triggers */
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uint32_t txcnt : 3;
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/* Bits [31:19] is reserved */
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uint32_t resv1 : 13;
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} __attribute__((packed, aligned(4))) uarths_txctrl_t;
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typedef struct _uarths_rxctrl
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{
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/* Bit 0 is txen, controls whether the Tx channel is active. */
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uint32_t rxen : 1;
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/* Bits [15:1] is reserved */
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uint32_t resv0 : 15;
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/* Bits [18:16] is threshold of interrupt triggers */
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uint32_t rxcnt : 3;
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/* Bits [31:19] is reserved */
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uint32_t resv1 : 13;
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} __attribute__((packed, aligned(4))) uarths_rxctrl_t;
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typedef struct _uarths_ip
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{
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/* Bit 0 is txwm, raised less than txcnt */
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uint32_t txwm : 1;
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/* Bit 1 is txwm, raised greater than rxcnt */
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uint32_t rxwm : 1;
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/* Bits [31:2] is 0 */
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uint32_t zero : 30;
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} __attribute__((packed, aligned(4))) uarths_ip_t;
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typedef struct _uarths_ie
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{
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/* Bit 0 is txwm, raised less than txcnt */
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uint32_t txwm : 1;
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/* Bit 1 is txwm, raised greater than rxcnt */
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uint32_t rxwm : 1;
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/* Bits [31:2] is 0 */
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uint32_t zero : 30;
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} __attribute__((packed, aligned(4))) uarths_ie_t;
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typedef struct _uarths_div
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{
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/* Bits [31:2] is baud rate divisor register */
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uint32_t div : 16;
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/* Bits [31:16] is 0 */
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uint32_t zero : 16;
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} __attribute__((packed, aligned(4))) uarths_div_t;
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typedef struct _uarths
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{
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/* Address offset 0x00 */
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uarths_txdata_t txdata;
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/* Address offset 0x04 */
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uarths_rxdata_t rxdata;
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/* Address offset 0x08 */
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uarths_txctrl_t txctrl;
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/* Address offset 0x0c */
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uarths_rxctrl_t rxctrl;
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/* Address offset 0x10 */
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uarths_ie_t ie;
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/* Address offset 0x14 */
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uarths_ip_t ip;
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/* Address offset 0x18 */
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uarths_div_t div;
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} __attribute__((packed, aligned(4))) UarthsT;
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typedef enum _uarths_interrupt_mode
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{
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UARTHS_SEND = 1,
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UARTHS_RECEIVE = 2,
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UARTHS_SEND_RECEIVE = 3,
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} uarths_interrupt_mode_t;
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typedef enum _uarths_stopbit
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{
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UARTHS_STOP_1,
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UARTHS_STOP_2
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} uarths_stopbit_t;
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extern volatile UarthsT *const uarths;
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/**
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* @brief Initialization Core UART
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*
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* @return result
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* - 0 Success
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* - Other Fail
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*/
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void uarths_init(void);
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/**
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* @brief Put a char to UART
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*
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* @param[in] c The char to put
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*
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* @note If c is '\n', a '\r' will be appended automatically
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*
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* @return result
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* - 0 Success
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* - Other Fail
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*/
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int uarths_putchar(char c);
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/**
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* @brief Send a string to UART
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*
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* @param[in] s The string to send
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*
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* @note The string must ending with '\0'
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*
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* @return result
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* - 0 Success
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* - Other Fail
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*/
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int uarths_puts(const char *s);
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/**
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* @brief Get a byte from UART
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*
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* @return byte as int type from UART
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*/
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int uarths_getc(void);
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/**
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* @brief Set uarths interrupt callback
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*
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* @param[in] interrupt_mode Interrupt mode recevice or send
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* @param[in] uarths_callback Interrupt callback
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* @param[in] ctx Param of callback
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* @param[in] priority Interrupt priority
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*
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*/
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void uarths_set_irq(uarths_interrupt_mode_t interrupt_mode, plic_irq_callback_t uarths_callback, void *ctx, uint32_t priority);
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/**
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* @brief Uarths receive data
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*
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* @param[in] buf The data received
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* @param[in] BufLen The length of data
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*
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* @return Number of received data
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*/
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size_t uarths_receive_data(uint8_t *buf, size_t BufLen);
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/**
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* @brief Uarths receive data
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*
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* @param[in] buf The data sended
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* @param[in] BufLen The length of data
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*
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* @return Number of sended data
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*/
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size_t uarths_send_data(const uint8_t *buf, size_t BufLen);
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/**
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* @brief Get interrupt mode
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*
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* @return Mode of interrupt
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*/
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uarths_interrupt_mode_t uarths_get_interrupt_mode(void);
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/**
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* @brief Set uarths baud rate and stopbit
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*
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* @param[in] BaudRate The baud rate
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* @param[in] stopbit The stopbit of data
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*
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*/
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void uarths_config(uint32_t BaudRate, uarths_stopbit_t stopbit);
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/**
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* @brief Set uart interrupt condition
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*
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* @param[in] interrupt_mode The interrupt mode
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* @param[in] cnt The count of tigger
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*
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*/
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void uarths_set_interrupt_cnt(uarths_interrupt_mode_t interrupt_mode, uint8_t cnt);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __UARTHS_H__ */
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