474 lines
16 KiB
C
474 lines
16 KiB
C
/*
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* Copyright (c) 2020 RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-03-18 ZYH first version
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*/
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/**
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* @file connect_spi.c
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* @brief support aiit-riscv64-board spi function and register to bus framework
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* @version 1.0
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* @author AIIT XUOS Lab
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* @date 2021-04-25
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*/
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/*************************************************
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File name: connect_spi.c
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Description: support aiit-riscv64-board spi configure and spi bus register function
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Others: take RT-Thread v4.0.2/bsp/k210/driver/drv_spi.c for references
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https://github.com/RT-Thread/rt-thread/tree/v4.0.2
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History:
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1. Date: 2021-04-25
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Author: AIIT XUOS Lab
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Modification:
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1. support aiit-riscv64-board spi configure, write and read
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2. support aiit-riscv64-board spi bus device and driver register
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*************************************************/
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#include <connect_spi.h>
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#include <dmac.h>
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#include <drv_io_config.h>
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#include <gpiohs.h>
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#include <hardware_spi.h>
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#include <string.h>
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#include <sysctl.h>
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#include <utils.h>
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#ifdef BSP_SPI1_USING_SS0
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#define SPI_DEVICE_SLAVE_ID_0 0
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#endif
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#ifdef BSP_SPI1_USING_SS1
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#define SPI_DEVICE_SLAVE_ID_1 1
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#endif
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#ifdef BSP_SPI1_USING_SS2
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#define SPI_DEVICE_SLAVE_ID_2 2
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#endif
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#ifdef BSP_SPI1_USING_SS3
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#define SPI_DEVICE_SLAVE_ID_3 3
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#endif
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static volatile spi_t *const spi_instance[4] =
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{
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(volatile spi_t *)SPI0_BASE_ADDR,
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(volatile spi_t *)SPI1_BASE_ADDR,
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(volatile spi_t *)SPI_SLAVE_BASE_ADDR,
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(volatile spi_t *)SPI3_BASE_ADDR
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};
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void __spi_set_tmod(uint8_t spi_num, uint32_t tmod)
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{
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CHECK(spi_num < SPI_DEVICE_MAX);
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volatile spi_t *spi_handle = spi[spi_num];
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uint8_t tmod_offset = 0;
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switch(spi_num)
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{
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case 0:
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case 1:
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case 2:
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tmod_offset = 8;
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break;
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case 3:
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default:
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tmod_offset = 10;
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break;
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}
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set_bit(&spi_handle->ctrlr0, 3 << tmod_offset, tmod << tmod_offset);
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}
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/*Init the spi sdk intetface */
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static uint32 SpiSdkInit(struct SpiDriver *spi_drv)
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{
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NULL_PARAM_CHECK(spi_drv);
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uint8 cs_gpio_pin, cs_select_id;
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uint32 max_frequency;
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SpiDeviceParam *dev_param = (SpiDeviceParam *)(spi_drv->driver.private_data);
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cs_gpio_pin = dev_param->spi_slave_param->spi_cs_gpio_pin;
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cs_select_id = dev_param->spi_slave_param->spi_cs_select_id;
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gpiohs_set_drive_mode(cs_select_id, GPIO_DM_OUTPUT);//Set the cs pin as output
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gpiohs_set_pin(cs_gpio_pin, GPIO_PV_HIGH);//set the cs gpio high
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spi_init(dev_param->spi_dma_param->spi_master_id,
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dev_param->spi_master_param->spi_work_mode & SPI_MODE_3,
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dev_param->spi_master_param->spi_frame_format,
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dev_param->spi_master_param->spi_data_bit_width,
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dev_param->spi_master_param->spi_data_endian);
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max_frequency = (dev_param->spi_master_param->spi_maxfrequency < SPI_MAX_CLOCK) ? dev_param->spi_master_param->spi_maxfrequency : SPI_MAX_CLOCK;
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uint32 real_freq = spi_set_clk_rate(dev_param->spi_dma_param->spi_master_id, max_frequency);
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return EOK;
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}
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static uint32 SpiSdkCfg(struct SpiDriver *spi_drv, struct SpiMasterParam *spi_param)
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{
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NULL_PARAM_CHECK(spi_drv);
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NULL_PARAM_CHECK(spi_param);
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SpiDeviceParam *dev_param = (SpiDeviceParam *)(spi_drv->driver.private_data);
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dev_param->spi_master_param = spi_param;
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dev_param->spi_master_param->spi_work_mode = dev_param->spi_master_param->spi_work_mode & SPI_MODE_MASK;
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dev_param->spi_master_param->spi_frame_format = SPI_FF_STANDARD;
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return EOK;
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}
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/*Configure the spi device param, make sure struct (configure_info->private_data) = (SpiMasterParam)*/
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static uint32 SpiDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
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{
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NULL_PARAM_CHECK(drv);
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NULL_PARAM_CHECK(configure_info);
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x_err_t ret = EOK;
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struct SpiDriver *spi_drv = (struct SpiDriver *)drv;
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struct SpiMasterParam *spi_param;
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switch (configure_info->configure_cmd)
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{
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case OPE_INT:
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ret = SpiSdkInit(spi_drv);
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break;
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case OPE_CFG:
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spi_param = (struct SpiMasterParam *)configure_info->private_data;
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ret = SpiSdkCfg(spi_drv, spi_param);
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break;
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default:
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break;
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}
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return ret;
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}
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static uint32 SpiWriteData(struct SpiHardwareDevice *spi_dev, struct SpiDataStandard *spi_datacfg)
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{
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SpiDeviceParam *dev_param = (SpiDeviceParam *)(spi_dev->haldev.private_data);
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uint8 device_id = dev_param->spi_slave_param->spi_slave_id;
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uint8 device_master_id = dev_param->spi_dma_param->spi_master_id;
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uint8 cs_gpio_pin = dev_param->spi_slave_param->spi_cs_gpio_pin;
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while (NONE != spi_datacfg)
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{
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uint32_t * tx_buff = NONE;
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int i;
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x_ubase dummy = 0xFFFFFFFFU;
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__spi_set_tmod(device_master_id, SPI_TMOD_TRANS_RECV);
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if (spi_datacfg->spi_chip_select) {
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gpiohs_set_pin(cs_gpio_pin, GPIO_PV_LOW);
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}
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if (spi_datacfg->length) {
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spi_instance[device_master_id]->dmacr = 0x3;
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spi_instance[device_master_id]->ssienr = 0x01;
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sysctl_dma_select(dev_param->spi_dma_param->spi_dmac_txchannel, SYSCTL_DMA_SELECT_SSI0_TX_REQ + device_master_id * 2);
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sysctl_dma_select(dev_param->spi_dma_param->spi_dmac_rxchannel, SYSCTL_DMA_SELECT_SSI0_RX_REQ + device_master_id* 2);
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dmac_set_single_mode(dev_param->spi_dma_param->spi_dmac_rxchannel, (void *)(&spi_instance[device_master_id]->dr[0]), &dummy, DMAC_ADDR_NOCHANGE, DMAC_ADDR_NOCHANGE,
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DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, spi_datacfg->length);
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if (!spi_datacfg->tx_buff) {
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dmac_set_single_mode(dev_param->spi_dma_param->spi_dmac_txchannel, &dummy, (void *)(&spi_instance[device_master_id]->dr[0]), DMAC_ADDR_NOCHANGE, DMAC_ADDR_NOCHANGE,
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DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, spi_datacfg->length);
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} else {
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tx_buff = x_malloc(spi_datacfg->length * 4);
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if (!tx_buff) {
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goto transfer_done;
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}
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for (i = 0; i < spi_datacfg->length; i++) {
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tx_buff[i] = ((uint8_t *)spi_datacfg->tx_buff)[i];
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}
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dmac_set_single_mode(dev_param->spi_dma_param->spi_dmac_txchannel, tx_buff, (void *)(&spi_instance[device_master_id]->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,
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DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, spi_datacfg->length);
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}
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spi_instance[device_master_id]->ser = 1U << dev_param->spi_slave_param->spi_cs_select_id;
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dmac_wait_done(dev_param->spi_dma_param->spi_dmac_txchannel);
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dmac_wait_done(dev_param->spi_dma_param->spi_dmac_rxchannel);
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spi_instance[device_master_id]->ser = 0x00;
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spi_instance[device_master_id]->ssienr = 0x00;
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transfer_done:
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if (tx_buff) {
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x_free(tx_buff);
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}
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}
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if (spi_datacfg->spi_cs_release) {
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gpiohs_set_pin(cs_gpio_pin, GPIO_PV_HIGH);
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}
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spi_datacfg = spi_datacfg->next;
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}
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return spi_datacfg->length;
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}
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static uint32 SpiReadData(struct SpiHardwareDevice *spi_dev, struct SpiDataStandard *spi_datacfg)
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{
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SpiDeviceParam *dev_param = (SpiDeviceParam *)(spi_dev->haldev.private_data);
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uint8 device_id = dev_param->spi_slave_param->spi_slave_id;
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uint8 device_master_id = dev_param->spi_dma_param->spi_master_id;
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uint8 cs_gpio_pin = dev_param->spi_slave_param->spi_cs_gpio_pin;
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while (NONE != spi_datacfg)
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{
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uint32_t * rx_buff = NONE;
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int i;
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x_ubase dummy = 0xFFFFFFFFU;
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__spi_set_tmod(device_master_id, SPI_TMOD_TRANS_RECV);
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if (spi_datacfg->spi_chip_select) {
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gpiohs_set_pin(cs_gpio_pin, GPIO_PV_LOW);
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}
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if (spi_datacfg->length) {
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spi_instance[device_master_id]->dmacr = 0x3;
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spi_instance[device_master_id]->ssienr = 0x01;
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sysctl_dma_select(dev_param->spi_dma_param->spi_dmac_txchannel, SYSCTL_DMA_SELECT_SSI0_TX_REQ + device_master_id * 2);
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sysctl_dma_select(dev_param->spi_dma_param->spi_dmac_rxchannel, SYSCTL_DMA_SELECT_SSI0_RX_REQ + device_master_id* 2);
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dmac_set_single_mode(dev_param->spi_dma_param->spi_dmac_txchannel, &dummy, (void *)(&spi_instance[device_master_id]->dr[0]), DMAC_ADDR_NOCHANGE, DMAC_ADDR_NOCHANGE,
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DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, spi_datacfg->length);
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if (!spi_datacfg->rx_buff) {
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dmac_set_single_mode(dev_param->spi_dma_param->spi_dmac_rxchannel, (void *)(&spi_instance[device_master_id]->dr[0]), &dummy, DMAC_ADDR_NOCHANGE, DMAC_ADDR_NOCHANGE,
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DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, spi_datacfg->length);
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} else {
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rx_buff = x_calloc(spi_datacfg->length * 4, 1);
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if(!rx_buff)
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{
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goto transfer_done;
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}
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dmac_set_single_mode(dev_param->spi_dma_param->spi_dmac_rxchannel, (void *)(&spi_instance[device_master_id]->dr[0]), rx_buff, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT,
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DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, spi_datacfg->length);
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}
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spi_instance[device_master_id]->ser = 1U << dev_param->spi_slave_param->spi_cs_select_id;
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dmac_wait_done(dev_param->spi_dma_param->spi_dmac_txchannel);
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dmac_wait_done(dev_param->spi_dma_param->spi_dmac_rxchannel);
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spi_instance[device_master_id]->ser = 0x00;
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spi_instance[device_master_id]->ssienr = 0x00;
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if (spi_datacfg->rx_buff) {
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for (i = 0; i < spi_datacfg->length; i++) {
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((uint8_t *)spi_datacfg->rx_buff)[i] = (uint8_t)rx_buff[i];
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}
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}
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transfer_done:
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if (rx_buff) {
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x_free(rx_buff);
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}
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}
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if (spi_datacfg->spi_cs_release) {
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gpiohs_set_pin(cs_gpio_pin, GPIO_PV_HIGH);
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}
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spi_datacfg = spi_datacfg->next;
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}
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return spi_datacfg->length;
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}
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/*manage the spi device operations*/
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static const struct SpiDevDone spi_dev_done =
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{
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.open = NONE,
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.close = NONE,
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.write = SpiWriteData,
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.read = SpiReadData,
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};
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static int BoardSpiBusInit(struct SpiBus *spi_bus, struct SpiDriver *spi_driver)
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{
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x_err_t ret = EOK;
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/*Init the spi bus */
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ret = SpiBusInit(spi_bus, SPI_BUS_NAME_1);
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if (EOK != ret) {
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KPrintf("Board_Spi_init SpiBusInit error %d\n", ret);
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return ERROR;
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}
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/*Init the spi driver*/
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ret = SpiDriverInit(spi_driver, SPI_1_DRV_NAME);
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if (EOK != ret) {
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KPrintf("Board_Spi_init SpiDriverInit error %d\n", ret);
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return ERROR;
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}
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/*Attach the spi driver to the spi bus*/
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ret = SpiDriverAttachToBus(SPI_1_DRV_NAME, SPI_BUS_NAME_1);
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if (EOK != ret) {
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KPrintf("Board_Spi_init SpiDriverAttachToBus error %d\n", ret);
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return ERROR;
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}
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return ret;
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}
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/*Attach the spi device to the spi bus*/
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static int BoardSpiDevBend(struct SpiDmaParam *spi_initparam)
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{
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x_err_t ret = EOK;
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#ifdef BSP_SPI1_USING_SS0
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static struct SpiHardwareDevice spi_device0;
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memset(&spi_device0, 0, sizeof(struct SpiHardwareDevice));
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static struct SpiSlaveParam spi_slaveparam0;
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memset(&spi_slaveparam0, 0, sizeof(struct SpiSlaveParam));
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spi_slaveparam0.spi_slave_id = SPI_DEVICE_SLAVE_ID_0;
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spi_slaveparam0.spi_cs_gpio_pin = SPI1_CS0_PIN;
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spi_slaveparam0.spi_cs_select_id = SPI_CHIP_SELECT_0;
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spi_device0.spi_param.spi_dma_param = spi_initparam;
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spi_device0.spi_param.spi_slave_param = &spi_slaveparam0;
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spi_device0.spi_dev_done = &(spi_dev_done);
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ret = SpiDeviceRegister(&spi_device0, (void *)(&spi_device0.spi_param), SPI_1_DEVICE_NAME_0);
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if (EOK != ret) {
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KPrintf("Board_Spi_init SpiDeviceInit device %s error %d\n", SPI_1_DEVICE_NAME_0, ret);
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return ERROR;
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}
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ret = SpiDeviceAttachToBus(SPI_1_DEVICE_NAME_0, SPI_BUS_NAME_1);
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if (EOK != ret) {
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KPrintf("Board_Spi_init SpiDeviceAttachToBus device %s error %d\n", SPI_1_DEVICE_NAME_0, ret);
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return ERROR;
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}
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#endif
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#ifdef BSP_SPI1_USING_SS1
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static struct SpiHardwareDevice spi_device1;
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memset(&spi_device1, 0, sizeof(struct SpiHardwareDevice));
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static struct SpiSlaveParam spi_slaveparam1;
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memset(&spi_slaveparam1, 0, sizeof(struct SpiSlaveParam));
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spi_slaveparam1.spi_slave_id = SPI_DEVICE_SLAVE_ID_1;
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spi_slaveparam1.spi_cs_gpio_pin = SPI1_CS1_PIN;
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spi_slaveparam1.spi_cs_select_id = SPI_CHIP_SELECT_1;
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spi_device1.spi_param.spi_dma_param = spi_initparam;
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spi_device1.spi_param.spi_slave_param = &spi_slaveparam1;
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spi_device1.spi_dev_done = &(spi_dev_done);
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ret = SpiDeviceRegister(&spi_device1, (void *)(&spi_device1.spi_param), SPI_1_DEVICE_NAME_1);
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if (EOK != ret) {
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KPrintf("Board_Spi_init SpiDeviceInit device %s error %d\n", SPI_1_DEVICE_NAME_1, ret);
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return ERROR;
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}
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ret = SpiDeviceAttachToBus(SPI_1_DEVICE_NAME_1, SPI_BUS_NAME_1);
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if (EOK != ret) {
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KPrintf("Board_Spi_init SpiDeviceAttachToBus device %s error %d\n", SPI_1_DEVICE_NAME_1, ret);
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return ERROR;
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}
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#endif
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#ifdef BSP_SPI1_USING_SS2
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static struct SpiHardwareDevice spi_device2;
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memset(&spi_device2, 0, sizeof(struct SpiHardwareDevice));
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spi_initparam->spi_slave_id[SPI_DEVICE_SLAVE_ID_2] = SPI_DEVICE_SLAVE_ID_2;
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spi_initparam->spi_cs_gpio_pin[SPI_DEVICE_SLAVE_ID_2] = SPI1_CS2_PIN;
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spi_initparam->spi_cs_select_id[SPI_DEVICE_SLAVE_ID_2] = SPI_CHIP_SELECT_2;
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spi_device2.spi_dev_done = &(spi_dev_done);
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ret = SpiDeviceRegister(&spi_device2, (void *)(&spi_device2.spi_param), SPI_1_DEVICE_NAME_2);
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if (EOK != ret) {
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KPrintf("Board_Spi_init SpiDeviceInit device %s error %d\n", SPI_1_DEVICE_NAME_2, ret);
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return ERROR;
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}
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ret = SpiDeviceAttachToBus(SPI_1_DEVICE_NAME_2, SPI_BUS_NAME_1);
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if (EOK != ret) {
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KPrintf("Board_Spi_init SpiDeviceAttachToBus device %s error %d\n", SPI_1_DEVICE_NAME_2, ret);
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return ERROR;
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}
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#endif
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#ifdef BSP_SPI1_USING_SS3
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static struct SpiHardwareDevice spi_device3;
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memset(&spi_device3, 0, sizeof(struct SpiHardwareDevice));
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spi_initparam->spi_slave_id[SPI_DEVICE_SLAVE_ID_3] = SPI_DEVICE_SLAVE_ID_3;
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spi_initparam->spi_cs_gpio_pin[SPI_DEVICE_SLAVE_ID_3] = SPI1_CS3_PIN;
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spi_initparam->spi_cs_select_id[SPI_DEVICE_SLAVE_ID_3] = SPI_CHIP_SELECT_3;
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spi_device3.spi_dev_done = &(spi_dev_done);
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ret = SpiDeviceRegister(&spi_device3, (void *)(&spi_device3.spi_param), SPI_1_DEVICE_NAME_3);
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if (EOK != ret) {
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KPrintf("Board_Spi_init SpiDeviceInit device %s error %d\n", SPI_1_DEVICE_NAME_3, ret);
|
|
return ERROR;
|
|
}
|
|
|
|
ret = SpiDeviceAttachToBus(SPI_1_DEVICE_NAME_3, SPI_BUS_NAME_1);
|
|
if (EOK != ret) {
|
|
KPrintf("Board_Spi_init SpiDeviceAttachToBus device %s error %d\n", SPI_1_DEVICE_NAME_3, ret);
|
|
return ERROR;
|
|
}
|
|
#endif
|
|
return ret;
|
|
}
|
|
|
|
/*RISC-V 64 BOARD SPI INIT*/
|
|
int HwSpiInit(void)
|
|
{
|
|
x_err_t ret = EOK;
|
|
static struct SpiDmaParam spi_initparam;
|
|
memset(&spi_initparam, 0, sizeof(struct SpiDmaParam));
|
|
|
|
#ifdef BSP_USING_SPI1
|
|
|
|
static struct SpiBus spi_bus;
|
|
memset(&spi_bus, 0, sizeof(struct SpiBus));
|
|
|
|
static struct SpiDriver spi_driver;
|
|
memset(&spi_driver, 0, sizeof(struct SpiDriver));
|
|
|
|
spi_initparam.spi_master_id = SPI_DEVICE_1;
|
|
spi_initparam.spi_dmac_txchannel = DMAC_CHANNEL1;
|
|
spi_initparam.spi_dmac_rxchannel = DMAC_CHANNEL2;
|
|
|
|
spi_driver.configure = &(SpiDrvConfigure);
|
|
|
|
ret = BoardSpiBusInit(&spi_bus, &spi_driver);
|
|
if (EOK != ret) {
|
|
KPrintf("Board_Spi_Init error ret %u\n", ret);
|
|
return ERROR;
|
|
}
|
|
|
|
ret = BoardSpiDevBend(&spi_initparam);
|
|
if (EOK != ret) {
|
|
KPrintf("Board_Spi_Init error ret %u\n", ret);
|
|
return ERROR;
|
|
}
|
|
#endif
|
|
return ret;
|
|
}
|